JP2009064341A - Data transfer system - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a data transfer system with improved data transfer efficiency when writing in data from another input/output device into a non-shared region and reading out the data to another input/output device. <P>SOLUTION: The data transfer system consists of an input/output device 110 and an input/output device 120 which are connected in data transferable manner through a PCI bus. The input/output device 110 includes: an address allocation change part which changes the memory address of RAM 113 allocated to an address space of the PCI bus based on a transfer request from the input/output device 120 to which write-in to the non-shared region 113b on the RAM 113 or reading from the non-shared region 113b is specified, and makes part or the whole of the non-shared region 113b a shared region; and a transfer response generation part which generates a transfer response sent out to the input/output device 120 through a PCI bus controller 112 as a response to the transfer request after changing of the memory address by the address allocation change part. <P>COPYRIGHT: (C)2009,JPO&INPIT

Description

  The present invention relates to a data transfer system, and more particularly, to an improvement in a data transfer system that transfers data between input / output devices via an input / output bus such as a PCI bus.

  In a data transfer system that transfers data between input / output devices via an input / output bus, the input / output bus controller in each input / output device controls the data transfer performed via the input / output bus. For example, in a multi-function peripheral (MFP) having a color copy function, a facsimile communication function, a network scanner function, and a network printer function, data transfer performed via a PCI (Peripheral Component Interconnect) bus is controlled by the PCI controller. (For example, patent document 1).

  In general, in data transfer performed via an input / output bus, the size of an address space composed of bus addresses of the input / output bus is determined by the number of address lines used by the input / output bus controller during data transfer. The address assignment in the case of assigning the memory address of the memory in the input / output device to such an address space is appropriately determined for each input / output device according to the purpose and function of the input / output device. For this reason, when the size of the address space is small compared to the number of bits of the memory address or when the number of memory addresses allocated to the address space is small, some input / output devices cannot be shared with other input / output devices. An area will be created. That is, no memory address is assigned to the address space of the input / output bus, and a memory area (non-shared area) that is not shared with other input / output devices is generated. In a conventional data transfer system, when data is written from other input / output devices to such a non-shared area, the shared area of the transfer destination input / output device, that is, a memory area in which a memory address is assigned to the address space. The data on the shared area written by the transfer source input / output device must be moved to the non-shared area in the transfer destination input / output device. When data is read from the non-shared area to another input / output device, first, the transfer source input / output device moves the data on the non-shared area to the shared area, and then moves the data that has been moved to the shared area. The transfer destination I / O device had to be read. Therefore, there is a problem that the data transfer efficiency is not good.

For example, Patent Documents 2 and 3 describe a technique for transferring data between input / output devices via a PCI bus.
JP 2006-309444 A JP 2001-243206 A International Publication WO2004 / 085522

  As described above, the conventional data transfer system has a problem that data transfer efficiency is not good when data is transferred between input / output devices.

  The present invention has been made in view of the above circumstances, and an object of the present invention is to provide a data transfer system with improved data transfer efficiency when transferring data between input / output devices. In particular, an object of the present invention is to provide a data transfer system with improved transfer efficiency when data is written from another input / output device to a non-shared area or when data is read from the non-shared area to another input / output device.

  A data transfer system according to a first aspect of the present invention is a data transfer system comprising a first input / output device and a second input / output device connected so as to be able to transfer data via an input / output bus. An input / output device is connected to the first input / output bus controller that controls data transfer through the input / output bus, and the first input / output bus controller is communicable via the first local bus, and the memory address is A first memory including a shared area assigned to the address space of the input / output bus and a non-shared area not assigned to the address space, wherein the second input / output device includes the input / output device. A second input / output bus controller that controls data transfer by the bus and a second input / output bus controller that are communicably connected via a second local bus A data transfer system having a memory. The first input / output device is assigned to the address space based on a transfer request from the second input / output device that is designated to write to or read from the non-shared area. Address allocation changing means for changing the memory address of the first memory, and the second input via the first input / output bus controller as a response to the transfer request after the memory address is changed by the address assignment changing means. Transfer response generating means for generating a transfer response sent to the input / output device.

  In this data transfer system, when the second input / output device writes data to the non-shared area of the first input / output device, or when the second input / output device reads data from the non-shared area, the first The memory address of the first memory is changed by the input / output device. At this time, the memory address assigned to the address space of the input / output bus is changed, and a transfer response is sent to the second input / output device after the memory address is changed. Therefore, since it is not necessary to move data in the first input / output device at the time of data transfer, when data is written from another input / output device to the non-shared area on the first memory or another input from the non-shared area is performed. It is possible to improve transfer efficiency when reading data to the output device.

  In addition to the above configuration, the data transfer system according to the second aspect of the present invention assigns the address assignment based on the transfer completion notification from the second input / output device sent by the first input / output device after data transfer. Address allocation restoring means for restoring the memory address changed by the changing means is provided.

  In the data transfer system according to the third aspect of the present invention, in addition to the above-described configuration, the transfer response generation means sends a transfer request from an input / output device other than the second input / output device during data transfer by the second input / output device. When received, a non-permission response indicating that transfer is not possible is generated as a response to the transfer request.

  In addition to the above configuration, the data transfer system according to the fourth aspect of the present invention is the case where the address assignment changing means is a case of writing data in which a continuous memory address is specified as a write destination, and the memory specified as the write destination When the number of addresses is larger than the number of memory addresses in the shared area, the memory address is changed during the continuous writing of data.

  According to the data transfer system of the present invention, since it is not necessary to move data in the first input / output device at the time of data transfer, when data is written from another input / output device to the non-shared area on the first memory. In addition, it is possible to improve the data transfer efficiency when data is read from the non-shared area to another input / output device.

  FIG. 1 is a system diagram showing a configuration example of a data transfer system according to an embodiment of the present invention. A digital multi-function peripheral 100 is shown as an example of a data transfer system. The digital multi-function peripheral 100 is a data processing device having a color copy function, a facsimile communication function, a network scanner function, and a network printer function, and includes a plurality of input / output devices connected to be able to transfer data via the PCI bus 10. Is done.

  That is, the digital multi-function peripheral 100 includes a PCI bus 10, a PCI bridge 11, an MFP controller 20, a scanner 26, a color image processing board 30, a network board 40, a printer controller 50, and a printer 55.

  The PCI bus 10 is an input / output bus as a data transmission path, and includes a data line for transmitting data, an address line for transmitting a memory address, a control line for transmitting a command, and the like. For example, an input / output bus having a 32-bit bus width is used as the PCI bus 10.

  The PCI bridge 11 is a circuit for connecting two PCI buses 10 to each other. In this example, the MFP controller 20 and the network controller 40 are connected to one PCI bus 10, and the color image processing board 30 and the printer controller 50 are connected to the other PCI bus 10. Such two PCI buses 10 function as one input / output bus by the PCI bridge 11.

  The MFP controller 20 is an input / output device that functions as a host device in this data transfer system, and the color image processing board 30, the network board 40, and the printer controller 50 are all input / output devices that function as slave devices. .

  The MFP controller 20 includes a CPU 21, a PCI host controller 22, an interrupt control register 23, and a RAM 24 that are communicably connected to each other via a local bus 25.

  In the MFP controller 20, for example, color image data read from a document by the scanner 26 is subjected to image processing such as color space conversion and data compression, and the color image processing board 30 or the network board via the PCI bus 10. 40, or an operation of transmitting / receiving color image data by facsimile is performed.

  The scanner 26 is an optical image reading device that generates image data by optical reading of a document or the like. For example, color image data including a plurality of color components is generated.

  A CPU (Central Processing Unit) 21 is a control unit that controls the PCI host controller 22, the interrupt control register 23, and the RAM 24 via the local bus 25. The PCI host controller 22 is an input / output bus controller that controls data transfer via the PCI bus 10, and controls communication performed with a slave device via the PCI bus 10.

  The interrupt control register 23 is a memory for writing an interrupt request when one of the input / output devices constituting the data transfer system generates an interrupt to another input / output device. The interrupt control register 23 is connected to the CPU 21 of its own device and the CPUs 31, 41 and 51 of other slave devices through interrupt signal lines. When an interrupt request is written by the interrupt request source device, the interrupt request destination device An interrupt signal is output.

  A RAM (Random Access Memory) 24 is a rewritable volatile semiconductor memory for holding communication data and image data, and is a memory that requires power supply for storage and holding. The RAM 24 is used as a main memory of the CPU 21, for example. In the RAM 24, a command area is provided as a memory area for a slave device connected to the own device via the PCI bus 10 to write a command. The CPU 21 can communicate with the slave device using this command area.

  The color image processing board 30 includes a circuit board having a CPU 31, a PCI bus controller 32, and a RAM 33 that are communicably connected to each other via a local bus 34, and performs image processing for printing image data on paper. . For example, the process of converting the color image data composed of the color component YCrCb transferred from the MFP controller 20 via the PCI bus 10 into the image data composed of the color component CMYK, or two more pieces of the image data subjected to the color space conversion. A gradation reduction process is performed.

  The CPU 31 is a control unit that controls the PCI bus controller 32 and the RAM 33 via the local bus 34 and incorporates an interrupt controller. The interrupt controller generates an interrupt when an interrupt signal is received from the interrupt control register 23 via the interrupt signal line.

  The PCI bus controller 32 is an input / output bus controller that controls data transfer via the PCI bus 10, and controls communication performed with other devices via the PCI bus 10. The RAM 33 is a rewritable volatile semiconductor memory, and is used as a main memory of the CPU 31, for example.

  The network board 40 is composed of a circuit board having a CPU 41, a PCI bus controller 42, and a RAM 43 that are communicably connected to each other via a local bus 44, and communicates with a client PC 46 on a communication network 45 such as a LAN. ing. For example, in order to send the image data transferred from the MFP controller 20 via the PCI bus 10 to the client PC 46 or to send the image data received from the client PC 46 by facsimile, the image data is sent via the PCI bus 10. A process of transferring to the MFP controller 20 is performed. Alternatively, a process of transferring the image data to the printer controller 50 via the PCI bus 10 is performed in order to output the image data received from the client PC 46 to the printer.

  The printer controller 50 includes a CPU 51, a PCI bus controller 52, and a RAM 53 that are communicably connected to each other via a local bus 54. The printer controller 50 performs an operation of controlling the printer 55 based on image data transferred from another device. Yes. For example, the printer 55 is controlled based on the image data transferred from the color image processing board 30 via the PCI bus 10 or transferred from the network board 40. The printer 55 is an image printing apparatus that prints image data on paper or the like.

  In the data transfer system configured as described above, the MFP controller 20 functioning as a host device is connected to each of the slave devices of the color image processing board 30, the network board 40, and the printer controller 50 connected via the PCI bus 10. Can communicate with each other, and these slave devices can also communicate with each other without going through the MFP controller 20.

  Here, as an example of data transfer performed between the slave devices without using the MFP controller 20, the color image processing board 30 is a slave device on the command transmission side, and the printer controller 50 is a slave device on the command reception side. The data transfer will be described.

  First, the CPU 31 of the color image processing board 30 on the command transmission side uses its own device provided on the RAM 53 of the printer controller 50 on the command reception side, that is, the semaphore of the command area for the color image processing board 30. To win. Specifically, the CPU 31 writes information for acquiring the right to use the command area in a predetermined area on the RAM 33 of its own device, whereby a semaphore in the command area on the RAM 53 is acquired.

  Next, the CPU 31 writes a command in the command area on the RAM 53. For writing this command, the PCI bus controller 32 transmits a command to the PCI bus controller 52 of the printer controller 50 via the PCI bus 10, and the command received by the PCI bus controller 52 is stored in the command area on the RAM 53 in the local bus 54. This is done by writing via

  Next, the CPU 31 writes the data to be transferred in the data area on the RAM 53. Specifically, the PCI bus controller 32 transmits data to the PCI bus controller 52 of the printer controller 50 via the PCI bus 10, and the data received by the PCI bus controller 52 is transferred to the local area in the data area on the RAM 53. This is done by writing via.

  When the CPU 31 of the color image processing board 30 on the command transmission side writes the command and data in the RAM 53 on the command reception side in this manner, an interrupt is generated to notify the command controller 50 on the command reception side. . That is, the PCI bus controller 32 writes an interrupt request for causing the printer controller 50 to generate an interrupt to the interrupt control register 23 via the PCI bus 10.

  In writing the interrupt request, the PCI bus controller 32 transmits an interrupt request to the PCI host controller 22 via the PCI bus 10, and the interrupt request received by the PCI host controller 22 is transmitted to the interrupt control register 23 via the local bus 25. This is done by writing.

  When an interrupt request from the color image processing board 30 to the printer controller 50 is set in the interrupt control register 23, an interrupt signal is transmitted from the interrupt control register 23 to the CPU 51 of the printer controller 50 via the interrupt signal line. In this way, when the CPU 31 generates an interrupt to the CPU 51 of the printer controller 50, the completion of writing of the command and data is notified to the printer controller 50.

  On the other hand, the CPU 51 of the printer controller 50 notified of the completion of writing reads the command from the command area for the color image processing board 30 in the RAM 53 and reads the data from the data area.

  Next, the CPU 51 executes processing corresponding to the command read from the command area for the color image processing board 30 on the data read from the data area, and executes the command and data from the command area for the color image processing board 30. Is interrupted to the color image processing board 30 in order to notify the command transmission side that the data has been read out.

  That is, the PCI bus controller 52 writes an interrupt request for causing the color image processing board 30 to generate an interrupt to the interrupt control register 23 via the PCI bus 10.

  For writing the interrupt request, the PCI bus controller 52 transmits an interrupt request to the PCI host controller 22 via the PCI bus 10, and the interrupt request received by the PCI host controller 22 is transmitted to the interrupt control register 23 via the local bus 25. This is done by writing.

  When an interrupt request from the printer controller 50 to the color image processing board 30 is set in the interrupt control register 23, an interrupt signal is transmitted from the interrupt control register 23 to the CPU 31 of the color image processing board 30 via the interrupt signal line.

  When the CPU 31 of the color image processing board 30 receives the interrupt signal from the interrupt control register 23, the CPU 31 of the printer controller 50 determines that the command and data written in the command area for the device itself are no longer necessary. . Then, the CPU 31 writes a command indicating that it is not used in the command area for its own device in the RAM 53 and writes information for returning the right to use the command area in a predetermined area in the RAM 33. The semaphore in the command area is returned and this communication is terminated.

  In this embodiment, in the data transfer between the slave devices performed through the PCI bus 10 in this manner and the data transfer performed between the host device and the slave device, other input / output devices are not shared on the memory. When data is written to the area or when another input / output device reads data from the non-shared area, an operation to change the memory address is performed by the input / output apparatus having the non-shared area.

  FIG. 2 is a block diagram illustrating a configuration example of a main part of the digital multifunction peripheral 100 of FIG. 1, in which input / output devices 110 and 120 connected by the PCI bus 10 are illustrated. The input / output devices 110 and 120 are both host devices or slave devices that constitute the data transfer system.

  Here, among the input / output devices of the MFP controller 20, the color image processing board 30, the network board 40, and the printer controller 50, the input / output device 110 having the shared area 113a and the non-shared area 113b on the RAM 113 is first input. The output device is “device A”. On the other hand, an input / output device 120 different from “device A” is set as a second input / output device “device B”.

  That is, the input / output device 110 includes a CPU 111, a PCI bus controller 112, a shared area 113a, a non-shared area 113b, and a local bus 114. The input / output device 120 includes a CPU 121, a PCI bus controller 122, a RAM 123, and a local bus 124.

  The shared area 113 a is a memory area in which a memory address is assigned to the address space of the PCI bus 10 and is shared with other input / output devices via the PCI bus 10. On the other hand, the non-shared area 113b is a memory area that is not assigned a memory address in the address space of the PCI bus 10 and is not shared with other input / output devices.

  That is, the RAM 113 is a memory composed of a shared area 113a in which the memory address is assigned to the address space of the PCI bus 10 and a non-shared area 113b in which the memory address is not assigned to the address space.

  It is assumed that the digital multifunction peripheral 100 includes one or more such input / output devices 110 and 120. In such data transfer between the input / output devices, the input / output device 120 writes data to the non-shared area 113b of the input / output device 110 and the input / output device 120 reads data from the non-shared area 113b. The memory address of the RAM 113 including the non-shared area 113b is changed.

  More specifically, the memory address of the RAM 113 assigned to the address space of the PCI bus 10 is changed based on a transfer request from the input / output device 120. At that time, the memory address is changed so that a part or all of the non-shared area 113b functions as a shared area.

  In general, the address space of the PCI bus 10 is a virtual space composed of the bus addresses of the PCI bus 10, and the size thereof depends on the number of address lines used when the PCI bus controller transfers data via the PCI bus 10. Is determined.

  In the address space, a memory address allocation area is formed for each input / output device connected to be able to transfer data to each other via the PCI bus 10. For example, an allocation area in which address allocation to the RAM 113 of the input / output device 110 is arranged and an allocation area in which address allocation to the RAM 123 of the input / output device 120 is arranged are formed.

  At this time, when the address space is small and the allocation area is small compared to the number of bits and the storage capacity of the memory address of the RAM, or the allocation area to which the memory address is allocated is small even if the address space size is large In addition, a memory area in which no memory address is assigned to the address space, that is, a non-shared area is generated. In the case of the input / output device 110, a memory address is allocated to the address space only in the allocation area corresponding to the shared area 113a in the memory area in the RAM 113.

  On the other hand, when the allocation area is large, no non-shared area is generated, and all memory addresses of the RAM are allocated to the address space.

  FIG. 3 is a block diagram showing a configuration example of the CPU 111 in the input / output device 110 of FIG. The CPU 111 includes an address assignment change unit 1, a transfer response generation unit 2, a default information storage unit 3, an address assignment storage unit 4, a transfer control unit 5, and an address assignment restoration unit 6.

  The address assignment changing unit 1 is a RAM 113 assigned to the address space of the PCI bus 10 based on a transfer request from the input / output device 120 that is designated to write to the non-shared area 113b or to read from the non-shared area 113b. The operation to change the memory address is performed. In this memory address change, a process is performed in which a memory area that has not been assigned to the address space is used as a shared area, and a memory area that has been assigned a memory address as a shared area is used as a non-shared area.

  In the address assignment changing unit 1, a process of changing the memory address based on an address assignment predetermined as default information is performed. The default information storage unit 3 holds such predetermined address allocation, that is, memory address allocation information for the address space as default information. On the other hand, the address assignment storage unit 4 holds the changed address assignment.

  Here, as the address assignment, it is assumed that a plurality of memory addresses are held in association with different bus addresses of the PCI bus 10, respectively.

  Further, the address allocation changing unit 1 is a case of writing data in which a continuous memory address is specified as a write destination, and the number of memory addresses specified as the write destination is larger than the number of memory addresses in the shared area. In this case, it is assumed that an operation for changing the memory address is performed during the continuous writing of data.

  The transfer response generation unit 2 performs an operation of generating a transfer response based on the transfer request from the input / output device 120. This transfer response is sent to the input / output device 120 via the PCI bus controller 112.

  Specifically, for a transfer request in which writing to the non-shared area 113b or reading from the non-shared area 113b is specified, a transfer response is returned as a response to the transfer request after the memory allocation is changed by the address assignment changing unit 1. It is generated and sent to the input / output device 120.

  The transfer response generation unit 2 includes a non-permission response generation unit 2a. When a transfer request is received from an input / output device other than the input / output device 120 during data transfer by the input / output device 120, the transfer response generation unit 2 A permission response is generated as a response to the transfer request.

  In other words, when there is a transfer request from another input / output device during data transfer, exclusive control is performed by notifying the input / output device that transfer is not possible. Such exclusive control can prevent other input / output devices from erroneously transferring data to a non-shared area on the RAM 113.

  The transfer control unit 5 controls data transfer between the PCI bus controller 112 and the RAM 113 based on the address assignment held in the address assignment storage unit 4.

  The address assignment restoring unit 6 performs an operation of returning the memory address of the RAM 113 changed by the address assignment changing unit 1 to the original state based on the transfer completion notification sent from the input / output device 120 sent after the data transfer. . The operation of returning the memory address to the original state is performed by reading the default information from the default information storage unit 3 and the restored address assignment is written in the address assignment storage unit 4.

  FIG. 4 is a diagram showing an example of the operation in the CPU 111 of FIG. 3, and shows address assignment 3a that is predetermined as default information and changed address assignments 4a and 4b. In the address allocation 3a predetermined as default information, a memory address is allocated to an address space using the memory area A1 on the RAM 113 as a shared area, and a memory area other than the memory area A1, that is, the memory area A2 is not stored. It is a shared area.

  That is, in data transfer performed via the PCI bus 10, another input / output device can write data into the memory area A1 or read data from the memory area A1.

  The address assignment changing unit 1 performs an operation of changing the memory address assigned to the address space based on a transfer request from another input / output device in response to such a predetermined address assignment 3a. . In the address assignment 4a after the change, a part of the memory area A2 that was a non-shared area is assigned to the address space as a shared area B12, and a part of the memory area A1 that was a shared area is assigned to the non-shared area B11. It has become. The other part of the memory area A2 that was the non-shared area is the non-shared area B13 as it is.

  In the changed address assignment 4b, all of the memory area A2 that was the non-shared area is assigned to the address space as the shared area B22, and all of the memory area A1 that was the shared area is the non-shared area B21. It has become.

  In this way, by changing the memory address of the RAM 113 in response to a transfer request from another input / output device, the other input / output device writes data into the memory area A2 which is a non-shared area by default, or Data can be read from the memory area A2.

  FIG. 5 is a sequence diagram illustrating an example of data transfer performed between the input / output devices 110 and 120 of FIG. 2 via the PCI bus 10, and the input / output device 120 may write data to the input / output device 110. It is shown. When data is transferred from the input / output device 120 “device B” to the input / output device 110 “device A” via the PCI bus 10, first, the CPU 121 of the input / output device 120 issues a transmission command as a transfer request, and PCI The data is sent to the input / output device 110 via the bus controller 122 (step S101).

  When receiving the transmission command from the input / output device 120, the CPU 111 of the input / output device 110 changes the address assignment to the RAM 113 based on the transmission command (step S102).

  Next, after changing the address assignment, the CPU 111 issues a response to the transmission command as a transfer response, and sends the response to the input / output device 120 via the PCI bus controller 112 (step S103).

  Upon receiving this response, the CPU 121 writes data to the RAM 113 of the input / output device 110 via the PCI bus controller 122 (step S104).

  Next, when the data writing is completed and the data transfer is completed, the CPU 121 issues a transmission completion command as a transfer completion notification and sends it to the input / output device 110 via the PCI bus controller 122 (steps S105 and S106). .

  When receiving the transmission completion command from the input / output device 120, the CPU 111 of the input / output device 110 returns the address assignment to the original state (step S107). Next, the CPU 111 issues a response to the transmission completion command, and ends this process (step S108).

  The response to the transmission completion command is sent to the input / output device 120 via the PCI bus controller 112. Upon receiving the response from the input / output device 110, the CPU 121 ends this processing based on the reception result.

  According to the present embodiment, it is not necessary to move data in the input / output device 110 during data transfer. Therefore, when data is written from another input / output device to the non-shared area 113b on the RAN 113 or from the non-shared area 113b. It is possible to improve the transfer efficiency when reading data to another input / output device.

  In particular, since the memory address is automatically restored to the original state based on the transfer completion notification from the input / output device 120, it is possible to prevent data from being erroneously written to the RAM 113 by another input / output device after the data transfer is completed. can do. In addition, when data is written with a continuous memory address specified as the write destination and the number of memory addresses specified as the write destination is greater than the number of memory addresses in the shared area, continuous data write Since the memory address is changed during the transfer, the transfer efficiency can be further improved.

  In this embodiment, an example has been described in which the memory address changed by the address assignment changing unit 1 is returned to the original state based on the transfer completion notification from the input / output device 120 sent after data transfer. However, the present invention is not limited to this. For example, when a transfer request from another input / output device is received after the data transfer is completed, the memory address may be returned to the original state based on the reception result of the transfer request.

  In this embodiment, when a transfer request is received from an input / output device other than the input / output device 120 during data transfer by the input / output device 120, a non-permission response is sent as a response to the transfer request. Although an example has been described, the present invention is not limited to this. For example, when a transfer request from another input / output device is received during data transfer, a response to the transfer request is not sent until the data transfer is completed and the memory address of the RAM 113 is returned to the original state. It may be anything.

  In this embodiment, an example in which the CPU transmits and receives data between the PCI bus controller and the RAM has been described. However, the present invention is not limited to this. For example, a DMA (Direct Memory Access) controller is provided in the input / output device, and when this DMA controller operates based on an instruction from the CPU, data is transmitted and received between the PCI bus controller and the RAM without going through the CPU. You may do it. In this way, the CPU load can be reduced by causing the DMA controller to transmit and receive data.

  When data is transmitted / received between the PCI bus controller and the RAM using the DMA controller, if there is a memory area that cannot be accessed by the DMA controller, a work buffer composed of a nonvolatile memory such as SRAM (Static Random Access Memory) It is conceivable that data is once received and transferred.

1 is a system diagram showing a configuration example of a data transfer system according to an embodiment of the present invention, in which a digital multifunction peripheral 100 is shown as an example of a data transfer system. FIG. 2 is a block diagram illustrating a configuration example of a main part of the digital multifunction peripheral 100 of FIG. 1, in which input / output devices 110 and 120 connected by a PCI bus 10 are illustrated. FIG. 3 is a block diagram illustrating a configuration example of a CPU 111 in the input / output device 110 in FIG. 2. It is the figure which showed an example of the operation | movement in CPU111 of FIG. 3, and the predetermined address assignment 3a and the changed address assignments 4a and 4b are shown. FIG. 3 is a sequence diagram showing an example of data transfer performed between the input / output devices 110 and 120 of FIG. 2 via the PCI bus 10.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 Address allocation change part 2 Transfer response production | generation part 3 Default information storage part 4 Address assignment storage part 5 Transfer control part 6 Address assignment restoration part 10 PCI bus 11 PCI bridge 20 MFP controller 21, 31, 41, 51 CPU
22 PCI host controller 23 Interrupt control registers 24, 33, 43, 53 RAM
25, 34, 44, 54 Local bus 26 Scanner 30 Color image processing board 32, 42, 52 PCI bus controller 40 Network board 50 Printer controller 55 Printer 100 Digital multi-function peripheral 110, 120 Input / output devices 111, 121 CPU
112, 122 PCI bus controller 113, 123 RAM
113a Shared area 113b Non-shared area 114, 124 Local bus

Claims (4)

A data transfer system comprising a first input / output device and a second input / output device connected to be able to transfer data via an input / output bus,
The first input / output device is connected to a first input / output bus controller that controls data transfer through the input / output bus, and the first input / output bus controller is communicable via a first local bus. A first memory including a shared area in which a memory address is assigned to the address space of the input / output bus and a non-shared area that is not assigned to the address space;
The second input / output device is connected to a second input / output bus controller that controls data transfer through the input / output bus, and the second input / output bus controller is communicable via a second local bus. A data transfer system having a second memory,
The first input / output device is assigned to the address space based on a transfer request from the second input / output device that is designated to write to or read from the non-shared area. Address assignment changing means for changing the memory address of the first memory;
Transfer response generating means for generating a transfer response sent to the second input / output device via the first input / output bus controller as a response to the transfer request after the memory address is changed by the address allocation changing means; A data transfer system characterized by comprising.   Address assignment restoring means for restoring the memory address changed by the address assignment changing means based on the transfer completion notification from the second input / output apparatus sent by the first input / output device after data transfer. The data transfer system according to claim 1, further comprising:   When the transfer response generation means receives a transfer request from an input / output device other than the second input / output device during the data transfer by the second input / output device, the transfer response generation unit sends an unacceptable response indicating that transfer is impossible. The data transfer system according to claim 1, wherein the data transfer system is generated as a response to.   The address allocation change means is for writing data in which a continuous memory address is specified as a write destination, and the number of memory addresses specified as the write destination is larger than the number of memory addresses in the shared area 2. The data transfer system according to claim 1, wherein the memory address is changed during continuous writing of data.

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