JP6331735B2 - Image processing apparatus and image processing apparatus control method - Google Patents

Description

  The present invention relates to an image processing apparatus and a control method for the image processing apparatus, and more particularly to processing for reducing latency of a memory read.

  In recent years, there has been a tendency to digitize information, and image processing apparatuses such as printers and facsimiles used for outputting digitized information and scanners used for digitizing documents have become indispensable devices. Such an image processing apparatus is often configured as a multifunction machine that can be used as a printer, a facsimile, a scanner, or a copier by providing an imaging function, an image forming function, a communication function, and the like.

  In such an image processing apparatus, there is a process that needs to ensure line isochronism, such as a print process or a scanner process, or a PC (Personal Computer) that converts the format of image data stored in the image processing apparatus. There is also a process that does not require ensuring isochronism of lines and pages. A process that does not require the isochronism of lines and pages may be configured as a separate device (hereinafter referred to as an “optional device”) as an optional function. It may be used by being connected to the bus of the main chip.

  In recent years, the main chip of the image processing apparatus has been replaced with a high-speed serial I / F. On the other hand, the above-described optional device often remains a device of a parallel bus I / F developed in the past. In this case, in order to connect the option device to the bus of the main chip, it is necessary to provide a conversion bridge for converting the high-speed serial I / F and the parallel bus I / F between the option device and the bus of the main chip. is there. When a plurality of option devices are connected to the main chip bus, it is necessary to provide a switch in addition to the conversion bridge.

  When such an optional device is connected to the bus of the main chip via a conversion bridge and a switch, since the distance between the optional device and the main memory is long, the read access latency is further increased and the performance of the memory read is deteriorated. To do.

  Memory read request only when there is a tendency to access the continuous memory area with reference to access history or access characteristic information for the purpose of enabling efficient memory access by the device without increasing memory read latency. In addition to the memory area specified in (1), the data in the memory area continuous to the memory area is read in advance, and if there is no tendency to access the continuous memory area, the data is read only from the specified memory area. Is disclosed (for example, refer to Patent Document 1).

  In addition, for the purpose of improving the isochronism of data and the productivity of a plurality of applications, the memory for storing data is monitored by monitoring the states of a plurality of line memories capable of storing the main scan size of image data. It is disclosed to control the issuance of a memory read request to an arbiter that arbitrates an access request to an access based on the monitoring result of the line memory (see, for example, Patent Document 2).

  In order to reduce the latency of read access in the image processing apparatus as described above, a buffer is provided between the main memory and each optional device connected to the bus of the main chip, and the data in the main memory is used as a buffer. It may be possible to transfer in advance. As a result, the option device may reduce the latency by reading the data transferred to the buffer instead of directly accessing the main memory. However, in this case, it is necessary to provide a buffer and a DMAC (Direct Memory Access Controller) for transferring data to each option device, which increases the circuit scale.

  In the techniques disclosed in Patent Document 1 and Patent Document 2, an increase in circuit scale due to the use of a DMAC and a buffer is not considered.

  The present invention has been made to solve such a problem, and an object of the present invention is to reduce the latency of a memory read by a device connected to the image processing apparatus while suppressing an increase in circuit scale in the image processing apparatus. And

  In order to solve the above problems, an aspect of the present invention is an image processing apparatus including a plurality of image processing units that acquire and process image data from an image storage medium that stores the image data, and the image to be processed A data storage processing unit that reads image data from the image storage medium in accordance with a read command for reading data and stores the read image data in a processing target image storage medium that is a storage medium for storing the image data; A storage medium control unit that stores the predetermined control information in a control information storage medium that stores predetermined control information indicating a storage area in the image storage medium of image data to be acquired by one of the image processing units And a storage area indicated in the predetermined control information among the plurality of image processing units according to the operation status of the plurality of image processing units. Characterized in that it comprises a switching control unit for switching from said processed image storage medium to the image processing unit should get Luo image data so as to acquire image data.

  According to the present invention, it is possible to reduce the latency of memory read by a device connected to the image processing apparatus while suppressing an increase in circuit scale in the image processing apparatus.

1 is a block diagram illustrating a conventional configuration of an image processing apparatus according to an embodiment of the present invention. It is a figure which illustrates the aspect of the memory read access in the image processing apparatus which concerns on embodiment of this invention. It is a figure which illustrates the path | route which connects the main memory 20 and the option device in the image processing apparatus which concerns on embodiment of this invention. It is a figure which illustrates the path | pass in case each of the option device and engine ASIC reads the image data memorize | stored in the main memory as a comparative example of the operation | movement in the image processing apparatus which concerns on embodiment of this invention. FIG. 10 is a sequence diagram illustrating a conventional operation example when the option device reads image data stored in the main memory as a comparative example of the operation in the image processing apparatus according to the embodiment of the present invention. It is a sequence diagram which shows the operation example in case the engine ASIC reads the image data memorize | stored in the main memory in the image processing apparatus which concerns on embodiment of this invention. It is a figure which illustrates the position of the address of the read access set to the DMAC register of engine ASIC in the image processing apparatus which concerns on embodiment of this invention. 1 is a block diagram illustrating a configuration of an image processing apparatus according to an embodiment of the present invention. It is a table which illustrates the information regarding the option device which concerns on embodiment of this invention. It is a flowchart which illustrates the register control by the register control part which concerns on embodiment of this invention. It is a figure which illustrates the header structure of the memory read command of TLP which concerns on embodiment of this invention. It is a flowchart which illustrates the process of the access control part which concerns on embodiment of this invention. It is a figure which illustrates the path | pass when the option device in the image processing apparatus which concerns on embodiment of this invention reads the image data memorize | stored in the main memory. It is a sequence diagram which shows the operation example in the image processing apparatus which concerns on embodiment of this invention. It is a sequence diagram which shows the operation example in the image processing apparatus which concerns on embodiment of this invention.

  Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings. In the present embodiment, an image processing apparatus in which an optional device is connected to the main chip via a bus will be described as an example. In the present embodiment, the process performed by the option device is a process that does not require the isochronism of lines and pages, such as converting the format of image data and transmitting it to the PC. "

  FIG. 1 is a block diagram illustrating a conventional configuration of an image processing apparatus 1 according to this embodiment. As shown in FIG. 1, an image processing apparatus 1 includes a controller ASIC (Application Specific Integrated Circuit) 100 that is a main chip, an option device 120 that is an image processing unit that performs option processing (hereinafter, referred to as “option A”), An option device 130 (hereinafter referred to as “option B”), an SoC (System-on-a-Chip) 10, a main memory 20, a switch 30, a bridge 40, a printer process and a scanner process, which are image processing units that perform option processing The engine ASIC 140 that is an image processing unit that performs processing that requires ensuring the isochronism of the line and the like, and a CPU (Central Processing Unit) 50 that controls the engine ASIC 140 are included.

  The SoC 10 includes a controller ASIC 100, a CPU (Central Processing Unit) that controls option A and option B, an interface of the main memory 20, and a data input / output interface such as USB (Universal Serial Bus) and Ethernet (registered trademark). The main memory 20 stores a program for controlling the image processing apparatus 1 and image data, and is used as a work area of the CPU. That is, the main memory 20 functions as an image storage medium that is a storage medium for storing image data.

  The switch 30 branches one serial bus I / F and switches the connection between a plurality of serial bus I / F devices and the controller ASIC 100. The bridge 40 converts the connection by the parallel bus I / F and the connection by the serial bus I / F. For example, since option A corresponds to a connection via the parallel bus I / F, the connection 154 via the parallel bus I / F is converted to a connection via the serial bus I / F via the bridge 40 and connected to the switch 30. Thus, the controller ASIC 100 is connected. On the other hand, since option B corresponds to connection via the serial bus I / F, it is connected to the controller ASIC 100 by being directly connected to the switch 30 via the serial bus connection 155.

  The controller ASIC 100 includes serial communication units 101, 102, and 103, a DMAC (Direct Memory Access Controller) register 104, a read DMAC 105, an output image editing unit 106, and an output data buffer 107. The serial communication unit 101, serial communication unit 102, DMAC register 104, and read DMAC 105 are connected to each other via an internal bus 108.

  The serial communication unit 101 is an interface that connects the controller ASIC 100 and the SoC 10, and thereby a serial bus connection 151 is established. The serial communication unit 102 is an interface that connects the controller ASIC 100 and the switch 30, and thereby a serial bus connection 152 is established. The serial communication unit 103 is an interface that connects the controller ASIC 100 and a serial communication unit 141 of an engine ASIC 140 described later, and thereby a serial bus connection 156 is established.

  The DMAC register 104 is a storage medium (control information storage medium) for storing control information for controlling the read DMAC 105 described later, and the control information is set via the serial bus connection 151 by the SoC 10. The control information is, for example, the start address of image data read from the main memory 20, the image width of the image data, and the number of lines. That is, the control information is predetermined control information indicating storage areas in the main memory 20 of image data to be acquired by the image processing unit such as option A, option B, and engine ASIC 140.

  The read DMAC 105 is activated by the control from the SoC 10, reads the image data stored in the main memory 20 according to the control information stored in the read command DMAC register 104, and outputs it to the subsequent block. The output image editing unit 106 performs editing processing such as deletion or addition of the end of the image data read by the read DMAC 105 as necessary, and outputs the result to the output data buffer 107. That is, the read DMAC 105 functions as a data storage processing unit that reads image data from the main memory 20 according to a read command and stores it in the output data buffer.

  The output data buffer 107 is a storage medium that stores the image data output from the output image editing unit 106. That is, the output data buffer 107 functions as a processing target image storage medium that stores in advance the image data to be processed read from the main memory 20 by the read DMAC 105. The image data stored in the output data buffer 107 is read by the read DMAC 143 of the engine ASIC 140 described later via the serial bus connection 156.

  The option A includes a parallel communication unit 121, a DMAC register 122, a read DMAC 123, an option processing unit 124, and a write DMAC 125. The parallel communication unit 121 is an interface for performing parallel bus connection. The DMAC register 122 is a storage medium for storing control information for controlling the read DMAC 123 to be described later. The SoC 10 controls the controller ASIC 100 (serial bus connection 151), the switch 30 (serial bus connection 152), and the bridge 40 (parallel bus connection). 154).

  The read DMAC 123 is activated by the control from the SoC 10, reads the image data stored in the main memory 20 in accordance with the control information stored in the DMAC register 122, and outputs the image data to the option processing unit 124. The option processing unit 124 performs an option process on the image data read by the read DMAC 123 and outputs it to the write DMAC 125. The option processing is, for example, image format conversion (RGB (Red, Green, Blue) and CMYK (Cyan, Magenta, Yellow, blackK) mutual color conversion), compression, expansion, reduction, and enlargement.

  The write DMAC 125 writes the image data processed by the option processing unit 124 into the main memory 20. Since option B is connected to the switch 30 through a serial bus, the configuration is the same as that of option A except that the parallel communication unit 121 of option A is replaced with a serial communication unit.

  The engine ASIC 140 includes a serial communication unit 141, a DMAC register 142, and a read DMAC 143. The serial communication unit 141 is an interface for connecting the engine ASIC 140 and the controller ASIC 100, and thereby a serial bus connection 156 is established.

  The DMAC register 142 is a storage medium that stores control information for controlling the read DMAC 143 described later, and is set by the engine CPU 50. The read DMAC 143 is activated by control from the engine CPU 50, and reads image data stored in the main memory 20 or the output data buffer 107 in accordance with control information stored in the DMAC register 142.

  The image data read by the read DMAC 143 is subjected to, for example, print processing, scanner processing, correction processing of an image read by the scanner processing, and the like by a processing unit (not shown) included in the engine ASIC 140. Further, an image processed by a processing unit included in the engine ASIC 140 (for example, a read image generated by a scanner process) may be written in the main memory 20 by a write DMAC (not shown).

  The read DMACs 105, 123, and 143 described above acquire read data (read data) transferred from the main memory 20 according to the read command via the bus by issuing a read command (hereinafter, such processing is referred to as “ Memory read access ”). Memory read access includes split transaction type and interlock type.

  FIG. 2 is a diagram illustrating an example of memory read access. FIG. 2A is a diagram illustrating a split transaction type memory read access mode, and FIG. 2B is a diagram illustrating an interlock type memory read access mode.

  In the split transaction type memory read access, the next read command can be issued before the read data transfer is completed according to the read command. For example, as shown in FIG. 2A, first, before the transfer of the read data 0 (RD0) transferred according to the read command 0 (RC0) is completed, the read command 1 (RC1) and the read command 2 (RC2) ) Are issued in order. Thereafter, when the transfer of RD0 is completed according to RC0, RC3 is issued before the transfer of read data for all read commands issued previously is completed. Similarly, RC4 is issued when transfer of RD1 is completed according to RC1, and RC5 is issued when transfer of RD2 is completed according to RC2.

  As described above, in the split transaction type memory read access, a plurality of read commands can be issued in advance before the read data transfer is completed, so that the memory read access latency T is large. However, the read data can be transferred efficiently, and the performance of the memory read is improved.

  On the other hand, in interlock type memory read access, the bus cannot be used until read data transfer is completed according to the read command, and the next read command cannot be issued. For example, as shown in FIG. 2B, the read command 1 (RC1) is issued after the transfer of the read data 0 (RD0) is completed according to the read command 0 (RC0). Then, after the transfer of the read data 1 (RD1) is completed according to RC1, a read command (RC2) is issued. Then, the transfer of the read data 2 (RD2) is completed according to RC2.

  As described above, in the memory read access of the interlock type, when the latency T of the memory read access is large, the memory read bandwidth may be reduced. Compared with the split transaction type memory read access, the read data transfer is performed. ineffective.

  PCI (Peripheral Component Interconnect)-ASIC internal buses such as high-speed serial I / F such as Express, AXI (Advanced Extensible Interface), OCP (Open Core Protocol) are compatible with split transaction type memory read access. Legacy PCI supports interlock type memory read access.

  In the image processing apparatus 1 shown in FIG. 1, the internal bus 108 and the serial bus connections 151, 152, 153, 155, and 156 correspond to split transaction type memory read access, and the parallel bus connection 154 is a split transaction type. Is compatible with interlock type memory read access.

  In the configuration of the image processing apparatus 1 shown in FIG. 1, the controller ASIC 100 supports serial bus connection. Here, the difference between the case where the controller ASIC 100 supports serial bus connection and the case where the controller ASIC 100 supports parallel bus connection as in the image processing apparatus 1 shown in FIG. 1 will be described.

  FIG. 3 is a diagram illustrating a path connecting the main memory 20 with the option A and the option B. FIG. 3A is a diagram illustrating a connection path when the controller ASIC 100 is compatible with parallel bus connection, and FIG. 3B is a connection when the controller ASIC 100 is compatible with serial bus connection. It is a figure which illustrates a route.

  As shown in FIG. 3A, when the controller ASIC 100 supports parallel bus connection, a plurality of option devices can be connected on one parallel bus. Therefore, for example, option A can read data from main memory 20 via SoC 10 and controller ASIC 100.

  However, in recent years, serial buses have become mainstream as external I / Fs for LSI (Legual Scale Integration) in order to increase the speed of the bus and reduce the number of pins. When the controller ASIC 100 supports serial bus connection (high-speed serial I / F), the connection is point-to-point. Therefore, in order to connect a plurality of optional devices, it is necessary to provide a plurality of serial bus I / Fs or branch one serial bus I / F using the switch 30.

  Since the optional devices are connected to the main chip of the image processing apparatus 1 via a bus as required, the number of connected devices often varies. Therefore, the switch 30 is often used rather than providing the controller ASIC 100 with a plurality of serial bus I / Fs according to the number of option devices. An option device corresponding to the parallel bus connection is connected to the switch 30 via the bridge 40.

  In such a case, for example, the option A can read data from the main memory 20 via the SoC 10, the controller ASIC 100, the switch 30, and the bridge 40 as shown in FIG. As described above, when the controller ASIC 100 supports serial bus connection, the path from the main memory 20 to the option A becomes longer and the latency becomes larger than when the controller ASIC 100 supports parallel bus connection.

  Since option devices that have been developed in the past are often used as they are, it is often the case that they have an interlocked parallel bus I / F such as the above-mentioned legacy PCI. When an optional device having an interlock type parallel bus I / F is connected to the main chip of the image processing apparatus 1, the connection path shown in FIG. 3B is used, so that the latency is increased and the performance of the memory read is increased. bad.

  This is a fundamental problem to be solved in the present embodiment. In order to solve such a problem, an option having an interlock type parallel bus I / F in which a read DMAC and a buffer similar to the read DMAC 105 and the output data buffer 107 shown in FIG. It is conceivable to provide as many devices as there are devices.

  As a result, the image data stored in the main memory 20 is temporarily stored in the buffer, and the option device only has to read out the image data stored in the buffer. Therefore, it is considered that the latency can be reduced. However, the number of such optional devices connected varies, and the number of connected read DMACs and output data buffers must be provided. Therefore, the circuit scale of the controller ASIC 100 increases.

  The gist of the present embodiment is that, in the image processing apparatus 1 to which an option device having an interlock type parallel bus I / F is connected, the latency of memory read by such an option device is suppressed while suppressing an increase in circuit scale. It is to reduce.

  Here, as a comparative example of the operation in the image processing apparatus 1 according to the present embodiment, the conventional operation in the image processing apparatus 1 shown in FIG. 1 will be described with reference to FIGS. FIG. 4 is a diagram illustrating a path when the read DMACs of the option A, the option B, and the engine ASIC 140 read image data stored in the main memory 20 in the image processing apparatus 1.

  In this embodiment, the option A is a device having an interlock type parallel bus I / F, and the option B and the engine ASIC 140 are devices having a strip transaction type serial I / F.

  As indicated by a thick dotted arrow in FIG. 4, the path when the option A read DMAC 123 reads the image data stored in the main memory 20 is the SoC 10, the serial communication unit 101, and the serial communication unit 102 in order from the main memory 20. , Switch 30, bridge 40, parallel communication unit 121, and lead DMAC 123.

  As described above, the option A having the interlock type parallel bus I / F cannot issue a plurality of read commands in advance and increases the latency. In addition, in order for option A to read the image data stored in the main memory 20, it is necessary to go through the switch 30 and the bridge 40, and the distance to the main memory 20 is farther than that of the option B or the engine ASIC 140. Further, the latency is increased.

  Further, as shown by a thick solid line arrow in FIG. 4, the path when the read DMAC (not shown) of option B reads image data stored in the main memory 20 is the SoC 10, serial communication unit 101, It passes through the serial communication unit 102, the switch 30, the serial communication unit (not shown) of option B, and the read DMAC.

  Since option B having a split transaction serial bus I / F can issue a plurality of read commands in advance, the latency is smaller than that of option A. Further, when the image data stored in the main memory 20 is read by the option B, the distance to the main memory 20 is closer and the latency is smaller than in the case of the option A because there is no need to go through the bridge 40.

  Further, as shown by a thick dashed line arrow in FIG. 4, the path when the read DMAC 143 of the engine ASIC 140 reads the image data stored in the main memory 20 is divided into two stages. First, in the first stage, the read DMAC 105 of the controller ASIC 100 reads the image data stored in the main memory 20 and outputs it to the output data buffer 107. In the second stage, the read DMAC 143 of the engine ASIC 140 reads the image data output to the output data buffer 107 via the serial communication unit 103 and the serial communication unit 141.

  In such a two-stage pass, the read DMAC 143 of the engine ASIC 140 does not directly access the main memory 20, so that the latency can be made smaller than that in the case of direct access. Since the engine ASIC 140 performs print processing, scanner processing, and the like, it is necessary to ensure the isochronism of the line of image data, and in particular, it is necessary to suppress latency. Therefore, the memory read by the read DMAC 143 of the engine ASIC 140 has such a configuration. It has become.

  FIG. 5 is a sequence diagram showing a conventional operation example when option A reads image data stored in the main memory 20 as a comparative example of the operation in the image processing apparatus 1 according to the present embodiment. In addition, the solid line arrow between each part shown in FIG. 5 shows the operation | movement by software, and a dotted line arrow shows the operation | movement by hardware. As shown in FIG. 5, the SoC 10 performs register setting (control information setting) for the option A DMAC register 122 (S501).

  The SoC 10 that has set the register activates the option A read DMAC 123 (S502). The read DMAC 123 activated by the control of the SoC 10 accesses the main memory 20 and reads the image data in accordance with the control information set in the DMAC register 122 (S503). The read DMAC 123 that has finished reading the image data notifies the SoC 10 of the completion of the data transfer and ends the processing (S504).

  Note that the operation example when the option B reads image data stored in the main memory 20 is the same as the operation example shown in FIG.

  FIG. 6 is a sequence diagram illustrating an operation example when the engine ASIC 140 reads image data stored in the main memory 20 in the image processing apparatus 1 according to the present embodiment. In addition, the solid line arrow between each part shown in FIG. 6 shows the operation | movement by software, and the dotted line arrow shows the operation | movement by hardware. As shown in FIG. 6, the SoC 10 sets a register in the DMAC register 104 of the controller ASIC 100 (S601).

  Further, the engine CPU 50 sets a register in the DMAC register 142 of the engine ASIC 140 (S602). The SoC 10 that has set the registers in the DMAC register 104 and the DMAC register 142 activates the read DMAC 105 of the controller ASIC 100 (S603).

  The read DMAC 105 activated under the control of the SoC 10 accesses the main memory 20 and reads out image data according to the control information set in the DMAC register 104 (S604). Then, the read DMAC 105 outputs the image data read from the main memory 20 to the output data buffer 107 (S605).

  The engine CPU 50 activates the read DMAC 143 of the engine ASIC 140 (S606). The read DMAC 143 activated under the control of the engine CPU 50 accesses the output data buffer 107 and reads the image data in accordance with the control information set in the DMAC register 142 (S607).

  FIG. 7 is a diagram exemplifying the position of the read access address set in the DMAC register 142. As indicated by hatching in FIG. 7, the read access address set in the DMAC register 142 is fixed. The serial communication unit 103 monitors the read access from the read DMAC 143. When the address is an address for accessing the output data buffer 107, the serial communication unit 103 accesses the output data buffer 107 instead of the main memory 20 to the read DMAC 143. Transfer data. With such a configuration, access from the read DMAC 143 to the output data buffer 107 is realized.

  When the reading of the image data from the main memory 20 and the output of the image data to the output data buffer 107 are completed, the read DMAC 105 notifies the transfer completion to the SoC 10 (S608). Note that the process of S608 is not limited to the process after S607, and may be executed before or during the process of S607. Further, when reading of the image data from the output data buffer is completed, the read DMAC 143 notifies the SoC 10 of the transfer completion and ends the processing (S609).

  An option A read DMAC and an output data buffer are provided in the controller ASIC 100, and the same processing as the image data read processing by the read DMAC 143 of the engine ASIC 140 shown in FIG. It is considered that the latency of the memory read can be reduced also when reading out. However, it is not preferable to add a read DMAC and an output data buffer individually for an optional device that is an optional function that is used as necessary and the number of connections is not determined, resulting in an increase in circuit scale. Hereinafter, an image processing apparatus 1 according to an embodiment of the present invention for the purpose of reducing memory read latency while suppressing an increase in circuit scale will be described.

  FIG. 8 is a block diagram illustrating the configuration of the image processing apparatus 1 according to this embodiment. As shown in FIG. 8, the image processing apparatus 1 according to the present embodiment has the configuration shown in FIG. 1, the register control unit 109, the DMAC register 110, the access source identification unit 111, the access control unit 112, and the selector 113 (hereinafter, “SEL1”) and a selector 114 (hereinafter referred to as “SEL2”) are added.

  The register control unit 109 performs the register setting from the SoC 10 to the DMAC 110 in accordance with the register setting performed from the SoC 10 via the serial communication unit 101. That is, the register control unit 109 functions as a storage medium control unit that stores control information in the DMAC register 110 that is a control information storage medium. A specific example of the processing of the register control unit 109 will be described below with reference to FIGS.

  FIG. 9 is a table illustrating information on optional devices. As shown in FIG. 9, the table includes, for example, “option device name”, “register address” indicating the address of the DMAC register of the option device, and “bus type” indicating the bus type of the option device. The register control unit 109 can refer to the table shown in FIG.

  FIG. 10 is a flowchart illustrating register control by the register control unit 109. As shown in FIG. 10, the register control unit 109 monitors the register setting performed from the SoC 10 via the serial communication unit 101, and acquires the address of the register specified in the register setting (S1001).

  The register control unit 109 that has acquired the register address refers to the table illustrated in FIG. 9 and acquires the “bus type” of the option device associated with the “register address” that matches the acquired register address ( S1002). The register control unit 109 that has acquired “bus type” determines whether or not the acquired “bus type” is “interlock type parallel bus I / F” (S1003).

  When it is determined that it is “interlock type parallel I / F” (S1003 / YES), the register control unit 109 sets the register setting from the SoC 10 also in the DMAC register 110 (S1004). On the other hand, when it is determined that it is not “interlock type parallel I / F” (S1003 / NO), the register control unit 109 ends the process without setting the register in the DMAC register 110.

  For example, in this embodiment, when the register address specified in the register setting from the SoC 10 is the address of the DMAC register 122 of the option A, the register control unit 109 uses the interlock type parallel bus I as the bus type of the option A. Therefore, the register setting of the DMAC register 122 is also set in the DMAC register 110.

  The DMAC register 110 is a storage medium (control information storage medium) that stores control information for controlling the read DMAC 105, and is set by the register control unit 109 as described above. The read DMAC 105 reads image data stored in the main memory 20 in accordance with control information stored in the DMAC register 110 in response to register switching of SEL1 described later.

  The access source specifying unit 111 specifies an option device that has issued a read command, that is, an access source option device that has accessed the serial communication unit 102. Hereinafter, a specific example of the process of the access source identifying unit 111 will be described with reference to FIG. Here, it is assumed that PCI-Express is used as the serial communication units 101, 102, 103, and 141, and PCI is used as the parallel communication unit 121.

  FIG. 11 is a diagram illustrating a header structure of a memory read command of a PCI-Express TLP (Transaction Layer Packet). As shown in FIG. 11, the TLP header includes “Bus Number” and “Device Number”. “Bus Number” and “Device Number” are information allocated to each bus and a device connected to the bus at the time of configuration in a PCI-Express or PCI system. The access source specifying unit 111 acquires “Bus Number” and “Device Number” included in the TLP header acquired via the serial communication unit 102, and specifies an access source option device.

  The access control unit 112 controls the SEL1 and SEL2 according to the operation status of the option device and the read DMAC 105 specified by the access source specifying unit 111, and controls the acquisition destination of the image data of the option device that issued the read command. . SEL1 switches the register connected to the read DMAC 105 to either the DMAC register 104 or the DMAC register 110. The SEL 2 switches the connection destination with the serial communication unit 102 to either the main memory 20 or the output data buffer 107. That is, the SEL 2 switches the image data acquisition destination by the option device to either the main memory 20 or the output data buffer 107 via the serial communication unit 101.

  Hereinafter, a specific example of processing of the access control unit 112 will be described with reference to FIG. FIG. 12 is a flowchart illustrating the processing of the access control unit 112. In the present embodiment, as an initial setting, SEL1 is controlled to connect the read DMAC 105 and the DMAC register 104, and SEL2 is controlled to use the main memory 20 as the image data acquisition destination. Yes.

  As shown in FIG. 12, the access control unit 112 determines whether the bus type of the option device (target image processing unit) specified by the access source specifying unit 111 is an interlocked parallel bus I / F. (S1201). The bus type of the option device is, for example, “bus type” associated with the option device specified by the access source specifying unit 111 from the table shown in FIG.

  When the bus type is other than the interlock type parallel bus I / F (the bus of option B in the present embodiment) (S1201 / NO), the access control unit 112 ends the process with the initial setting. In this case, in this embodiment, since the option device that issued the read command is option B that is not an interlock type parallel bus I / F, the image data of option B is left with the initial settings of SEL1 and SEL2. Is obtained from the main memory 20.

  On the other hand, when the bus type is an interlock type parallel bus I / F (the bus of option A in this embodiment) (S1201 / YES), the access control unit 112 indicates that the read DMAC 105 is operating for the engine ASIC 140. It is determined whether or not there is (S1202). Specifically, in order for the read DMAC 143 of the engine ASIC 140 to acquire the image data stored in the main memory 20, the access control unit 112 reads out and outputs the image data stored in the main memory 20. It is determined whether or not the data buffer 107 has been output in advance.

  That is, the process of S1202 means determining whether or not the engine ASIC 140 is acquiring data from the output data buffer 107, and the operation status of the read DMAC 105 is one of a plurality of image processing units. It can also be said that an engine ASIC 140 is operating. For example, the access control unit 112 can determine whether the read DMAC 105 is operating for the engine ASIC 140 by monitoring an operation control state by the SoC 10.

  If it is determined that it is operating (S1202 / YES), the access control unit 112 controls SEL2 so that the serial communication unit 102 and the main memory 20 are connected (S1203).

  Since the engine ASIC 140 performs print processing, scanner processing, and the like, it is necessary to ensure timeliness such as lines of image data, and in particular, it is necessary to suppress latency. For this reason, the priority for acquiring image data from the output data buffer 107 is higher in the engine ASIC 140 than in the option device that does not need to ensure isochronism of lines and pages. That is, the priority order is set according to the type of processing performed by the engine ASIC 140 or the optional device. The DMAC register 104 and the DMAC register 110 store control information for the image processing units having different priorities to acquire image data from the main memory 20, respectively.

  When the read DMAC 105 is operating for the engine ASIC 140 by the above processing, the read DMAC 143 reads the image data stored in the output data buffer 107, and the option A read DMAC 123 is stored in the main memory 20. Image data is read out.

  The access control unit 112 that has controlled SEL1 and SEL2 returns to the process of S1202 and monitors the operation status of the read DMAC 105.

  On the other hand, if it is determined that it is not operating (S1202 / NO), the access control unit 112 controls SEL1 so that the read DMAC 105 and the DMAC register 110 are connected (S1204). Further, the access control unit 112 controls SEL2 so that the serial communication unit 102 and the output data buffer 107 are connected (S1205).

  When the read DMAC 105 is not operating for the engine ASIC 140, the output data buffer 107 can be used. Therefore, the read DMAC 105 reads the image data from the main memory 20 according to the control information stored in the DMAC register 110 having the same register setting as that of the option A DMAC register 122 that issued the read command by the above processing, and the output data buffer. It outputs to 107. Since the option A read DMAC 123 can read image data from the output data buffer 107, the latency of the memory read is reduced as compared with the conventional case.

  The access control unit 112 that controls SEL1 and SEL2 returns to the processing of S1202 and monitors the operation status of the read DMAC 105 until the data transfer completion is notified from the option A to the SoC 10 (S1206 / YES). When the completion of data transfer is notified from the option A to the SoC 10 (S1206 / YES), the access control unit 112 controls SEL1 and SEL2 to the initial setting state and ends the processing (S1207).

  Further, as described above, the access control unit 112 monitors the operation status of the read DMAC 105 even after controlling the connection between the SEL1 and the SEL2. As a result, even when the read DMAC 105 is operating for the engine ASIC 140 when the option A issues a read command, when the operation is completed, the acquisition destination of the image data by the option A is stored in the output data buffer 107 halfway. Can be switched.

  In this case, the access source identifying unit 111 records to what address the option A read DMAC 123 has read the image data from the main memory 20. When the operation of the engine ASIC 140 of the read DMAC 105 is completed, the access control unit 112 sets, in the DMAC register 110, the start address of image data that has not been read out from the address recorded by the access source specifying unit 111.

  Although not shown in FIG. 12, even if the access control unit 112 switches the acquisition destination of the image data by the option A to the output data buffer 107, if the engine ASIC 140 issues a read command in the middle, the access control unit 112 The image data acquisition destination can be switched to the main memory 20. As described above, the access control unit 112 is indicated in the control information stored in the DMAC 110 among the plurality of image processing units according to the operation status of the plurality of image processing units such as the option A, the option B, and the engine ASIC 140. It functions as a switching control unit that switches the image processing unit that should acquire image data from the storage area to acquire the image data from the output data buffer 107.

  FIG. 13 is a diagram exemplifying a path when the option A read DMAC 123 reads image data stored in the main memory 20 in the image processing apparatus 1 according to the present embodiment. Here, a path when the read DMAC 105 is not operating for the engine ASIC 140 will be described.

  As indicated by a thick solid arrow in FIG. 13, the path when the option A read DMAC 123 reads the image data stored in the main memory 20 is divided into two stages. First, in the first stage, according to the control information stored in the DMAC register 110, the read DMAC 105 of the controller ASIC 100 reads out the image data stored in the main memory 20 and outputs it to the output data buffer 107.

  In the second stage, the option A read DMAC 123 reads the image data output to the output data buffer 107 via the SEL 2, the serial communication unit 102, the switch 30, the bridge 40, and the parallel communication unit 121. The path when the read DMAC 143 of the engine ASIC 140 and the read DMAC of the option B read the image data stored in the main memory 20 is the same as the path described with reference to FIG.

  FIG. 14 is a sequence diagram illustrating an operation example in the image processing apparatus 1 according to the present embodiment. Here, when the read DMAC 105 is not operating for the engine ASIC 140 (when image data processed by the engine ASIC 140 is not being read from the main memory 20), the option A read DMAC 123 is stored in the main memory 20. An example of operation when reading out image data will be described. In addition, the solid line arrow between each part shown in FIG. 14 shows the operation | movement by software, and the dotted line arrow shows the operation | movement by hardware.

  As shown in FIG. 14, the SoC 10 sets a register for the option A DMAC register 122 (S1401). When the register setting is performed by the SoC 10, the register setting set in the DMAC register 122 by the register control unit 109 is also reflected in the DMAC register 110 of the controller ASIC 100 (S1402).

  The SoC 10 that has set the register activates the read DMAC 105 of the controller ASIC 100 (S1403). The read DMAC 105 activated by the control of the SoC 10 accesses the main memory 20 for the set size from the start address of the memory according to the control information set in the DMAC register 110 connected by switching the SEL1 by the access control unit 112. The image data is read out (S1404). Then, the read DMAC 105 outputs the image data read from the main memory 20 to the output data buffer 107 (S1405).

  The option A read DMAC 123 reads the image data in accordance with the control information set in the DMAC register 122 (S1406). However, SEL2 is switched by the access control unit 112, and the output data buffer 107 is the acquisition destination of the image data. Therefore, the read DMAC 123 ignores the start address set in the DMAC register 122 and reads the image data stored in the output data buffer 107.

  When the read DMAC 105 of the controller ASIC 100 completes the reading of the image data from the main memory 20 and the output of the image data to the output data buffer 107, it notifies the SoC 10 of the transfer completion (S1407). Note that the process of S1407 is not limited to the process after S1406, and may be executed before or during the process of S1406. Further, when the reading of the image data from the output data buffer is completed, the read DMAC 123 notifies the SoC 10 of the transfer completion and ends the processing (S1408).

  In this embodiment, the case where the read DMAC 105 notifies the SoC 10 of transfer completion (S1407) has been described as an example. However, as described with reference to FIG. 5, when the option A read DMAC 123 reads image data directly from the main memory 20, the SoC 10 does not receive a transfer completion notification from the read DMAC 105. For this reason, in order to make the control in the SoC 10 equivalent to the conventional control, when the read DMAC 105 is operating according to the control information stored in the DMAC register 110, the transfer completion may not be notified to the SoC 10. .

  FIG. 15 is a sequence diagram illustrating an operation example in the image processing apparatus 1 according to the present embodiment. Here, an example of an operation when the read DMAC 123 of the option A reads image data stored in the main memory 20 when the read DMAC 105 is operating for the engine ASIC 140 will be described. Note that solid line arrows between the units illustrated in FIG. 15 indicate operations by software, and dotted arrows indicate operations by hardware.

  Since the operation of reading the image data stored in the main memory 20 by the read DMAC 143 of the engine ASIC 140 is the same as the operation shown in FIG. 6, the description of the operation up to the middle is omitted in FIG. The process of S607 shown in FIG. 6 will be described as the process of S1501 shown in FIG.

  As shown in FIG. 15, the read DMAC 143 of the engine ASIC 140 accesses the output data buffer 107 and reads the image data in accordance with the control information set in the DMAC register 142 (S1501).

  The SoC 10 sets a register for the option A DMAC register 122 (S1502). When the register setting is performed by the SoC 10, the register setting set by the register control unit 109 in the DMAC register 122 is also reflected in the DMAC register 110 of the controller ASIC 100 (S1503).

  The SoC 10 that has set the register activates the read DMAC 123 of the controller ASIC 100 (S1403). Since the SEL2 is controlled by the access control unit 112 and the serial communication unit 102 and the main memory 20 are connected, the read DMAC 123 activated by the control of the SoC 10 follows the control information set in the DMAC register 122. 20 is accessed and image data is read out (S1505).

  The read DMAC 105 transfers the image data to the SoC 10 when reading of the image data from the main memory 20 and output of the image data to the output data buffer 107 are completed while the read DMAC 123 is reading image data from the main memory 20. Completion is notified (S1506). Further, when the reading of the image data from the output data buffer is completed, the read DMAC 143 notifies the SoC 10 of the transfer completion and ends the processing (S1507).

  The read DMAC 105 that has notified the transfer completion accesses the main memory 20 from the start address of the image data that has not been read in accordance with the control information set in the DMAC register 110 connected by switching SEL1 by the access control unit 112. The image data is read out (S1508). Then, the read DMAC 105 outputs the image data read from the main memory 20 to the output data buffer 107 (S1509).

  Thereafter, processing similar to S1406 to S1408 shown in FIG. 14 is performed (S1510 to S1512). Also, in the operation shown in FIG. 15, as in the operation shown in FIG. 14, the transfer completion notification to the SoC 10 that is the process of S <b> 1511 may not be performed.

  As described above, in the image processing apparatus 1 according to the present embodiment, the output data buffer 107 that stores the image data read from the main memory 20 and the image data are read in advance from the main memory 20 and the output data buffer 107. The read DMAC 105 stored in is shared by a plurality of image processing units such as an engine and an optional device. When the option A having the interlock type parallel bus I / F reads the image data from the main memory 20, the image data read from the main memory 20 by the read DMAC 105 is read according to the operation status of the read DMAC 105. Are read to the output data buffer 107, and the option A read DMAC 123 reads the image data from the output data buffer 107.

  As a result, the option A read DMAC 123 does not need to read the image data directly from the main memory 20, so that the latency of the memory read is reduced as compared with the conventional case. Further, the read DMAC 105 and the output data buffer 107 for realizing such a configuration are shared by the engine and a plurality of optional devices, and it is not necessary to provide the read DMAC and the output data buffer individually according to the number of connected optional devices. Therefore, an increase in circuit scale can be suppressed. Therefore, with such a configuration, it is possible to reduce the latency of memory read by a device connected to the image processing apparatus while suppressing an increase in circuit scale in the image processing apparatus.

  In the above-described embodiment, the case where the acquisition destination of the image data by the read DMAC 123 of the option A is switched to the output data buffer 107 when the operation for the engine ASIC 140 by the read DMAC 105 is completed has been described as an example. In addition, even when the operation for the engine ASIC 140 by the read DMAC 105 is completed, the acquisition destination may not be switched to the output data buffer 107 according to the remaining amount of image data to be read by the read DMAC.

  In this case, when the operation for the engine ASIC 140 by the read DMAC 105 is completed, for example, the access control unit 112 determines the total amount obtained from the read image data amount recorded by the access source specifying unit 111 and the register setting of the DMAC register 110. The remaining image data amount to be read is calculated from the image data amount. When the calculated remaining image data amount is smaller than a predetermined threshold, the access control unit 112 controls SEL1 and SEL2 so that the read destination of the image data by the read DMAC 123 is not switched to the output data buffer 107. Like that. This is because, when the remaining amount of image data to be read is small, it may be more efficient to perform the reading process from the main memory 20 as it is than to switch the reading destination to the output data buffer 107.

  In the above embodiment, when the read DMAC of the optional device having the interlock type parallel bus I / F reads image data from the main memory 20, the image data reading destination is determined according to the operation status of the read DMAC 105. Has been described as an example of switching to the output data buffer 107. In addition, when the read DMAC of an optional device having an interlock type or split transaction type serial bus I / F reads image data from the main memory 20 as well as an optional device having an interlock type parallel bus I / F. Such a switching process may be performed.

  In this case, a priority order for using the output data buffer 107 as a data acquisition destination is set according to the bus type of the optional device. For example, a device having a parallel bus I / F has a longer distance from the main memory 20 to the option device and has a higher latency than the device having a serial bus I / F because it needs to go through the bridge 40. The use priority of the output data buffer 107 is set higher in the device having the I / F than in the device having the serial bus I / F.

  In addition, since the interlock type device has a larger memory read latency than the split transaction type device, the interlock type device is set to have a higher use priority of the output data buffer 107 than the split transaction type device. The The access control unit 112 determines which option device's image data acquisition destination to switch to the output data buffer 107 based on such usage priority. With this configuration, the memory read latency is reduced even in devices other than the optional device having the interlock type parallel bus I / F.

  In the above embodiment, the case where the option A having the interlock type parallel bus I / F and the option B having the split transaction type serial bus I / F are connected to the controller ASIC 100 has been described as an example. However, this is an example, and three or more such optional devices may be connected to the controller ASIC 100.

  In the above embodiment, the case where the controller ASIC 100 includes the two DMAC registers 104 and the DMAC register 110 has been described as an example. However, this is an example, and one DMAC register 104 may be shared by the engine ASIC 140 and a plurality of optional devices. In this case, SEL1 is unnecessary, and the register control unit 109 determines that the DMAC register is not used when the read DMAC 105 is not operating for the engine ASIC 140 when the option A acquires image data stored in the main memory 20. The register setting 122 is also set in the DMAC register 104.

  If the acquisition of image data by the engine ASIC 140 is completed before the acquisition of image data from the main memory 20 by the option A is completed, the register control unit 109 starts the remaining image data to be acquired by the option A. An address is set for the DMAC 104. Further, when a read command is issued by the engine ASIC 140 during acquisition of image data from the main memory 20 by the option A, the register control unit 109 sets the start address of the remaining image data to be acquired by the engine ASIC 140 to the DMAC 104. For option A, the remaining image data to be acquired is acquired from the main memory 20.

  When two DMAC registers 104 and 110 are provided, the processing efficiency is good in that rewriting of the DMAC register 104 is unnecessary, but the circuit scale becomes smaller when one DMAC 104 is shared. In addition, the controller ASIC 100 may include three or more DMAC registers. In this case, the circuit scale is somewhat larger, but the efficiency is improved in terms of managing the control information of each image processing unit.

  In the above embodiment, the case where the register control unit 109, the access source specifying unit 111, and the access control unit 112 are realized by hardware configured as an ASIC has been described as an example. However, this is an example, and these components may be realized by software. In this case, a program stored in a recording medium such as a ROM, an HDD, or an optical disk (not shown) is read out to the RAM, and a software control unit is configured by the CPU performing calculations according to those programs. A functional block that realizes the functions of the register control unit 109, the access source specifying unit 111, and the access control unit 112 according to the present embodiment is configured by a combination of the software control unit configured in this way and hardware. .

  In the above embodiment, the image processing apparatus 1 has been described as an example, and the case where the engine or the optional device reads image data from the main memory 20 has been described as an example. However, the present embodiment is not limited to the image processing apparatus 1, and the same applies to a case where a dedicated engine or an optional device in an information processing apparatus that processes data stored in the main memory reads out data stored in the main memory. It is applicable to.

1 Image processing device 10 SoC
20 Main memory 30 Switch 40 Bridge 50 Engine CPU
100 Controller ASIC
101, 102, 103, 141 Serial communication unit 104, 110, 122, 142 DMAC register 105, 123, 143 Read DMAC
106 Output image editing unit 107 Output data buffer 108 Internal bus 109 Register control unit 111 Access source specifying unit 112 Access control unit 113, 114 Selector 120, 130 Option device 121 Parallel communication unit 124 Option processing unit 125 Write DMAC
140 Engine ASIC

JP-A-9-198300 JP 2012-034254 A

Claims (9)

An image processing apparatus including a plurality of image processing units that acquire and process image data from an image storage medium that stores the image data,
A data storage processing unit that reads image data from the image storage medium in accordance with a read command for reading image data to be processed, and stores the read image data in a processing target image storage medium that is a storage medium for storing the image data When,
Storage for storing the predetermined control information in a control information storage medium that is a storage medium for storing predetermined control information indicating a storage area in the image storage medium of image data to be acquired by one of the plurality of image processing units A medium control unit;
According to the operation status of the plurality of image processing units, among the plurality of image processing units, the processing target image storage is performed in an image processing unit that acquires image data from a storage area indicated in the predetermined control information. A switching control unit that switches to obtain image data from the medium ;
An image processing apparatus comprising: In each of the plurality of image processing units, a priority order is set for obtaining image data from the processing target image storage medium,
The storage medium control unit stores, in a plurality of the control information storage media, predetermined control information indicating storage areas in the image storage medium of image data to be acquired by the image processing units having different priorities. ,
The switching control unit is a target image process that is one of image processing units that should acquire image data from a storage area indicated in the predetermined control information stored in each of the plurality of control information storage media. When the image acquisition unit newly acquires the image data, the plural image processing units except for the case where another image processing unit having a higher priority than the target image processing unit is acquiring image data from the processing target image storage medium. Among the plurality of predetermined control information stored in each control information storage medium, the predetermined control information indicating the storage area in the image storage medium of the image data to be acquired by the target image processing unit is used. Switching to switch the target image processing unit to acquire image data from the processing target image storage medium ,
The image processing apparatus according to claim 1. Before Symbol switching control unit,
When the other image processing unit having a higher priority is acquiring image data from the processing target image storage medium, of the plurality of predetermined control information, the image data to be acquired by the other image processing unit Switching to use predetermined control information indicating a storage area in the image storage medium, causing the other image processing unit to acquire image data from the processing target image storage medium, and causing the target image processing unit to acquire image data from the image storage medium Switch to get image data,
If the acquisition of image data by the other image processing unit is completed before the acquisition of image data by the target image processing unit is completed, the image to be acquired by the target image processing unit among the plurality of predetermined control information Switching so that predetermined control information indicating a storage area of data in the image storage medium is used, and switching so that the target image processing unit acquires image data from the processing target image storage medium ;
The image processing apparatus according to claim 2. The switching control unit
If the acquisition of the image data by the other image processing unit is completed before the acquisition of the image data by the target image processing unit is completed, the remaining data amount to be acquired by the image data processed by the target image processing unit is determined. Calculate
Of the plurality of predetermined control information, predetermined control information indicating a storage area in the image storage medium of the image data to be acquired by the target image processing unit is used according to the calculated remaining data amount. Switching so that the target image processing unit acquires image data from the processing target image storage medium ,
The image processing apparatus according to claim 3. The switching control unit is configured such that when the target image processing unit obtains image data from the processing target image storage medium and an image data read command from the image storage medium is issued by the other image processing unit, Among a plurality of predetermined control information, switching is performed so that predetermined control information indicating a storage area in the image storage medium of image data to be acquired by the other image processing unit is used, and the other image processing unit Switching to acquire image data from the processing target image storage medium and cause the target image processing unit to acquire image data from the image storage medium ;
The image processing apparatus according to claim 2, wherein the image processing apparatus is an image processing apparatus. In each of the plurality of image processing units, a priority order is set for obtaining image data from the processing target image storage medium,
The storage medium control unit has a higher priority than a target image processing unit that is an image processing unit that newly acquires the image data when one of the plurality of image processing units newly acquires the image data. Except when a high image processing unit is acquiring image data from the processing target image storage medium, the predetermined control information is stored in the control information storage medium,
The switching control unit is configured to send an image from the processing target image storage medium to the target image processing unit, except when the other image processing unit having a high priority is acquiring image data from the processing target image storage medium. Switch to get data ,
The image processing apparatus according to claim 1. The image processing apparatus according to claim 2 , wherein the priority is set according to a type of processing executed in the image processing unit. The priority is further set according to the type of bus corresponding to the image processing unit ,
The image processing apparatus according to claim 7. A control method for an image processing apparatus including a plurality of image processing units for acquiring and processing image data from an image storage medium for storing image data,
The image processing apparatus reads image data from the image storage medium in accordance with a read command for reading image data to be processed, and stores the read image data on a processing target image storage medium that is a storage medium for storing the image data. Including a data storage processing unit for storing,
Storing the predetermined control information in a control information storage medium that is a storage medium for storing predetermined control information indicating a storage area in the image storage medium of image data to be acquired by one of the plurality of image processing units;
According to the operation status of the plurality of image processing units, among the plurality of image processing units, the processing target image storage is performed in an image processing unit that acquires image data from a storage area indicated in the predetermined control information. Switch to get image data from the media ,
And a control method for the image processing apparatus.

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