JP2005284580A - Bus device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a bus device omitting generation of unnecessary overhead of retransfer to realize efficient data transfer by allowing resuming of the transfer suspended when a RETRY signal is generated, from halfway. <P>SOLUTION: This bus device has: a transfer state holding device 5 holding data from a master connected via a bus line 4, and transferring the held data to a slave connected via the bus line 4; and an arbiter 6 controlling the bus line 4 such that the corresponding master and slave are connected according to a bus requirement signal from the master, controlling the bus line 4 such that it is changed to connection between the corresponding master and the transfer state holding device 5 according to the RETRY signal from the slave in the middle of the data transfer, and also controlling the bus line 4 such that it is changed to connection between the transfer state holding device 5 and the slave according to a ready state of the slave in the middle of the data transfer. <P>COPYRIGHT: (C)2006,JPO&NCIPI

Description

  The present invention relates to a bus device that is connected between a plurality of masters and a plurality of slaves and performs mutual data transfer between the plurality of masters and the plurality of slaves.

Conventionally, a bus is used as a means for interconnecting a plurality of masters and a plurality of slaves. This is because it is easy to implement, but on the other hand, if access from multiple masters concentrates on slaves that are slow in response and operation, a master uses the bus even though the bus line is not being used effectively. Since the right is occupied for a long time, the overall processing performance may be deteriorated. In order to avoid this, in AMBA AHB (Advanced High performance Bus), when the slave is unable to respond for a long time, division such as retry or split to release the bus use right once and readjust. Means are provided for retransmission.
Also, in the method disclosed in Patent Document 1 below, if the slave cannot respond in a certain cycle, the slave outputs a retransfer request, and the master that has received the retransfer request from the slave releases the bus. A method of accessing again after a certain time is employed.

Japanese Patent Laid-Open No. 3-201054

  Since the conventional bus device is configured as described above, when the master that has received the retransfer request receives a retransfer request during a burst transfer, for example, in response to the command that has received the retransfer request, Even during the burst transfer, the transfer was aborted, and after waiting for the slave to become ready, it became possible to retransmit, and then the transfer was reissued from the beginning of the aborted transfer. That is, if a retransfer request is issued at the time when the seventh transfer is completed during a burst transfer in which eight transfers are performed, the seven transfers performed so far are useless. Also, it is normal that the master cannot perform other processing until a retransfer request is possible. Since the processing is not efficiently performed due to the overhead generated during the retransfer, there is a problem that the system cannot obtain a desired performance.

  The present invention has been made to solve the above-described problems, and by making it possible to resume the transfer interrupted at the time of the retransfer request from the middle, it is possible to eliminate the occurrence of unnecessary overhead of the retransfer and to improve the efficiency. An object of the present invention is to obtain a bus device that achieves improved system performance by realizing typical data transfer.

  The bus device according to the present invention holds a data from a master connected through a bus line and transfers the held data to a slave connected through the bus line, and a bus use request from the master The bus line is controlled so that the corresponding master and slave are connected to each other, and the connection is changed to the connection between the corresponding master and transfer status holding device in response to a retransfer request from the slave in the middle of the data transfer. In addition to controlling the bus line, the transfer state holding device and the arbiter for controlling the bus line to be changed to the connection between the slaves according to the transfer permission state of the slave during the data transfer are provided. .

  According to the present invention, in response to a retransfer request from a slave in the middle of data transfer, data from the master is transferred from the middle to the transfer state holding device, and the data from the middle is held in the transfer state holding device. Further, data from the middle held in the transfer status holding device is transferred to the slave according to the transfer permission status of the slave. Therefore, by enabling the transfer to be resumed from the point where it was interrupted at the time of the re-transfer request, the unnecessary overhead of re-transfer is eliminated, and efficient data transfer is achieved, thereby improving the system performance. There is an effect that can be done.

Embodiment 1 FIG.
FIG. 1 is a block diagram showing a bus device according to Embodiment 1 of the present invention. In the figure, the bus device 1 includes X + 1 (X is an arbitrary natural number) masters 2m0 to 2mX, Y + 1 (Y is an arbitrary Natural number) slaves 3s0 to 3sY are connected to each other, and data transfer between the connected masters 2m0 to 2mX and slaves 3s0 to 3sY is performed. As the masters 2m0 to 2mX, devices such as computers or H / W I / Ps for specific applications are applied, and as the slaves 3s0 to 3sY, storage devices such as SDRAM are applied. .
In the bus device 1, the bus line 4 is connectable to masters 2m0 to 2mX and slaves 3s0 to 3sY, and transfers data between the connected master and slave. The transfer state holding device 5 is connectable to the bus line 4, holds data from a master connected through the bus line 4, and holds the held data etc. as a slave or master connected through the bus line 4. To be transferred to. The arbiter 6 controls the bus line 4 so that the corresponding master and slave are connected in response to a bus use request from the masters 2m0 to 2mX, and a RETRY signal (retransfer request) from the slave in the middle of the data transfer The bus line 4 is controlled so as to be changed to the connection between the corresponding master and the transfer state holding device 5 according to the transfer state, and the transfer state holding device 5 according to the ready state (transfer permission state) of the slave in the middle of the data transfer. The bus line 4 is controlled so as to be changed to the connection between the slaves.

The signal lines 100 to 10X, 110 to 11Y, and 12 are used by the masters 2m0 to 2mX and the slaves 3s0 to 3sY to communicate with each other.
FIG. 2 is an explanatory diagram showing signal lines between the master and the slave. Specifically, as shown in FIG. 2, an R / W signal indicating writing / reading as a signal from the master to the slave, and the address of the slave are shown. An address signal to indicate, a transfer type signal to indicate the state and type of transfer, a write data signal to be written to the slave, and a master identifier signal for identifying the master. The signal from the slave to the master is composed of a response signal indicating a response to the master request and a read data signal from the slave.
The bus request signals 130 to 13X and 14 are used by the masters 2m0 to 2mX and the transfer state holding device 5 to issue a bus use request to the arbiter 6, respectively.
The bus line control signal 15 is a signal line 100 of the masters 2m0 to 2mX and the transfer state holding device 5 to which the arbiter 6 has given permission to use the bus line 4 among the bus requests from the masters 2m0 to 2mX and the transfer state holding device 5. -10X and 12 and the bus line 4 is controlled so as to connect the appropriate signal line among the signal lines 110 to 11Y corresponding to the address included in the signal line.
The RETRY signals 160 to 16Y are used to issue a retransfer request to the master when it is determined that the slave is busy or the slave requires a large number of cycles to complete the transfer.
The transfer switching control signal 17 is transmitted by the arbiter 6 from the bus line 4 to the transfer state holding device 5 through the signal line 12 and from the transfer state holding device 5 to the bus line 4 through the signal line 12. Switching control.

FIG. 3 is a block diagram showing a transfer state holding device. In the figure, the transfer state holding device 5 includes a FIFO and a register for holding various signals described in FIG. 2, and in this configuration example, an R / W signal is transmitted. It comprises an R / W FIFO 21 that holds, an address FIFO 22 that holds an address signal, a transfer type FIFO 23 that holds a transfer type signal, a write FIFO 24 that holds a write data signal, and a master identifier register 25 that holds a master identifier signal. . Further, in response to the transfer switching control signal 17 from the arbiter 6, the FIFO 21 to 24 and the register 25 are output with a FIFO / W control signal 27, and the switch control signal is output to the transfer direction switching switch 28. 25 is provided with changeover switch control means 26 for controlling 25 writing / reading.
FIG. 4 is a timing chart showing the operation of the bus device according to the first embodiment of the present invention.

Next, the operation will be described.
In FIG. 1, in order for the masters 2m0 to 2mX to execute write / read commands to the slaves 3s0 to 3sY, first, bus request signals 130 to 13X are asserted to the arbiter 6. The arbiter 6 outputs a significant value to the bus line control signal 15 based on a bus usage right determination algorithm set in advance according to the input of the bus request signals 130 to 13X. The bus line 4 connects any one of the signal lines 100 to 10 </ b> X and any one of the signal lines 110 to 11 </ b> Y according to the input of the bus line control signal 15. In this way, the master is connected to the target slave and can transfer data from the master to the slave.
Thereafter, the transfer from the master to the slave is executed, and it is determined that the slave in the middle of the data transfer is busy, or that the slave requires a very large number of cycles to complete the transfer. When the RETRY signal (retransfer request) is output, the arbiter 6 changes the bus line control signal 15 according to the RETRY signal and asserts the transfer switching control signal 17 to transfer from the master to the slave. Then, switching from the master to the transfer state holding device 5 is performed.

  This operation will be described in more detail. In FIG. 3, in the transfer state holding device 5, the changeover switch control means 26 is driven by the transfer changeover control signal 17 from the arbiter 6. In response to the switch control signal, the driven changeover switch control means 26 turns the transfer direction changeover switch 28 in the writing direction, that is, the R / W signal, the address signal, the transfer type signal, the write data signal, and the master identifier signal are from left to right. The FIFOs 21 to 24 and the register 25 are controlled to be written by the FIFO / W control signal 27. Since the arbiter 6 switches the connection of the bus line 4 from the connection between the master and the slave to the connection between the master and the transfer state holding device 5, various signals output from the master are transferred through the bus line 4 and the signal line 12. The data is transferred to the holding device 5 and written into the FIFOs 21 to 24 and the register 25 through the transfer direction changeover switch 28. The transfer state holding device 5 records all the signals in each cycle in the FIFOs 21 to 24 and the register 25 for the switched transfer, and the transfer direction changeover switch 28 detects the end of the transfer when no signal passes and detects the transfer direction. A response signal of the write command is output from the changeover switch 28 to the master. This completes the write request from the master.

When the transfer from the master is completed, the arbiter 6 deasserts the transfer switching control signal 17, and the changeover switch control means 26 of the transfer state holding device 5 asserts the bus request signal 14 to the arbiter 6. As a result, the transfer status holding device 5 is switched from writing to reading of various signals.
The arbiter 6 preferentially accepts a bus request from the transfer request holding device 5 and gives the bus use right to the transfer request holding device 5 when the slave that was in the middle of transfer becomes ready. The transfer request holding device 5 that has obtained the right to use the bus sequentially transfers various signals written in the FIFOs 21 to 24 and the register 25 to the slave that was in the middle of transfer, instead of the master.

The operation up to this point is shown in FIG. 4 using four burst write transfers as an example. The bus grant signal in FIG. 4 is a signal (not shown in FIGS. 1 to 3) indicating permission to use the bus line 4 output from the arbiter 6.
The master issues a bus request signal to the arbiter 6 at the clock (1), and the bus use right is issued by the arbiter 6 asserting the bus grant signal to the master at the clock (2). At the same time, the bus line control signal 15 And the master and the slave are connected using the bus line 4. At the clock (3), the master senses that the bus grant signal is asserted and starts transfer. The slave issues a RETRY signal at the clock (4), and the arbiter 6 immediately asserts the transfer switching control signal 17 to switch the master transfer from the slave to the transfer state holding device 5. The master transfer is recorded in the transfer status holding device 5 at the clock (5). At this time, if it is the conventional technique, an ERROR response should be returned. At this time, the response signal of the bus line 4 is a response signal issued by the transfer state holding device 5, and the transfer state holding device 5 correctly receives the data. Is held, so an OKAY response is returned. At the clock (6), the slave deasserts the RETRY signal and becomes ready. The transfer state holding device 5 obtains permission to use the bus line 4 from the arbiter 6 at the clock (7), and resumes the held transfer.
Note that while the transfer status holding device 5 holds the request of the master and issues a bus request, that is, between the clocks (4) to (7) in FIG. 4, until the slave is ready. The arbiter 6 may assign the use of the bus line 4 to a master that issues a request to a slave other than the slave.

Further, when a read request is issued from another master to the slave, and the arbiter 6 determines that the data corresponding to the read request is held in the transfer state holding device 5, that is, in the example of FIG. In the case of read access to the data at the address 0x0c held in the transfer state holding device 5, the arbiter 6 switches the connection of the bus line 4 to the connection between the master and the transfer state holding device 5.
The read request output from the master is transferred to the transfer state holding device 5 through the bus line 4 and the signal line 12, and the address of the slave to be read is input to the changeover switch control means 26 through the transfer direction changeover switch 28, and the changeover switch control is performed. The address is decoded by means 26 and output to address FIFO 22. The arbiter 6 drives the changeover switch control means 26 by the transfer changeover control signal 17, and the changeover switch control means 26 reads the transfer direction changeover switch 28 by the switch control signal, that is, various signals are transferred from right to left. The FIFOs 21 to 24 and the register 25 are controlled to be read by the FIFO / W control signal 27.
In this way, the address of the read request and the address held in the address FIFO 22 are compared and collated, and data corresponding to the match is read from the write data FIFO 24. Thereafter, read data is transferred to the master that has requested reading through the transfer direction switch 28, the signal line 12, the bus line 4, and the signal lines 100 to 10X, and a response signal is output from the transfer direction switch 28. The read request from the master is completed.

As described above, according to the first embodiment, data from the master is transferred from the middle to the transfer state holding device 5 according to the RETRY signal from the slave in the middle of the data transfer, and is transferred to the transfer state holding device 5 halfway. Data from is retained. Further, data from the middle held in the transfer status holding device 5 is transferred to the slave according to the ready state of the slave. Therefore, by making it possible to resume transfer from the point where it was interrupted when a RETRY signal was generated, unnecessary overhead of retransmission is eliminated, and efficient data transfer is realized, thereby improving system performance. Can be achieved.
In addition, the data originally written in the slave is held in the transfer state holding device 5 by the generation of the RETRY signal, and the read request from another master corresponds to the slave address held in the transfer state holding device 5. Even in such a case, the data held in the transfer state holding device 5 can be read from the master without waiting for the completion of data writing to the slave.

Embodiment 2. FIG.
FIG. 5 is a block diagram showing a bus device according to the second embodiment of the present invention. In the figure, the bus device 31 includes X + 1 masters 32m0 to 32mX and Y + 1 slaves 33s0 to 33sY connected to each other. Thus, mutual data transfer is performed between the connected masters 32m0 to 32mX and slaves 33s0 to 33sY.
In the bus device 1, the bus line 34 is connectable to masters 32m0 to 32mX and slaves 33s0 to 33sY, and transfers data between the connected master and slave. The arbiter 36 controls the bus line 34 so that the corresponding master and slave are connected in response to a bus use request from the masters 32m0 to 32mX. The transfer status holding device is provided in each of the masters 32m0 to 32mX.
The bus request signal 43 is used by the masters 32m0 to 32mX to issue a bus use request to the arbiter 36, respectively. The RETRY signal 46 is used to issue a retransfer request to the master, judging that the slave is busy or that the slave requires a very large number of cycles to complete the transfer. The bus grant signal 71 is used by the arbiter 36 to issue a bus use permission in response to a bus request from the masters 32m0 to 32mX.

FIG. 6 is a block diagram showing a master. In the figure, masters 32m0 to 32mX are a central processing unit 81 that controls the entire master, a bus request signal 43, a communication signal generation unit 82 that generates a communication signal, and a slave. It is configured by a transfer state holding device 83 that stops the transfer of the communication signal in response to the RETRY signal 46 and restarts the transfer of the communication signal from the stop position in accordance with the ready state (transfer permission state) of the slave. is there.
The transfer state holding device 83 updates the content of the register 84 when the register 84 holding the communication signal generated by the communication signal generating device 82, the RETRY signal 46 is deasserted, and the bus grant signal 71 is asserted. The register controller 85 holds the contents of the register 84 when the signal 46 is asserted or the bus grant signal 71 is deasserted.
FIG. 7 is a timing chart showing the operation of the bus device according to the second embodiment of the present invention.

Next, the operation will be described.
In FIG. 5, in order for the masters 32m0 to 32mX to communicate with the slaves 33s0 to 33sY, first, the bus request signal 43 is issued to the arbiter 36. The arbiter 36 receiving it asserts the bus grant signal 71 to the master to give the right to use the bus line 34 and at the same time makes the bus line control signal 15 significant. As a result, the master signal line and the target slave signal line are connected one-to-one via the bus line 34 to enable communication. When the arbiter 36 notifies the master by the bus grant signal 71 that the communication is possible, in FIG. 6, the master communication signal generator 82 sequentially asserts the communication signal in synchronization with the system clock to perform the transfer. To do. To assert, the contents of the register 84 are sequentially updated. As a result, communication signals are transferred from the masters 32m0 to 32mX to the slaves 33s0 to 33sY through the signal lines 100 to 10X, the bus line 34, and the signal lines 110 to 11X. The slave that receives the communication signal from the master returns a response according to the communication content. If the communication signal is processed normally, the slave returns an OKY signal as a response signal, and otherwise returns an ERROR signal to the master. When the master receives the OKY signal, the target transfer is completed.

  FIG. 7 shows a four-time burst transfer operation as a specific example of the above transfer operation. In the figure, the master issues a bus request signal 43 to the arbiter 36 at the clock (1), and the arbiter 36 asserts a bus grant signal 71 to the master at the clock (2) to issue a bus use right. The arbiter 36 generates a bus line control signal 15 and connects the master and the slave via the bus line 34. The master starts transfer at the clock (3), the slave issues the RETRY signal 43 at the clock (4), and the arbiter 36 immediately deasserts the bus grant signal 71. The register control unit 85 in the master senses that the RETRY signal 46 is asserted and the bus grant signal 71 is deasserted at the clock (5), and stops the shift of the register 84 in order to stop the transfer. The slave deasserts the RETRY signal 46 at the clock (6) and enters the ready state. At the same time, the master issues a bus request signal 43, and the bus grant signal 71 is asserted at the clock (7), and the master obtains permission to use the bus line 34. At the same time, the register controller 85 senses that the bus grant signal 71 is asserted and the RETRY signal 43 is deasserted, and resumes the stopped transfer from the stop position.

As described above, according to the second embodiment, the data transfer from the master is stopped according to the RETRY signal from the slave in the middle of the data transfer, and the data transfer from the master according to the ready state of the slave. Is resumed from the stop position. Therefore, by making it possible to resume transfer from the point where it was interrupted when a RETRY signal was generated, unnecessary overhead of retransmission is eliminated, and efficient data transfer is realized, thereby improving system performance. Can be achieved.
Further, the control of the arbiter bus line 34 can be simplified, and the configuration of the bus device 31 can be simplified by providing the transfer state holding device 83 in each master.

1 is a block diagram showing a bus device according to Embodiment 1 of the present invention. It is explanatory drawing which shows the signal line between a master and a slave. It is a block diagram which shows a transfer status holding device. It is a timing chart which shows operation | movement of the bus apparatus by Embodiment 1 of this invention. It is a block diagram which shows the bus apparatus by Embodiment 2 of this invention. It is a block diagram which shows a master. It is a timing chart which shows operation | movement of the bus apparatus by Embodiment 2 of this invention.

Explanation of symbols

  1,31 bus device, 2m0 to 2mX, 32m0 to 32mX master, 3s0 to 3sY, 33s0 to 33sY slave, 4,34 bus line, 5,83 transfer status holding device, 6,36 arbiter, 100 to 10X, 110 to 11Y , 12 signal lines, 130 to 13X, 14, 43 bus request signal, 15 bus line control signal, 160 to 16Y, 46 RETRY signal, 17 transfer switching control signal, 21 R / WFIFO, 22 address FIFO, 23 transfer type FIFO, 24 write FIFO, 25 master identifier register, 26 changeover switch control means, 27 FIFO / W control signal, 28 transfer direction changeover switch, 71 bus grant signal, 81 central processing unit, 82 communication signal generation device, 84 register, 85 register control Dress .

Claims (3)

A bus line that is connectable to a plurality of masters and a plurality of slaves and transfers data between the connected masters and slaves;
A transfer state holding device that is connectable to the bus line, holds data from a master connected through the bus line, and transfers the held data to a slave connected through the bus line;
The bus line is controlled so that the corresponding master and slave are connected in response to a bus use request from the master, and the corresponding master and the transfer state in response to a retransfer request from the slave in the middle of the data transfer The bus line is controlled so that the connection between the holding devices is changed, and the transfer state holding device and the connection between the slaves are changed according to the transfer permission state of the slave in the middle of the data transfer. A bus device including an arbiter that controls the bus line. The transfer status holding device
Along with the data from the master, holds the address of the slave to which the data is transferred,
Arbiter
When a read request from another master corresponds to the slave address held in the transfer status holding device, the bus line is controlled so that the connection is changed to the connection between the other master and the transfer status holding device, 2. The bus device according to claim 1, wherein the data held in the transfer status holding device can be read from another master. A bus line that is connectable to a plurality of masters and a plurality of slaves and transfers data between the connected masters and slaves;
An arbiter that controls the bus line so that the corresponding master and slave are connected in response to a bus use request from the master;
In response to a retransfer request from the slave in the middle of data transfer, the data transfer from the master in the middle of the data transfer is stopped, and from the master in the middle of the data transfer according to the transfer permission state of the slave in the middle of the data transfer. A bus device comprising: a transfer state holding device that resumes data transfer from the stop position.

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