JPH113311A - Dma circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To attain direct memory access(DMA) transfer by inexpensive hardware constitution by executing a memory access to a RAM through a 2nd bidirectional buffer based on a signal from a CPU. SOLUTION: When the execution of an access from the CPU 101 to a ROM 102 is confirmed based on a bus cycle start signal BCST issued from the CPU 101, chip select signals CSO# to CSN#, etc., the DMA circuit 104 executes a memory access to a RAM 103-i (i=1 to N) through a 2nd bidirectional buffer 109-i (i=1 to N). When the execution of a memory access from the CPU 101 to a certain RAM 103-i is confirmed by any one of the chip select signals CSO# to CSN#, the DMA circuit 104 executes a memory access to a RAM 103-i other than the RAM 103-i concerned.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a direct memory access (hereinafter, referred to as "DMA").
That. In particular, the present invention does not require a bus arbitration circuit or a circuit for performing complicated timing control, and can avoid a memory access from the CPU and a bus conflict in the DMA with less hardware. The present invention relates to a DMA circuit that enables DMA with a hardware configuration.

[0002]

2. Description of the Related Art DMA is a data transfer system for exchanging data with a memory connected to a bus without passing through a CPU. Usually, a DMA controller for controlling data transfer by DMA is provided in a DMA circuit. In preparation for D
It is performed under the control of the MA controller. As a conventional DMA circuit capable of performing such a DMA transfer, for example, there is a DMA circuit shown in FIG. 5 described in Japanese Patent Application Laid-Open No. 6-187285. In this figure, a conventional DMA circuit includes a CPU 501 and a readable first
(Hereinafter referred to as “ROM”) 502 and a readable and writable second storage means (hereinafter referred to as “ROM”).
It is called "RAM". ) 503 and DMA controller 5
04 and an I / O 505.
1, a ROM 502, a RAM 503, and a DMA controller 504 are connected by a system bus 510 including a data bus and an address bus. When performing data transfer by DMA, the DMA controller 504
Holds the CPU 501 and puts the CPU 501 in a hold state (stop state), and then the DMA controller 504 secures the occupation right of the system bus 510 and the ROM 5 via the system bus 510.
02 or the RAM 503 to perform data transfer. If it is necessary to hold the CPU 501 and stop the execution of the CPU 501, the ROM 5 that performs DMA is used.
02 or the RAM 503 can be controlled to be disconnected from the system bus 510, and while the data transfer by the DMA is being executed, the ROM for performing the DMA from the CPU 501 is used.
Control was performed to prohibit access to 502 or RAM 503.

[0003]

However, in the above-described DMA circuit, in the system in which the CPU 501 is in the hold state (stop state) and the data is transferred by DMA, the CPU 501 cannot be used during the DMA transfer. Therefore, there is a problem that the utilization efficiency of the DMA circuit is poor. ROM 502 or RAM for performing DMA
The method of controlling the disconnection of the system bus 503 from the system bus 510 requires a bus arbitration circuit that arbitrates the right to use the system bus 510 and arbitrates access, a circuit that performs complicated timing control, and the like. When use conflicts, the CPU 501 or DM
Since the A transfer cannot be used, there has been a problem that the configuration and control of the hardware are complicated and the utilization efficiency of the DMA circuit is not improved. The present invention has been made in view of the above-described conventional problems, and eliminates the need for a bus arbitration circuit and a circuit for performing complicated timing control, and has a CP
An object of the present invention is to provide a DMA circuit capable of avoiding a bus contention in a memory access from the U and a DMA transfer with less hardware and enabling a DMA transfer with a low-cost hardware configuration.

[0004]

According to a first aspect of the present invention, there is provided a DMA circuit comprising: a CPU;
A system bus including a readable first storage unit and a readable and writable second storage unit, wherein the CPU, the first storage unit, and the second storage unit include a data bus and an address bus DM combined with
In the A circuit, a first bidirectional buffer for bidirectionally transferring data between the second storage means and the system bus, a direct memory access circuit, and a communication between the DMA circuit and the second storage means. A second bidirectional buffer for bidirectionally transferring data, wherein the DMA circuit includes a signal from the CPU to start a bus cycle, and the CPU controls the first storage unit and the second
Based on an access signal supplied to the storage means of
And performing memory access to said second storage means via said second bidirectional buffer. A DMA circuit according to a second aspect of the present invention is the DMA circuit according to the first aspect, wherein the DMA circuit performs a memory access to the second storage unit via the second bidirectional buffer. This is performed using an access signal supplied to the first storage means and the second storage means. In the DMA circuit of the present invention, the DMA circuit includes:
A signal from the CPU to start a bus cycle and C
Based on an access signal supplied from the PU to the first storage unit and the second storage unit, the PU performs memory access to the second storage unit via the second bidirectional buffer. Here, the “signal from the CPU to start a bus cycle” is, for example, a bus cycle start signal (hereinafter, “BCST”) issued by the CPU at the beginning of the bus cycle.
That. ), And when a multiplex bus, that is, a configuration in which an address bus and a data bus are shared by one bus, is used, addresses and data are transferred in this order, but are issued at the first address transfer. An address latch enable signal indicating that the address is valid also corresponds to this. The “access signal supplied by the CPU to the first storage means and the second storage means” includes a read / write signal issued when the CPU accesses the memory and indicating a read or write operation, A first storage unit to be accessed and a second storage unit
Corresponds to the chip select signal for specifying the storage means. In other words, in the DMA circuit of the present invention, for example, the CPU operates based on the bus cycle start signal or the address latch enable signal issued by the CPU, and the read / write signal and the chip select signal.
When it is confirmed that the memory access to the storage means is not performed, the DMA circuit performs memory access to the second storage means via the second bidirectional buffer. Therefore, in the DMA circuit of the present invention, priority determination of the right to use the bus, access inhibition control of the CPU during memory access by DMA transfer, and the like become unnecessary, and a bus arbitration circuit, a circuit for performing complicated timing control, and the like become unnecessary. DMA that can avoid bus contention in memory access from the CPU and DMA transfer with less hardware and enable DMA transfer with a low-cost hardware configuration
A circuit can be realized. In the DMA circuit of the present invention, D
The MA circuit performs memory access to the second storage unit via the second bidirectional buffer using an access signal supplied by the CPU to the first storage unit and the second storage unit. is there. For example, an access signal (read / write) based on a read / write signal issued by a CPU in a bus cycle and synchronized with the read / write signal.
The write circuit is issued by the DMA circuit to the second storage means, whereby the hardware required for generating the memory access signal has a simple configuration, and the DMA transfer is performed with a low-cost hardware configuration. D that enabled
An MA circuit can be realized.

[0005]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Hereinafter, embodiments of a DMA circuit according to the present invention will be described in detail in the order of [first embodiment] and [second embodiment] with reference to the drawings. Regarding the reference numerals of the signals used in the description of the embodiments, a signal with a symbol # added at the end of the reference numeral indicates that the signal is a negative logic signal. [First Embodiment] FIG. 1 is a block diagram of a DMA circuit according to a first embodiment of the present invention. In the figure, a DMA circuit according to the present embodiment includes a CPU 101 and a readable first
Storage means (ROM) 102 and second storage means (RAM) 103-1 to 103 readable and writable.
-N, a DMA circuit 104, and an I / O 105. Here, the CPU 101 and the ROM 102
And RAMs 103-1 to 103-N are connected to a data bus
This is a bus connection configuration connected to a system bus 110 including an address bus and various control signals. Also, RO
M102 and the data signal lines of the RAMs 103-1 to 103-N are connected to the system bus 110 via the first one-way buffer 106 and the first bidirectional buffers 108-1 to 108-N. Lines are also connected via an address buffer (not shown), and transfer control is performed by these buffer groups. The DMA circuit 104 and the ROM 102 are connected via a second one-way buffer 107 and an address buffer (not shown), and transfer data and addresses via the second one-way buffer 107 and the address buffer, respectively. Is performed. Further, the DMA circuit 104
And the RAMs 103-1 to 103-N are connected by second bidirectional buffers 109-1 to 109-N and an address buffer group, respectively.
-1 to 109-N and an address buffer group,
In this configuration, data and addresses are transferred bidirectionally. The signals TXD and RXD from the bidirectional serial port of the DMA circuit 104 are transmitted to the I / O 105
And the transfer address and transfer data are D
In this configuration, data is transferred bidirectionally between the MA circuit 104 and the I / O 105. Here, the activation / inactivation of the first one-way buffer 106 is controlled by the ROM 102 from the CPU 101.
Of the first bidirectional buffers 108-1 to 108-N is controlled by the RAM 103 from the CPU 101.
-1 to 103-N are respectively performed based on chip select signals CS1 # to CSN #. For the control of the activation / inactivation of the second one-way buffer 107 and the second bidirectional buffers 109-1 to 109-N, a bus cycle start signal BCST for starting a bus cycle is issued from the CPU 101. When
PU 101 is ROM 102 and RAMs 103-1 to 103-1
This is performed based on chip select signals CS0 # to CSN #, which are access signals issued when accessing 03-N. Specifically, a chip select signal CS0 # for selecting the ROM 102, RAMs 103-1 to 103-N
Select signals CS1 # to CS1
This is performed by a signal generated based on N #. For example, the CPU 101 issues a bus cycle start signal BCST in order to start a read operation on the ROM 102, and outputs a chip select signal CS for selecting the ROM 102.
When 0 # is made valid, the DMA circuit 104
103-1 to 103-N can be accessed. In this case, based on the source address or the destination address in the DMA transfer, the DMA circuit 104 accesses the RAM 103-i (i =
1 to N), the chip select signal to the RAM 103-i is made valid, and the connected second bidirectional buffer 109-i is activated. It goes without saying that one buffer on the read / write side is activated and the other is deactivated in response to the read / write operation. At the same time, the second bidirectional buffers other than the second one-way buffer 107 and the second bidirectional buffer 109-i are deactivated. As described above, in the DMA circuit of the present embodiment, the bus cycle start signal BCST issued by the CPU 101 and the chip select signals CS0 # to CS0
When it is confirmed that the CPU 101 performs memory access to the ROM 102 based on the SN # or the like,
RAM 103-i (i = 1 to N) by MA circuit 104
Is accessed via the second bidirectional buffer 109-i. In addition, the CPU 101
When it is confirmed by the chip select signal that the memory access to −i
Performs a memory access to a RAM other than the RAM 103-i. This eliminates the need for priority determination of the bus use right and access inhibition control of the CPU 101 during memory access by DMA transfer, and eliminates the need for a bus arbitration circuit and a circuit for performing complicated timing control.
Bus contention between memory access from the memory 101 and DMA transfer by the DMA circuit 104 can be avoided with less hardware, and a DMA circuit capable of DMA transfer with a low-cost hardware configuration can be realized.

[Second Embodiment] FIG. 2 is a block diagram of a DMA circuit according to a second embodiment of the present invention. The configuration diagram of FIG. 13 is the same as the configuration diagram of FIG.
M) is composed of one RAM 203 (N = 1), and DMA
FIG. 4 is a detailed circuit configuration diagram when the circuit 104 can access only the RAM 203. In the figure,
The DMA circuit of the present embodiment includes a CPU 201 and a ROM 20.
2, a RAM 203, and a DMA circuit 204. Here, the CPU 201, the ROM 202, and the RAM 203 have a bus connection configuration connected to a system bus 210 including a data bus, an address bus, and various control signals. The RAM 203 is connected to the system bus 210 via a CPU buffer 208. Also, a DM circuit is provided between the DMA circuit 204 and the RAM 203.
A buffer 209 is connected to the DMA buffer 20
9, data and addresses are transferred. Further, the serial ports (the sending port TXD and the receiving port RXD) of the DMA circuit 204 are connected to an I / O device or the like (not shown), and a transfer address and transfer data are transferred between the DMA circuit 204 and the I / O device. Configuration. Here, a detailed circuit configuration diagram of the CPU buffer 208 is shown in FIG. As shown in FIG.
An address buffer 208A for controlling address supply to the AM 203, bidirectional buffers 208R and 208W for controlling bidirectional data transfer between the CPU 201 and the RAM 203, and a gate G11 for generating a control signal for activating / deactivating these buffer groups. To G13. The activation / inactivation of the address buffer 208A is controlled based on a chip select signal CS1 # for selecting the RAM 203 by the CPU 201 and a bus cycle start signal BCST for instructing the CPU 201 to start a bus cycle. Becomes valid, the control signal output from the gate G11 becomes valid, the address buffer 208A is activated, and the CPU address is supplied to the RAM 203. The bidirectional buffer 2
08R and 208W, read buffer 208
The activation / inactivation of R is controlled by the chip select signal CS1.
# And a read signal RD # indicating that the CPU 201 executes a read cycle. When both signals become valid, the control signal R which is the output of the gate G13 is output.
AMR # becomes valid, and the read buffer 208R
Is activated, and the read data from the RAM 203 is supplied onto the system bus 210. Further, the activation / inactivation of the write buffer 208W is controlled based on the chip select signal CS1 # and the write signal WR # indicating that the CPU 201 executes a write cycle, and both of these signals become valid. At this time, the control signal RAMW #, which is the output of the gate G12, becomes valid, the write buffer 208W is activated, and the data on the system bus 210 is supplied to the RAM 203. On the other hand, the transfer control of the address and data in the DMA buffer 209 is performed by the bus cycle start signal B from the CPU 201.
This is performed based on the CST and a chip select signal CS0 # which is an access signal issued when the CPU 201 accesses the ROM 202. For example, the CPU 201
Starts a read operation on the ROM 202,
A bus cycle start signal BCST is issued, and the ROM
When the chip select signal CS0 # for selecting 02 and the read signal RD # are made valid, the DMA circuit 204 can access the RAM 203. In this case, the DMA circuit 204 makes the chip select signal DCS1 # in the DMA valid, makes the chip enable terminal CE # of the RAM 203 valid, and reads the read signal RD.
#, The read signal DMAARD # or the write signal DMAWR # is made valid, and the connected DMA buffer 209 is activated. Note that the chip select signal DCS
1 # is a signal generated based on the bus cycle start signal BCST. FIG. 3A shows a detailed circuit configuration diagram of the DMA buffer 209. As shown in the figure, the DMA buffer 209 includes an address buffer 209A for controlling the address supply from the DMA circuit 204 to the RAM 203, a DMA circuit 204 and the RAM 203.
Buffer 20 for controlling bidirectional transfer of data between
9R and 209W, and gates G21 to G23 that generate control signals for activating / deactivating these buffer groups. Activation of address buffer 209A /
The deactivation control includes a chip select signal DCS0 # for the CPU 201 to select the ROM 202 and a bus cycle start signal B indicating that the CPU 201 starts a bus cycle.
CST, and when both signals become valid, the control signal output from the gate G21 becomes valid, the address buffer 209A is activated and the DMA
The address is supplied to the RAM 203. The CPU 201 controls activation / inactivation of the read buffer 209R among the bidirectional buffers 209R and 209W.
Chip select signal DCS0 # for selecting OM202
And a read signal DMARD # to the effect that the DMA circuit 204 executes a read cycle. When both signals become valid, the control signal DMAR # output from the gate G23 becomes valid. The read buffer 209R is activated, and the read data from the RAM 203 is supplied to the DMA circuit 204. Further, the activation / inactivation control of the write buffer 209W is controlled by the CP
U201 is performed based on a chip select signal DCS0 # for selecting the ROM 202 and a write signal DMAWR # indicating that the DMA circuit 204 executes a write cycle. When both signals become valid, the output of the gate G22 is used. When a certain control signal DMAW # becomes valid, the write buffer 209W is activated and the DMA circuit 20
4 is supplied to the RAM 203.

Next, the operation of the DMA circuit of this embodiment will be described.
This will be described with reference to the timing chart shown in FIG. First, in order for the CPU 201 to start a read operation from the ROM 202, the bus cycle start signal BC
ST is issued (see FIG. 4A), and the system bus 210 is issued.
The address is output above (see FIG. 4B), and the CPU 20
When 1 makes the read signal RD # valid (see FIG. 4C), the read data from the ROM 202 is output to the system bus, and the CPU 201 takes in the read data. On the other hand, at this time, the RAM 2 of the DMA circuit 204
03 becomes accessible and the DMA circuit 20
4 starts an access operation. That is, while outputting the DMA address, the address buffer 209A of the DMA buffer 209 is activated, and the DMA address is supplied to the RAM 203 (see FIG. 4D). next,
In synchronization with the read signal RD # from the CPU 201, DM
A circuit 204 receives read signal RD # or write signal WR
When # is enabled, the read buffer 209R or the write buffer 209W of the DMA buffer 209 is
Is activated (see FIG. 4E), and the write data from the DMA circuit 204 is supplied to the RAM 203, or the read data from the RAM 203 is supplied to the DMA circuit 204. In this case, the DMA circuit 204
Enables the chip select signal DCS1 # in the DMA and sets the chip enable terminal CE #
(See FIG. 4F). As mentioned above,
In the DMA circuit of the present embodiment, the CPU 201 controls the ROM 20 based on the bus cycle start signal BCST and the chip select signal CS0 # issued by the CPU 201.
When the memory access to the RAM 203 is confirmed, the DMA circuit 204
A memory access via the A buffer 209 can be performed. Therefore, priority determination of bus use right and D
Access prohibition control or the like of the CPU 201 during memory access by MA transfer is not required, and a bus arbitration circuit and a circuit for performing complicated timing control are not required.
1 and DM by the DMA circuit 204
A bus circuit with the A transfer can be avoided with less hardware, and a DMA circuit capable of DMA transfer with a low-cost hardware configuration can be realized. Also, the DM of the present embodiment
In the circuit A, the DMA circuit 204 performs memory access to the RAM 203 via the DMA buffer 209,
Using the access signal (read signal RD #) of the CPU 201, the DMA circuit issues an access signal synchronized with the read signal RD # to the second storage means. The required hardware configuration is also simple.

[0008]

As described above, according to the DMA circuit of the present invention, based on the bus cycle start signal or address latch enable signal issued by the CPU, the read / write signal and the chip select signal, etc. Is determined that the memory access to the second storage means is not performed by the DMA circuit, the memory access to the second storage means is performed through the second bidirectional buffer. And the need for complicated timing control circuits
It is possible to provide a DMA circuit capable of avoiding bus contention in U and U memory access and DMA transfer with less hardware and capable of performing DMA transfer with a low-cost hardware configuration. Further, according to the DMA circuit of the present invention, the DMA circuit controls the memory access to the second storage means via the second bidirectional buffer, and the CPU controls the first storage means and the second storage means. Since the access is performed using the supplied access signal, the hardware configuration required for generating the memory access signal is simplified, and a DMA circuit capable of DMA transfer with a lower-cost hardware configuration can be realized.

[Brief description of the drawings]

FIG. 1 is a configuration diagram of a DMA circuit according to a first embodiment of the present invention.

FIG. 2 is a configuration diagram of a DMA circuit according to a second embodiment of the present invention.

FIG. 3A is a circuit configuration diagram of a DMA buffer according to a second embodiment, and FIG. 3B is a circuit configuration diagram of a CPU buffer.

FIG. 4 is a timing chart illustrating an operation of the DMA circuit according to the second embodiment.

FIG. 5 is a configuration diagram of a conventional DMA circuit.

[Explanation of symbols]

101, 201 CPU 102, 202 ROM (first storage means) 103-1 to 103-N, 203 RAM (second storage means) 104, 204 DMA circuit 105 I / O 106 first one-way buffer 107 2 one-way buffers 108-1 to 108-N first bidirectional buffers 109-1 to 109-N second bidirectional buffers 110 and 210 system bus 208 CPU buffers 209 DMA buffers 208A and 209A address buffers 208R , 209R read buffer 208W, 209W write buffer BCST bus cycle start signal CS0 # to CSN # chip select signal RD # read signal WR # write signal DCS1 # DMA circuit chip select signal DMARD # DMA circuit read signal DM WR # Write signal of DMA circuit RAMR #, RAMW #, DMAR #, DMAW # Control signal CE # Chip enable terminal G1, G11-G23 Gate TXD, Signal from serial port of RXD DMA circuit 501 CPU 502 ROM 503 RAM 504 DMA Controller 505 I / O 510 System bus

Claims (2)

[Claims] 1. A CPU, a readable first storage unit, and a plurality of readable and writable second storage units, wherein the CPU, the first storage unit, and the second storage unit A DMA circuit in which means are connected by a system bus including a data bus and an address bus, a first bidirectional buffer for bidirectionally transferring data between the second storage means and the system bus, and a direct memory access circuit And a second bidirectional buffer for bidirectionally transferring data between the direct memory access circuit and the second storage means, wherein the direct memory access circuit sets a bus cycle from the CPU. The plurality of second storages are performed based on a start signal and an access signal supplied by the CPU to the first storage unit. A memory access to a stage through the second bidirectional buffer; and a signal from the CPU to start a bus cycle and access to one of the plurality of second storage means. DM access to a second storage means other than the second storage means via the second bidirectional buffer based on a signal.
A circuit. 2. The readable first storage means,
In the DMA circuit including the second readable and writable second storage unit, the direct memory access circuit performs a memory access to the second storage unit via the second bidirectional buffer. 2. The DMA circuit according to claim 1, wherein the CPU performs the access using an access signal supplied to the first storage unit or the second storage unit.