JPH03296159A - Memory access system for dma device - Google Patents

Abstract

PURPOSE:To improve the direct memory access DMA transfer performance and to prevent the generation of a logic conflict by holding previously the ID information and a CM-IM boundary address in a common bus interface control part. CONSTITUTION:A DMA control part 43 designates a DMA via a control line 110 and suddenly gives a DMA address and the DMA data of a certain port to a common bus interface control part 42 via an address line 111 and a data line 112. The part 42 sends the DMA address, i.e., the output of a demultiplexer 113 and the DMA data, i.e., the output of a demultiplexer 114 to a common bus. At the same time, a comparator 118 compares the DMA address with the IM-CM boundary address of a register 117. Based on the result of this comparison, a selector 119 selects the CPU-ID or the CM-ID previously held in the registers 115 and 116. Then the ID information is sent to the common bus. Thus the DMA transfer performance is improved and at the same time a logic conflict is eliminated.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a multiprocessor system in which, under the control of a specific central processing unit (CPU) on a common bus, individual memory (IM) of the CPU or common memory (C
The present invention relates to a memory access method in a DMA device that executes a DMA (direct memory access) transfer operation for M).

[Conventional technology]

Figure 3 shows an example of the configuration of a multiprocessor system, in which n central processing units (C
PU) i, common memory (CM) 3 shared by each CPUI
, and the DMA device 4 are shown connected to the common bus 5. CPU1 and IM2 each have separate buses 6
connected with. Although not shown in FIG. 3, a file storage device, a communication line, etc. are connected to the DMA device 4. The DMA device 4 autonomously accesses the IM or CM of a specific CPU under the control of the CPU, and connects the IM or CM with an input/output device (1) such as a file storage device.
0).

FIG. 4 shows an example of a general configuration of a DMA device. A start control command from the CPU to the DMA device is received by the DMA control unit 43 via the common bus interface control unit 42. This is notified to the main control unit (MPU) 40 by an interrupt or the like, and is interpreted there. For example, in the case of reading data from the file storage device 8, the MPU 4.
0, ■○ bus interface control unit 44 and DMA
The control unit 43 is activated, and the bus interface control unit 44 transfers data from the file storage device 8 under the IO bus 7 to the data buffer 45, and the DMA control unit 43 transfers data from the data buffer 45 to the common bus interface. Data is transferred to the IM or CM via the unit 42 and the common bus 45. In the case of writing data to the file storage device 8, the MPU 40 similarly activates the DMA control unit 43 and the bus interface control unit 44, and the DMA control unit 43 controls the transfer from the IM or CM to the data buffer 45.
Further, the IO bus interface control section 44 performs transfer from the data buffer 45 to the file storage device 38, respectively.

Note that ■If bus 7 is capable of time division multiplexing, DMA
The control section 43 has a plurality of ports, and is often configured to accommodate a plurality of data buffers thereunder and operate them in parallel. FIG. 4 shows this case. R
The OM/RAM unit 41 holds programs/data that the MPU 40 executes/references/updates.

In this way, the CPU that controls the MA device is a specific CPU among a plurality of CPUs, and the DMA device accesses the IM or CM of the CPU under the control of the specific CPU. However, this one specific CPU is not always fixed, and the CPU that controls the DMA device may be switched, and if there are multiple DMA devices,
In some cases, separate CPUs control each DMA device.

By the way, the IM room space overlaps between multiple CPUs,
In order to access the IM of a certain CPU from a DMA device, in addition to the memory address, an I
It is necessary to add D information (CPU-ID). That is,
The DMA device accesses the IM using the combination of rID information J+r memory address. Note that when accessing the CM, it is possible to use ``rCM-IDJ+r memory address'' or ``memory address'' alone, and either can be used depending on the design conditions. This is because on the CM side, since there are no duplicate addresses, it is possible to determine that the message is addressed to itself from the address information alone.

Conventionally, in a multiprocessor system as shown in Figure 3, D
When an MA device accesses IM or CM, the necessary I
D information and memory address information are DM in FIG.
It was prepared on the A control unit side and transferred from there to the common bus via the common bus interface control unit. This will be specifically explained using FIGS. 5 and 6.

FIG. 5 shows a conventional configuration example of part of the common bus interface control section and DMA control section in FIG. 4. One common bus interface control section and one DMA control section each.
When converting a chip into an LSI, the common bus interface control section in particular has address/data lines with the common bus interface and the DMA control section, so the number of terminals of the LSI increases, causing a problem in the number of terminals. In order to prevent this increase in the number of terminals, the common bus interface control section is generally
It does not have a dedicated ID information input terminal between it and the A control section, and for this reason, the conventional method was to multiplex transfer ID information and memory address information between the common bus interface control section and the DMA control section. be.

In FIG. 5, 501 is a selector (SEL) for selecting one of the DMA addresses corresponding to the two accommodated ports using a predetermined time division control logic, and 502 is a selector (SEL) for selecting one of the DMA addresses corresponding to the two accommodated ports; Selectors 503, 504, and 505 are registers that hold CPU-ID information, CM-ID information, and IM-CM boundary address, respectively, and these pieces of information are set in advance by initial settings. 506 is a comparator (CMP) that compares the magnitude relationship between the DMA address and the IM-CM boundary address; 507 is a selector that selects either CPU-ID or CM-ID according to the output of CMP 506; 508 and 509 are selectors that output one of a register address and a DMA address, and one of ID information and DMA data under the control of the register access/DMA control line 510, respectively. 511 is an address line, and 512 is a data line. 513 and 514 are demultiplexers (DMPX) that distribute addresses and data input from the address line 511 and data line 512, respectively, to either the common bus side or within the common bus interface control unit; 515 is a register address decoder; 516 is a register address decoder; This is a register (IDR) that holds ID information from the DMA control unit. 517 is another register.

When performing DMA operation, first register access/DMA
The control line 510 indicates the register access side, and the CM determines whether the DMA address from the selector 501 is addressed to the IM or the CM.
P 506 and register 5 is determined according to the result.
Either the CPU-ID or CM-ID of 03 or 504 is the selector 507, 509, the data line 512,
It is set on IDR 516 via demultiplexer 514. Subsequently, the register access/DMA control line 51
0 switches to the DMA side, and the DM from the selector 501
The DMA data from the A address and register 502 is
ID selected by selectors 508 and 509, demultiplexers 513 and 514, and output from IDR516.
It is sent to the common bus along with the information.

Figure 6 is the above-mentioned operation sequence diagram, where ■ ID information I
It shows that the DMA address, data, and ID information are sent to the common bus in the order of write operation to DR, and (2) actual DMA operation. The above operation is performed by the DMA device.
This applies to data writing to M or CM, but the same applies to data reading.

[Problem to be solved by the invention]

The memory access method of the conventional DMA device described above has the following drawbacks.

(1) In order to prevent an increase in the number of terminals, the common bus interface control unit does not have a dedicated ID information input terminal between it and the DMA control unit (i.e., when receiving data via a general-purpose data transfer line) , ID information and memory address (DM
A address) is divided into two parts and sent to the common bus interface control unit, which deteriorates the performance of DMA transfer.

(2) The DMA control unit has multiple ports on the lower side (IO side), and multiple buffers and memories (IM/
CM), if ID information and memory address information are not controlled in pairs, logical contradictions will occur, so pair control is required. The amount of gold is the overhead.

SUMMARY OF THE INVENTION An object of the present invention is to provide a memory access method for a DMA device that solves the above-mentioned conventional drawbacks.

[Means to solve the problem]

In order to achieve the above object, the present invention focuses on the fact that the CPU that controls the DMA device is limited to one specific one, and the memory accessed by the DMA device is the IM or CM of the CPU. ID information of ID and CM-ID, and CM
- IM boundary address is held in advance in the common bus interface control unit, and at the time of DMA transfer, only the memory address is given from the DMA control unit, and the common bus interface control unit stores the memory address and the CM-ID.
Compare DMA address and find CPU-ID or CM-I
The present invention is characterized in that the ID information of D is selected, and the selected ID information is added to a memory address and sent to the common bus.

Note that the CM-ID is stored in the common bus interface control unit.
Instead of holding the information, the common bus interface control unit may add CPU-ID information to the memory address and send it to the common bus only at the time of IM access.

[For production]

In the present invention, since the ID information is generated within the common bus interface control section, there is no need to send it out from the DMA control section. It is sufficient to send only the memory address from the DMA control unit. Therefore, there is no need for the DMA $1 controller to send the ID information and memory address twice to the common bus interface #IJ controller.
There is no fear of logical contradictions even in the case of time division multiplexing operation.
There is no need to control ID information and memory addresses in pairs.

〔Example〕

An embodiment of the present invention will be described below with reference to FIGS. 1 and 2.

FIG. 1 is a configuration diagram of an embodiment of a common bus interface control section and a DMAMfH section of a DMA device according to the present invention. The overall configuration of the DMA device is the same as that shown in FIG. 4, and an example of the configuration of the multiprocessor system to which the present invention is applied is as shown in FIG.

In FIG. 1, 101 is a selector for selecting one of the DMA addresses corresponding to two accommodated boats using a predetermined time division control logic, and 102 is also for selecting two DMA write data corresponding to each boat. The selectors 501 and 502 in FIG.
corresponds to 110 is a register access/DMA control line, 111 is an 11-2-address line, and 112 is a data line. 113 and 11
4 inputs the address on line 111 and the data on line 112 by a signal on register access/DMA control line 110.
This is a demultiplexer (DMPX) that allocates the internal register of the common bus interface control unit to the common bus. 115°116 and 117 are CPU-
IDfl! 118 is a comparator (CMP) that compares the magnitude relationship between the DMA address and the IM-CM boundary address, and 119 is the output of CMP i 18. This is a selector (SEL) that selects either the CPU-ID or the CM-ID depending on the CM-ID, and these are provided on the DMA control section side in FIG.

FIG. 2 shows an operation sequence diagram for the case of FIG. That is, when performing DMA, there is no need to set ID information in the common bus interface control unit 42 as in the conventional case, and the DM
The A control unit 43 specifies DMA using the control line 110,
Suddenly, the DMA address and DMA data of a certain boat are given to the common bus interface control unit 42 via the address line 111 and the data line 112. The common bus interface controller 42 sends the DMA address that is the output of the demultiplexer 113 and the DMA data that is the output of the demultiplexer to the common bus. At the same time, a comparator 118 compares the magnitude relationship between the DMA address and the IM-CM boundary address in the register 117, and depending on the comparison result, the CPU-ID or CM - Select the ID with the selector 119 and send the ID information to the common bus.

This applies to writing data to memory, but the same applies to reading data.

As described above, with the configuration shown in FIG. 1, ID information and DMA address/data can be sent to the common bus in one step.

Furthermore, it is clear from a comparison between Figures 1 and 5 that the number of hardware stores has been reduced compared to the past.

Note that in the above embodiment, one CM is connected to the common bus, and one CM-ID is used to identify it. However, depending on the system, a plurality of CMs may be connected on a common bus and -dimensional addresses may be assigned to them, but this can be implemented in the same way.

That is, in the case of such a system, not only the IM-CM boundary address but also the intra-CM boundary address is held in advance in the common bus interface control unit, and correspondingly, a plurality of CM-ID information is also held, and the DMA The memory address input from the control unit and the boundary address may be compared, and predetermined CM-ID information may be separated and output to the common bus.

In addition, in the case of a CM address, even if there is no ID information, the CM address
Since the M side can determine whether the message is addressed to itself, there is no need to add ID information from the DMA device.

Even in this case, the effects of the present invention remain unchanged.

〔Effect of the invention〕

As explained above, according to the present invention, since the ID information is generated within the common bus interface control unit, the DMA
The control unit only needs to send the memory address, and there is no need to send the ID information and the memory address twice, improving the performance of DMA transfer. Furthermore, the ID information is generated within the common bus interface control unit and transferred to the D
Since there is no need to send data from the MA control unit, the DMA control unit has multiple ports on the lower level (IO side) and time-sharing transfers between multiple buffers connected to these ports and memory (IM/CM). Even if the function has multiple execution functions, the ID
There is no need to control information and memory addresses in pairs, and there is no fear of logical contradictions occurring.

[Brief explanation of the drawing]

FIG. 1 is a configuration diagram showing an embodiment of a common bus interface control section and a DMA control section of a DMA device according to the present invention, FIG. 2 is a sequence diagram for explaining the DMA operation of FIG. 1, and FIG. A diagram showing an example of the configuration of a multiprocessor system to which the present invention is applied, FIG. 4 is an overall configuration diagram of a DMA device, and FIG. 5 is a diagram showing an example of the configuration of a conventional common bus interface control unit and a DMA control unit. Figure 6 is D of Figure 5.
5-6- It is a sequence diagram for explaining MA operation. 1...Central processing unit (CPU), 2...CP
U individual memory (IM), 3... Inter-CPU common memory (CM), 4... DMA device, 5... Common bus, 42... Common bus interface control unit, 43...
・DMA control unit, 115... CPU-IP holding register, 116... CM-ID holding register, 1
17...IM-CM boundary address holding register. (7) Both figures 1 and 5 (see AD It)

Claims (2)

[Claims] (1) A multiprocessor in which multiple central processing units (CPUs), a common memory (CM) of each CPU, and a DMA (direct memory access) device are connected to a common bus, and each CPU has an individual memory (IM). In the system, the DMA device performs DMA processing under the control of a specific CPU.
a common bus interface control unit that interfaces with the common bus in order to autonomously access the IM or CM; a DMA control unit that is connected to the common bus interface control unit and controls address transmission to the IM or CM; The common bus interface control unit includes CPU-ID information for identifying a CPU, CM-ID information for identifying a CM,
means for holding an IM-CM boundary address; and a means for holding an IM-CM boundary address;
The memory address given from the A control unit and the IM-C
A DMA characterized in that it has means for comparing M boundary addresses, selecting the CPU-ID information or CM-ID information, and sending the selected ID information to the common bus together with the memory address. Device memory access method. (2) The CM-
DMA according to claim 1, characterized in that the common bus interface control unit stops holding ID information and adds CPU-ID information to a memory address and sends it to the common bus only when accessing an IM. Device memory access method.