JP2583586B2 - Bus control method - Google Patents

Description

Description: BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a bus control method for transferring data between a processor and a memory.

2. Description of the Related Art Protocols (communication rules) regarding formats and correction methods when data are transmitted between computers or between a computer and a terminal or other device are referred to as protocols.
Various protocols have been announced so far. Similarly, several methods for transferring data between a processor and a memory inside a computer are known.

As one of them, there is a bus control system in which an address bus and a data bus are separated and data transfer between a processor and a memory can be performed in both a single transfer mode and a sequential transfer mode. FIGS. 3 and 4 show, for example, “Intel MULTIB
FIG. 3 is a timing chart of the bus transfer method shown in the "US II Bus Architecture Specification Manual", FIG. 3 shows a case of a single transfer operation, and FIG. 4 shows a case of a sequential transfer operation. .

In FIG. 3, (1) is a bus request (XBUSREQ) signal issued by a transfer source (hereinafter, referred to as a master) to acquire a bus, and (2) is a bus request (hereinafter, referred to as a slave) transmitted to the master. A bus approval granting permission to use the bus (XBUSAC
K) signal, (3) an access request (XACCREQ) signal indicating activation of an address or a command, (5) a data line (XD) signal, and (6) a read access wait from the slave side to the master side. Is a wait (XWAIT) signal.

Further, (1) to (6) in FIG. 4 are signals similar to those in FIG. 3, and (7) is a block transfer control (XBTCTL) signal indicating block transfer.

 Next, the operation will be described.

First, the operation at the time of the single transfer shown in FIG. 3 will be described. The master uses XBUS to acquire the bus during bus transfer.
Activate the REQ signal (1). The slave activates the XBUSACK signal (2) when it becomes possible to accept the master's request, and returns an access permission to the master. Master is XBUS
Upon seeing the activation of the ACK signal (2), it outputs an address and a command signal (3), activates the XACCREQ signal (4) that notifies the slave of the start of access, and performs a read or write operation.

Next, the sequential transfer operation will be described with reference to FIG. In the figure, the operations of (1) to (4) are the same as those of FIG. 3, but while the XBTCTL signal (7) indicating the sequential transfer is activated, data continuously appears on the bus, The transfer is performed by the XWAIT signal (6) and the XBTCTL signal (7).

[Problems to be Solved by the Invention] The conventional bus control system of the address / data bus separation system operates according to the protocol described above, and the address lines are not used for the sequential transfer as compared with the address / data multiplex system. However, there has been a problem that the use efficiency of the signal line is low and the data transfer speed is low. Therefore,
There is a problem that the above problems must be solved.

SUMMARY OF THE INVENTION The present invention has been made to solve the above problems, and has as its object to provide a bus control method that can effectively use signal lines on a bus and almost double data transfer throughput.

Means for Solving the Problems In a bus control method according to the present invention, an address bus and a data bus are separated, and data transfer between a processor and a memory can be performed by both single transfer and sequential transfer. On the processor side, an address buffer connected to an address bus and capable of controlling the output of internally stored address data; and an output buffer connected to the data bus and outputting internally stored data to the data bus, or A first data buffer capable of capturing data of the bus,
A second data buffer connected to the address bus and capable of outputting internally stored data to the address bus or taking in data of the address bus; and Connected
An address counter that stores the address value sent from the address buffer and sequentially increments the stored address value in the case of sequential transfer, and a data bus that is connected to a data bus and stores data therein. A third data buffer capable of outputting to the bus or taking in data of the data bus, and connected to the address bus and outputting data stored therein to the address bus or taking in data of the address bus; A possible fourth data buffer;
A data direction control signal line for controlling the data transfer direction is connected to each of the data buffers
In a control system, the second
And with the input and output of the fourth data buffer disabled,
The address transfer from the address buffer to the address counter on the address bus and the data transfer between the first data buffer and the third data buffer on the data bus are simultaneously performed in accordance with the direction specified via the data direction control signal line. At the time of the sequential transfer, the transfer of the address from the address buffer to the address counter on the address bus is performed in a state where the input and output of the second and fourth data buffers are prohibited, and thereafter the operation of the address buffer is prohibited. When a predetermined count state is reached, input / output of the second data buffer and the fourth data buffer is permitted, and the second data buffer using the address bus is used in accordance with the direction specified through the data direction control signal line.
Data transfer between the data buffer and the fourth data buffer and data transfer between the first data buffer and the third data buffer using a data bus are performed.

[Operation] In the bus control method according to the present invention, in the system having the above-described configuration, data transfer is performed by using the data bus at the time of single transfer, and data is transferred by using both the data bus and the address bus at the time of sequential transfer. Added transfer. Therefore, it is possible to increase the data transfer capability from the processor to the memory or from the memory to the processor by effectively utilizing the vacant address bus at the time of the sequential transfer.

Hereinafter, an embodiment of the present invention will be described with reference to the drawings.
FIG. 1 is a block diagram of a bus control system according to an embodiment of the present invention.

In the figure, (10) is an address buffer on the master side, (11) is an address control signal line for controlling the address buffer (10), and (12) and (13) are upper data buffers on the master side and slave side, respectively. , (14), (15)
Are the lower data buffers on the master and slave sides, respectively.
(16) is a master / slave data output control signal line, (17) is a master / slave data direction control signal line, and (18) is a slave address counter.

Next, the operation of the above embodiment will be described with reference to the timing chart shown in FIG. (1), (2), (4),
(6) and (7) are the same as the prior art shown in FIG. (8) shows a bus signal (XDH) obtained by multiplexing upper bits of an address and data by sequential transfer, and (9) shows a bus signal (XDL) for transferring lower bits of data.

Since the single transfer operation is the same as that of the prior art, a description thereof will be omitted. In this single transfer operation, only the lower data buffers (14) and (15) shown in FIG. 1 are used for data transfer, and the upper data buffer (12). , (13) are left unused.

 Hereinafter, the case of the sequential transfer operation will be described.

The master uses XBUSRE to acquire the bus during bus transfer.
Activate the Q signal (1). When the master becomes ready to accept the request, the slave activates the XBUSACK signal (2) and returns an access permission to the master. Master is XBUS
Upon seeing the activation of the ACK signal (2), it outputs an address or a command signal (8), activates the XACCREQ signal (4) notifying the slave of the start of access, and performs a read or write operation. While the XBTCTL signal (7) for instructing sequential transfer is activated, data appears continuously on the bus,
The transfer is controlled by the XWAIT signal (6) and the XBTCTL signal (7).

Upon acquiring the bus, the master activates the address control signal line (11) of the address buffer (10) in FIG. 1 and outputs the address (XA) to the slave as REQ2. At this time, the data output control signal line (16) connected to the data buffers (12) to (15) is still inactive, and data transfer has not been started.

Next, the slave loads the address into the address counter (18) by the XACCREQ signal (4) of the master. The master side indicates the sequential transfer by the XBTCTL signal (7), and sequentially transfers data by the XWAIT (6).

A feature of the present invention is that an address bus is used for data transfer in addition to a normal data bus, and the upper data buffers (12) and (13) shown in FIG. Perform a transfer.

At this time, the address control signal line (11) is inactive, and after the address transfer of the REQ2, the address buffer (10) does not send the address to the address bus, and opens the address bus for data transfer.

On the other hand, the upper and lower data buffers (12) to (15) of both the master / slave control the data output control signal (1
6), and the data direction control signal (17) is switched by the read / write operation. As a result, at the time of sequential data transfer, data also flows to the address line, and as shown in FIGS. 2 (8) and (9), the data transfer throughput is increased about twice.

That is, in the figure, the lower data buffer (14),
(15) is the same as before, using the data bus to
(1), (3), and (5) are transferred, and at the same time, the upper data buffers (12) and (13) transfer DATA (2), (4), and (6) using the address bus, which used to be idle. I do.

In the above embodiment, the operation of only the sequential transfer is described. However, even a single transfer can be performed once twice as long as the data width so far.
The transfer throughput can be almost doubled.

[Effect of the Invention] As described above, according to the present invention, by adopting the configuration in which the address line at the time of the sequential transfer can be used as the data line, about twice the throughput can be obtained as compared with the conventional address / data separated type data transfer. Thus, the data transfer speed can be almost doubled.

[Brief description of the drawings]

FIG. 1 is a block diagram of an embodiment of a bus control system according to the present invention, FIG. 2 is a timing chart showing the operation of the system of FIG. 1, and FIGS. FIG. 4 is a timing chart showing a single transfer operation and a sequential transfer operation of the bus control system of the data separation system. In the figure, (10) is an address buffer on the master side, (11) is an address control signal line, (12) and (14) are upper and lower data buffers on the master side, and (13) and (15) are upper parts on the slave side. , A lower data buffer, (16) a data output control signal line, (17) a data direction control signal line, and (18) a slave address counter for counting addresses during sequential transfer. In the drawings, the same reference numerals indicate the same or corresponding parts.

Claims (1)

(57) [Claims] An address bus and a data bus are separated from each other, so that data transfer between a processor and a memory can be performed by a single transfer method or a sequential transfer method. An address buffer that can control the output of address data stored in the data bus, and a first data buffer that is connected to the data bus and that can output internally stored data to the data bus or take in data from the data bus And a second data buffer connected to the address bus and capable of outputting internally stored data to the address bus or capturing data of the address bus. Connected to a bus and stores the address value sent from the address buffer, and in the case of sequential transfer, An address counter for sequentially incrementing the stored address value; a third data buffer connected to the data bus and capable of outputting internally stored data to the data bus or capturing data from the data bus; A fourth data buffer connected to the address bus and capable of outputting data stored therein to the address bus or taking in data of the address bus; and In a bus control system in which a data direction control signal line for controlling a data transfer direction is connected to a data buffer, in a single transfer, input and output of a second and a fourth data buffer are prohibited and an address bus is used. Transfer of an address from an address buffer to an address counter; A state in which data transmission between the first data buffer and the third data buffer on the data bus is simultaneously performed in accordance with a direction specified through a signal line, and input and output of the second and fourth data buffers are prohibited during sequential transfer. Then, the address is transferred from the address buffer to the address counter on the address bus, and then the operation of the address buffer is prohibited. The address counter enters a predetermined count state, and the input of the second data buffer and the fourth data buffer is performed. Permitting output, transferring data between a second data buffer and a fourth data buffer using an address bus, and a first data buffer using a data bus in accordance with a direction specified via the data direction control signal line. Bus data transfer between a data buffer and a third data buffer .