JPH05143531A - Data processor - Google Patents

Abstract

PURPOSE:To improve the throughput of data processor which transfers data through the use of a common data bus between plural CPUs. CONSTITUTION:The data processor is constituted in such a way that plural CPUs 2 and 3 are connected with a common data bus 1, the data bus 1 and CPUs 2 and 3 are connected to a bus arbiter 4 which controls the usage state of the data bus by CPUs, the bus arbiter 4 is connected to a data buffer 13, transfer data is stored from transmission side CPU to the data buffer 13 with the data bus 1 and the bus arbiter 4 when data is transferred between CPUs 2 and 3 and transfer data stored in the data buffer 13 is transferred to reception side CPU with the bus arbiter 4 and the data bus 1.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a data processing device in which a plurality of CPUs perform data processing operations in parallel and data transfer operations are performed among the CPUs.

In recent data processing apparatuses, a plurality of CPUs are provided and each CPU performs data processing operations in parallel to improve system throughput, and after the processing operations are completed, data is transferred between the CPUs. There is something like this. In such a data processing device, data transfer between the CPUs is performed by one common bus system, so that an increase in the bus usage rate of the common bus system becomes an obstacle to the improvement of the system throughput.
Therefore, it is required to reduce the bus usage rate of the common bus system to improve the system throughput.

[0003]

2. Description of the Related Art An example of a conventional data processor will be described with reference to FIG.
U2 and 3 are connected, and data can be transferred between the first and second CPUs 2 and 3 via the data bus 1. A bus arbiter 4 that manages the usage state of the data bus 1 is connected to the data bus 1, the bus arbiter 4 and the first CPU 2 are connected by a control signal line 5, and the bus arbiter 4 and the second CPU 2 are connected. The CPU 3 is connected by a control signal line 6.

To explain the transfer operation of such a data processor, for example, when transferring data from the first CPU 2 to the second CPU 3, the first CPU 2 first uses the bus line arbiter via the control signal line 5. The bus use request is output to 4. Then, the bus arbiter 4 determines whether or not the data bus 1 is available, and if available, outputs a bus use permission to the first CPU 2 via the control signal line 5, and at the same time outputs the second CPU 3 The data reception request is output to.

After the handshake operation as described above, the first
The CPU 2 transfers data of 1 word consisting of, for example, 8 bits or 16 bits to the second CPU 3 via the data bus 1. The handshake operation as described above is repeated each time one word is transferred, and the data in units of one word is sequentially transferred from the first CPU 2 to the second CPU 3.

In addition, from the second CPU 3 to the first CPU 2
When data is transferred to, the same handshake operation is repeated and the data in units of 1 word is sequentially transferred.

[0007]

However, in the above data processing device, since the capacity of the registers incorporated in the CPUs 2 and 3 is small, every time one word data consisting of 8 bits or 16 bits is transferred. CP to transfer
A handshake operation between U is required. Therefore, each C
If the operation speed of the handshake input / output circuit of the PU is low, it takes a lot of time to transfer the transfer data composed of a large number of words, and the time for occupying the data bus 1 becomes long. However, there is a problem in that the transfer operation is disabled and the system throughput is reduced.

Further, when data is transferred between the two CPUs 2 and 3, it is necessary to set both the CPUs 2 and 3 in a transfer mode in synchronization with each other. Therefore, an interrupt operation is performed on the receiving CPU, or There has been a problem in that the receiving CPU may not be able to receive a reception request, thus reducing the system throughput.

An object of the present invention is to improve the throughput of a data processing device that transfers data using a common data bus among a plurality of CPUs.

[0010]

FIG. 1 illustrates the principle of the present invention. That is, a plurality of CPUs 2 and 3 are connected via a common data bus 1, and a bus arbiter 4 that manages the usage state of the data bus by the CPUs is connected to the data bus 1 and the CPUs 2 and 3, and the bus arbiter 4, a data buffer 13 is connected to the CPU
When data is transferred between 2 and 3, the transfer CPU stores the transfer data in the data buffer 13 via the data bus 1 and the bus arbiter 4, and the transfer data stored in the data buffer 13 is the above-mentioned data. It is transferred to the receiving side CPU via the bus arbiter 4 and the data bus 1.

[0011]

According to the control of the bus arbiter 4, the data transferred from the transmitting side CPU is first stored in the data buffer 13 via the data bus 1 as continuous data of the maximum buffer length, and then from the data buffer 13 to the data bus 1. Is continuously transferred to the receiving side CPU via.

[0012]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment embodying the present invention will now be described with reference to FIG.
Follow the instructions below. The same components as those of the conventional example will be described with the same reference numerals.

The first to fourth CPUs 2, 3, 7 and 8 are respectively connected to the data bus 1 and data can be input / output to / from the data bus 1. In addition, the first to fourth CPUs 2, 3, 7, and 8 have control signal lines 5, 6, 9, and 10 respectively.
Are respectively connected to the bus arbiter 4 via the, and handshake signals are exchanged between the first to fourth CPUs 2, 3, 7, 8 and the bus arbiter 4.

The data bus 1 is a buffer manager 1
1 and the buffer manager 11 is connected to the bus arbiter 4 via a control signal line 12.
Further, the first to fourth CPUs 2, 3, 7, and 8 are connected to the buffer manager 11 via the control signal line 12, and output strobe signals for reading and writing to the data buffer 13 described later. ing.

A data buffer 13 is connected to the buffer manager 11 via a buffer bus 14, and the data output from the first to fourth CPUs 2, 3, 7, 8 to the buffer manager 11 is transferred to the buffer bus 14. It is designed to be temporarily stored via.

The operation of transferring data from the first CPU 2 to the third CPU 7 in the data processing apparatus configured as described above will be described below. First, the first CP will be described.
U2 outputs a transfer request to the bus arbiter 4 via the control signal line 5. Then, the bus arbiter 4 determines whether or not the data bus 1 is in use at that time, and outputs a bus use permission to the first CPU 2 if it is not in use.

The first CPU 2 which has received the use permission outputs a strobe signal to the buffer manager 11 via the control signal line 12 and outputs data to the buffer manager 11 via the data bus 1. At this time, the strobe signals other than those of the first CPU 2 are also output to the buffer manager 11, but the buffer manager 11 is controlled by the bus arbiter 4 and validates only the strobe signal output from the first CPU 2.

Haffa manager 11 receiving the data
Sets an appropriate buffer address and sequentially stores the received data in the data buffer 13 based on the buffer address.

When the first CPU 2 finishes transferring the data to the buffer manager 11, the first CPU 2 outputs a transfer end signal to the bus arbiter 4. Then, the bus arbiter 4 outputs a reception request signal to the third CPU 7,
The third CPU 7 receiving the reception request receives the data buffer 13
The data read from is received via the buffer manager 11 and the data bus 1.

As described above, in this data processing device, C
When data is transferred between PUs, the CP on the sending side is first
Data is transferred from U to the data buffer 13 via the data bus 1, and then transferred from the data buffer 13 to the receiving CPU via the data bus 1. Therefore, since the transfer data can be continuously transferred word by word without the need for a handshake operation, the occupied time of the data bus 1 can be reduced and the overall throughput of this data processing device is improved. be able to.

Further, since the transfer data is stored in the data buffer 13, one transmission side CPU can receive a plurality of reception side Cs.
When the same data is transferred to the PU, the data buffer 13 may sequentially perform the transfer operation to each receiving CPU. Therefore, when performing the transfer operation between one transmitting CPU and a plurality of receiving CPUs, respectively. The transfer time can be shortened compared to. Furthermore, in each receiving CPU, the sending CP
It is not necessary to synchronize the transfer operation with U, and the data may be read from the data buffer 13 after other data processing operations are completed. Therefore, the software for the read operation can be simplified, and the entire system can be simplified. The data processing operation can be performed efficiently.

[0022]

As described above in detail, the present invention exerts an excellent effect that the throughput of the data processing device for transferring data using a common data bus among a plurality of CPUs can be improved. ..

[Brief description of drawings]

FIG. 1 is a diagram illustrating the principle of the present invention.

FIG. 2 is a block diagram showing an embodiment of the present invention.

FIG. 3 is a block diagram showing a conventional example.

[Explanation of symbols]

 1 data bus 2,3 CPU 4 bus arbiter 13 data buffer

Claims (1)

[Claims] 1. A plurality of CPUs (2, 3) are connected via a common data bus (1), and the data bus (1) and the CPU (2, 3) are When a bus arbiter (4) for managing the usage state is connected, a data buffer (13) is connected to the bus arbiter (4), and when data is transferred between the CPUs (2, 3), the transmission side CPU Transfer data is stored in the data buffer (13) via the data bus (1) and the bus arbiter (4), and the transfer data stored in the data buffer (13) is transferred to the bus arbiter (4) and the data bus (1). ) To the receiving CPU via the data processing device.