JPH07334453A - Memory access system - Google Patents

Abstract

PURPOSE:To shorten occupancy time for an extended bus in an information processing system having the extended bus for extending an I/O controller in addition to a basic bus connected to a main memory. CONSTITUTION:A read address and an own device BM address are sent to the extended bus 6 by regarding DMA read operation from each of I/O controllers 51 to 5n as write operation. A bus adaptor 4 respectively stores the read address and the BM address in an access address buffer 41 and a write data buffer 42 and then releases the bus 6. The adaptor 4 accesses a memory by using the read address through a reference bus 3 and stores read data in a read data buffer 43. Then the adaptor 4 sends the BM address stored in the buffer 42 and the read data stored in the buffer 43 to the bus 6 in order to execute write operation. The read data are written in a buffer memory 101 in the I/O controller corresponding to the MB address.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a memory access system, and in particular, an expansion bus is provided in addition to the basic bus of the system for expanding an input / output (IO) control unit, and IO is provided via this expansion bus and the basic bus. The present invention relates to a memory access system in which a controller accesses a main memory.

[0002]

2. Description of the Related Art FIG. 3 shows a schematic block diagram of a conventional memory access system of this type. In FIG. 3, CPU1
The main memory 2 and the main memory 2 are connected to the basic bus 3 of the system, and the IO control units (PCU) 51 to 5n are connected to the expansion bus 6, respectively. Has been.

A bus adapter (BADP) 4 is connected between the expansion bus 6 and the basic bus 3, and memory access to the main memory 2 from each IO control device 51 to 5n is performed via the expansion bus 6. Transmitted to the adapter 4,
Further, the data is transmitted from the bus adapter 4 to the main memory 2 via the basic bus 3.

FIG. 4 is a timing chart showing an operation example of the memory access system of FIG. 3, wherein the upper chart shows the time chart of the expansion bus 6 and the lower chart shows that of the basic bus 3.

In the figure, "AD / D" means address / data, and the address and data are ready for time division transfer. Further, "bus valid" indicates that a unit (BADP or PCU) that has acquired the bus use right is using the bus, and "bus response" indicates a response signal returned by the response unit for the bus transfer. . Further, "bus request" indicates a signal for the BADP to make an access request to the main memory, and "bus permission" indicates a signal for permitting the memory access from the BADP.

In the time chart of FIG. 4, one I
The figure shows a case where a read access (DMA read: direct memory access read) from the O control unit (PCU) to the main memory is executed twice, where AD1 is the first read access address and AD2 is the second read access address. Are shown respectively. Each read access causes the expansion bus 6 to be exclusively occupied, and the bus adapter (BAD
P) 4 receives these read accesses and the main memory 2
Until the read data D1 and D2 are respectively read out to the IO controller via the expansion bus 6, the exclusive state of the expansion bus 6 is maintained.

Japanese Unexamined Patent Publication No. 2-272666 discloses IO
When a DMA transfer request is issued from the control device, another IO
For the purpose of reducing the waiting time of the control device and performing efficient data transfer, a FIFO (first in, first out) type buffer memory is provided, and DM is provided via this FIFO memory.
A technique for performing A transfer is disclosed.

[0008]

In the conventional memory access system shown in FIG. 3, since the memory read access from the IO control device is an interlock system having both the expansion bus and the basic bus, the IO control is performed. There is a drawback in that the system performance drops significantly as the number of connected devices increases.

In the technique disclosed in Japanese Patent Laid-Open No. 2-272666, the basic bus of the system can be used efficiently, but the expansion bus to which the IO controller is connected cannot be used efficiently.

An object of the present invention is to provide a memory access system capable of improving the usage efficiency of the expansion bus by shortening the exclusive time of the expansion bus to which the IO controller is connected.

[0011]

[Means for solving the problems]. According to the present invention, a main memory, a basic bus for transmitting an access address and access data to the main memory, an expansion bus, and a plurality of input / output control devices connected to the expansion bus are included. A memory access system in which read access from an output control device to the main memory is performed via the expansion bus and a basic bus, and the read access request to the main memory is provided at the same time in each of the input / output control devices. Means for generating a device address for identifying its own device and sending it to the expansion bus; and control means for temporarily storing the request address and the device address at the time of the read access request and controlling the expansion bus in a release state at the same time. The stored request address is sent to the basic bus and is returned to the main memory. Access means for performing a read access, read data storage means for temporarily storing read data by the read access, and the stored read data and the stored device address to the device address via the expansion bus. A memory access system is provided which includes a sending means for sending to a corresponding input / output control device.

[0012]

In the read access, it is necessary to occupy the expansion bus from the time the read access request is issued until the read data is returned from the main memory, but
The write access focuses on the fact that the expansion bus can be opened immediately when a write access request is issued.

That is, at the time of a read access request from the IO controller, a read address and a device address are generated and sent to the bus adapter as a write operation via the expansion bus. This bus adapter regards this read access as a write access. The read address is temporarily stored in the request address buffer and the device address is temporarily stored in the write data buffer, and the expansion bus is immediately released.

Thereafter, the bus adapter converts what is regarded as the write access into read access to the main memory again, and sends only the read address in the request address buffer to the main memory via the basic bus to perform the read operation. None, this read data is temporarily stored in the read data buffer. Then, the bus adapter again occupies the expansion bus as a write access request and performs write access to the requesting IO control device, and sends the device address in the write data buffer and the read data in the read data buffer.

[0015]

Embodiments of the present invention will be described below with reference to the drawings.

FIG. 1 is a system block diagram of an embodiment of the present invention, and the same portions as those in FIG. 3 are designated by the same reference numerals. In the figure, a bus adapter 4 is further connected to the basic bus 3 to which the CPU 1 and the main memory 2 are connected,
The bus adapter 4 further includes a plurality of IO control devices (PC
U) 51 to 5n are connected to the expansion bus 6.

An SP request line 7 and an SP response line 8 are added in parallel with the expansion bus 6, and the SP request indicates a read access request among DMA requests from the IO control units 51 to 5n. IEEE89 which is the IO bus technology of the time
The SP request is defined by the SPLIT method (a method of receiving a response ID when sending a DMA address to release the bus and then sending the response ID and read data) specified in 6.2 etc., as the SP request. The SP response shows a response to this SP request.

Each IO control device has an IO device 102 under it, a processor (MPU) 100, and a buffer memory (BM) 101.
01 is a device address unique to the IO control device (hereinafter B
It is assumed that M address) is assigned in advance.

The bus adapter 4 is an IO control device 51-5.
It has a FIFO buffer 41 for temporarily storing an access address from n, a FIFO buffer 42 for temporarily storing write data, a FIFO buffer 43 for temporarily storing read data, and a response address register 44 described later.

At the time of read access, the IO control device
The SP request 7 is set to "1" and the BM address and the read address are sent to the expansion bus 6. Bus adapter 4 is this S
If the P request 7 is "1", it is regarded as a write access,
The BM address is stored in the write data buffer 42 and the read address is stored in the access address buffer 41, and at the same time, the expansion bus 6 is released.

Next, the bus adapter 4 fetches the read address from the access address buffer 41 and sends it to the basic bus 3 to make a read access to the main memory 2, and at the same time makes this read access to the main memory 2. , B stored in the write data buffer 42
The M address is transferred to the response register 44.

The read data by this read access is temporarily stored in the read data buffer 43 via the basic bus 3. Thereafter, the bus adapter 4 sets the SP response 8 to "1" so as to occupy the expansion bus 6, and the IO controller 5
It notifies each of 1 to 5n that it is a response to the previous SP request, and performs write access to the IO control device. In this write access, a BM address is sent from the response address register 44 and a read data is sent from the read data buffer 43 to the expansion bus 6, and the buffer memory 101 in the IO control device corresponding to this BM address.
Then, the write operation is performed to the request source IO controller, and as a result, the DMA read data is sent to the request source IO control device.

FIG. 2 is a time chart showing the operation of the system shown in FIG. 1. Similarly to FIG. 4, the upper chart shows the time chart of the expansion bus 6, and the lower chart shows the basic bus 3.
Show it. In addition, in this example, DM within the same time as FIG.
The figure shows a case where A read is executed three times and DMA write is executed twice using the free time of the expansion bus.

When the MPU 100 of the IO control unit (PCU) issues a memory read request, the SP request 7 is set to "1".
Then, the read address and the BM address of the own device are generated, output to the expansion bus 6, and the memory write is executed.

The bus adapter 4 stores the address of the expansion bus 6 in the access address buffer 41 and the BM address in the write data buffer 42, and when it detects that the SP request 7 is "1", the expansion bus 6 is immediately set. release. Then, the read access to the main memory 2 is started.

At this time, the access address buffer 41
From the read address to the main memory 2 via the basic bus 3, and transfers the BM address stored in the write data buffer 42 to the response address register 44. Although this transfer is performed via the basic bus 3 in the time chart of FIG. 2, without using the basic bus 3,
It may be directly transferred from the buffer 42 to the register 44 in the bus adapter.

When the read data is returned from the main memory 2, the bus adapter 4 reads the read data buffer 4
This read data is temporarily stored in No. 3, then the SP response 8 is set to "1" toward the expansion bus 6, and the BM address of the response address register 44 and the read data of the read data buffer 43 are used to make the IO control device. The write operation is executed with respect to.

The IO control device which has detected that the SP response 8 is "1" stores (writes) the read data in the buffer memory 101 corresponding to the BM address, and as a result, the DMA read request generated by the device itself. You can know the end of.

In the above embodiment, the example in which the bus adapter 4 is used is shown, but the main memory 2 can be considered as a kind of bus adapter. Therefore, in this case, the main memory 2 in FIG. It can be considered that all the functions of the bus adapter 4 shown in FIG.

[0030]

As described above, according to the present invention, a read operation having a long bus occupation time is converted into a write operation and processed only when the expansion bus between the IO controller and the bus adapter is used. Since this is done, the exclusive time of the expansion bus can be shortened without increasing the hardware, and as shown in FIG. 2, the expansion bus can be effectively used.

[Brief description of drawings]

FIG. 1 is a system block diagram of an embodiment of the present invention.

FIG. 2 is a time chart showing an operation example of the block of FIG.

FIG. 3 is a block diagram of a conventional memory access system.

FIG. 4 is a time cheat showing an operation example of the block of FIG.

[Explanation of symbols]

 1 CPU 2 Main Memory 3 Basic Bus 4 Bus Adapter 6 Expansion Bus 7 SP Request 8 SP Response 41 Access Address FIFO Buffer 42 Write Data FIFO Buffer 43 Read Data FIFO Buffer 44 Response Address Register

Claims (3)

[Claims] 1. An input / output device comprising: a main memory; a basic bus for transmitting an access address and access data for the main memory; an expansion bus; and a plurality of input / output control devices connected to the expansion bus. A memory access system in which a read access to the main memory from a control device is performed via the expansion bus and a basic bus, and the read access request to the main memory is provided in each of the input / output control devices. A means for generating a device address for specifying a device and sending it to the expansion bus; and a control means for temporarily storing the request address and the device address at the time of the read access request and controlling the expansion bus in a release state at the same time. The stored request address is sent to the basic bus and is transferred to the main memory. Access means for performing read access, read data storage means for temporarily storing read data by this read access, and the stored read data and the device address stored therein to the device address via the expansion bus. A memory access system comprising: a sending unit for sending to a corresponding input / output control device. 2. The control means, the access means, the read data storage means, and the transmission means are bus adapter devices connected between the basic bus and the expansion bus. The memory access system described. 3. The control means includes request address storage means for temporarily storing the read address and write data storage means for temporarily storing write data, and the device address is temporarily stored in the write data storage means. 3. The memory access system according to claim 1, wherein the memory access system is configured to have a memory.