JP3458037B2 - Split bus control method - Google Patents

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a bus control system for a computer, and more particularly to a split bus control which eliminates waste of a reply receiving buffer in a high speed system which employs a split system bus for increasing the capacity of bus transfer. It is related to the method.

[0002]

2. Description of the Related Art In split type bus control,
It is not decided when the reply to the sent command will be returned. In addition, an appropriate time is required for the command sending side unit to complete the processing for the returned reply.

Therefore, in the conventional split type bus, the same number of reply receiving buffers as the number of commands that can be sent are prepared so that all returned reply packets can be received.

However, even if a plurality of replies are returned at the same time, the internal processing of the command sending side unit is performed almost sequentially, so that there is not much time merit to receive a plurality of replies at the same time, and ， It was rare that multiple replies actually returned at the same time.

[0005]

Therefore, in a system employing a split type bus, it is disadvantageous in terms of physical quantity and has a merit in performance to have the same number of reply receiving buffers as the number of commands that can be transmitted. There was a problem that there were not many.

An object of the present invention is to control the number of reply packets to be received at the same time to reduce the capacity of the reply receiving buffer, to reduce the physical quantity, and to control so as not to impair the merits of the split bus. It is to provide a split bus control method that enables the above.

[0007]

FIG. 1 is a block diagram showing the principle of the present invention. In the figure, 1 is a first unit, 11 is a plurality of processing control units, 12 is a reply buffer management unit, 13
Is a reply buffer, 14 is a reply buffer status signal sending unit, 2 is a second unit, 21 is a transmission packet management unit, 22 is a reply holding buffer, 23 is a sending holding unit, 3 is a split bus, and 4 is a CPU. .

The first unit 1 is connected to the CPU 4 via, for example, a CPU bus. The processing control unit 11 uses, for example, a CPU for various processing such as message communication control, external register access control or memory access control.
4 is a means for transmitting a command packet to the second unit 2 via the split bus 3 in response to a request from the device 4 and requesting processing.

The reply buffer management unit 12 is means for managing the reply packet acceptance state information of the processing control unit 11 and the reply buffer 13. The reply buffer 13 is a means for receiving and storing a reply packet sent from the second unit 2. The capacity of the reply buffer 13 is a capacity for storing one reply packet, or depending on the processing content of the processing control unit 11, a capacity corresponding to a plurality of replies that can be simultaneously accepted so that no processing space is created. is there. However, the capacity of the entire processing control unit 11 is smaller than the capacity capable of storing all reply packets corresponding to the number of commands that can be transmitted during the same period.

The reply buffer status signal sending unit 14 is
It is a means for transmitting a signal (hereinafter, referred to as a reply buffer status signal) for notifying whether or not the reply packet can be accepted from the processing control unit 11 or whether or not the processing of the previously received reply packet is completed. .

The second unit 2 is a device that receives a process from the first unit 1 via the split bus 3 and returns a reply packet to the first unit 1. The transmission packet management unit 21 is the processing control unit 1 of the first unit 1.
It is a means for managing the transmission of a reply packet in response to a command from 1. The size of the reply packet is determined by the bus.
The size is 2 words and 8 words as data.

The reply holding buffer 22 is means for temporarily storing a reply packet to be returned from the second unit 2 to the first unit 1. The reply holding buffer 22 has a capacity capable of storing reply packets according to the number of requests (commands) that the second unit 2 can simultaneously accept.

The transmission holding unit 23 receives the reply buffer status signal (-R from the reply buffer status signal sending unit 14).
PLBSY) and the signal is READY (+)
If it is not, it is a control means that suspends the transmission with the reply packet stored in the reply suspension buffer 22.

The present invention operates as follows. The plurality of processing control units 11 of the first unit 1 transmit command packets requesting processing to the second unit 2 when necessary. The replies to these requests are
It is returned from the second unit 2 to the first unit 1 via the split bus 3 and stored in the reply buffer 13 common to the processing control unit 11 of the first unit 1.

The reply buffer status signal sending unit 14 is
First, the reply buffer status signal (-RPLBSY) is negated, that is, READY (+), the reply buffer 13 receives a fixed amount of reply packets, and the process control unit 11 in the first unit 1 performs the process. When there is a delay, the reply buffer status signal (-R
PLBSY) is asserted.

Transmission packet management unit 2 of the second unit 2
When the reply buffer status signal from the reply buffer status signal sending unit 14 indicates READY (+), 1 sends the next reply packet subsequently. On the other hand, when the reply buffer status signal (-RPLBSY) is asserted, the transmission holding unit 23 of the transmission packet management unit 21.
Is the reply buffer status signal (-RPLBSY)
In response, the reply packet that can be returned is temporarily stored in the reply holding buffer 22 and the reply is held.

When the processing of the processing control unit 11 in the first unit 1 is performed and the reply buffer 13 becomes ready for reception, the transmission packet management unit 21 sends the reply buffer status signal from the reply buffer status signal sending unit 14 to the reply packet status signal sending unit 14. Then, the hold of the reply packet by the transmission hold unit 23 is released, and the transmission of the reply packet is restarted.

As a result, for example, the capacity of the first unit 1 may be smaller than the capacity stored for all reply packets for the transmitted command packet, for example, one reply or the processing content of the processing control unit 11. Depending on the number of replies, the number of replies that can be received at the same time can be stored so that there is no vacancy in processing. The capacity corresponding to the number of replies for a few minutes is unnecessary. Therefore, the capacity of the reception buffer (reply buffer 13) can be reduced.

A configuration in which a plurality of second units 2 are present is also possible, and in this case, the first unit 1 sends the reply packet to the plurality of second units 2 in the ready state or the previous reception state. The second unit 2 sends a control signal notifying the completion of processing of the reply packet, and each second unit 2 sends the reply packet depending on the status of the reply packet accepting state or the status of the control signal notifying completion of processing of the previously received reply packet. First unit 1
Controls whether to immediately reply to or to suspend the reply by the transmission suspending unit 23.

Further, a configuration in which a plurality of first units 1 are present is possible, and in this case, each first unit 1
To the second unit 2 for transmitting a control signal for notifying the reply packet accepting state or the completion of processing of the previously received reply packet.

[0021]

BEST MODE FOR CARRYING OUT THE INVENTION Embodiments of the present invention will be described below with reference to the drawings. FIG. 2 is a diagram showing an example of a block configuration according to the first embodiment of the present invention. In FIG. 2, 3 is a split bus, 4 is a CPU, 5 is a memory, 6 is a system bus, 41 is a protocol control unit, 42 is a message communication control unit, 43 is an external register access control unit, 44 is a reply buffer management unit, Reference numeral 45 is a reply buffer, 46 is a reply buffer status signal sending unit, 51 is a bus connection control unit, 52 is a transmission packet management unit, 53 is a reply holding buffer, and 54 is a transmission holding unit.

In FIG. 2, the protocol control unit 41 is
This corresponds to the first unit 1 shown in FIG. 1, and the message communication control unit 42 and the external register access control unit 43 respectively correspond to the processing control unit 11 shown in FIG. The bus connection control unit 51 corresponds to the second unit 2 shown in FIG.

The message communication control unit 42 and the external register access control unit 43 in the protocol control unit 41 are connected to the bus connection control unit 51 via the split bus 3.
Further, it is connected to the system bus 6. In this embodiment, the system bus 6 is also a split type bus, and the split bus control is also performed between the bus connection control unit 51 and another unit (not shown) connected via the system bus 6. However, that part is based on the split bus control method similar to the conventional one, and in the present embodiment, the control according to the present invention is applied to the control of the split bus 3 between the protocol control unit 41 and the bus connection control unit 51. The scheme is used.

The plurality of message communication control units 42 and the external register access control unit 43 simultaneously operate the bus connection control unit 5
1 to request system bus access. When there is a system bus access request, the bus connection control unit 51 requests the system bus 6 for it. When there is a reply from the system bus 6 in response to the request, the transmission packet management unit 52 causes the reply buffer status signal transmission unit 4
The reply buffer status signal from 6 controls whether the reply packet is transmitted or temporarily held.

Reply buffer status signal is READY
In the case of (+), the transmission packet management unit 52 transmits the reply packet to the protocol control unit 41, and if the reply buffer status signal (-RPLBSY) is asserted, the transmission holding unit 54 replies from the system bus 6. Is held on the reply holding buffer 53.

The reply from the system bus 6 via the bus connection control unit 51 is received by the reply buffer 45 common to the message communication control unit 42 and the external register access control unit 43 in the protocol control unit 41. When the reply buffer 45 receives a fixed amount of reply packets and the processes of the message communication control unit 42 and the external register access control unit 43 of the protocol control unit 41 are delayed, the reply buffer management unit 44 sends a reply buffer status signal. The sending unit 46 asserts the reply buffer status signal (-RPLBSY). In this case, the transmission packet management unit 52 holds the reply in the reply holding buffer 53 by the transmission holding unit 54 as described above, even if the reply is received from the system bus 6.

Subsequently, the message communication control unit 42 of the protocol control unit 41 or the external register access control unit 4
When the process of step 3 is performed and the reply buffer 45 is in the receivable state, the transmission packet management unit 52 sees the reply buffer status signal from the reply buffer status signal sending unit 46, and cancels the hold of reply, Send a reply packet.

FIG. 3 and FIG. 4 are diagrams showing a more detailed configuration example of the system for realizing the first embodiment.
FIG. 3 shows a configuration example of the protocol control unit 41 of FIG. 2, in which the MSG control units 103 and 104 correspond to the message communication control unit 42 of FIG. 2 and the external REG control units 105 and 1
Reference numeral 06 corresponds to the external register access control unit 43 in FIG. 2, the reception buffer management unit 113 corresponds to the reply buffer management unit 44 in FIG. 2, and the reception buffer 116 corresponds to the reply buffer 45 in FIG.

The operation of the protocol control unit 41 shown in FIG. 3 will be described below. (1) In the protocol control unit 41, commands, addresses, and data related to message communication or external register access input from the CPU 4 via the CPU bus 7 are
Under the control of the reception control unit 108, the protocol conversion unit 10
After passing 1, the data is stored in the transmission buffer 109. The fact that they are received means that the MSG control units 103 and 104 and the external REG control units 105 and 106 are received through the decoder 102.
Alternatively, the other control unit 107 is notified. In response to this notification, the corresponding control unit instructs the reception control unit 108 about the position of the transmission buffer 109 that stores the command, address, and data. That is, the reception control unit 108 is notified of the storage permission and the start address of the storage location.

The protocol conversion unit 101 includes the reception control unit 1
According to the instruction 08, the received command, address, etc. are protocol-converted into a predetermined appropriate format. As the transmission buffer 109, a RAM that can independently execute Read / Write is usually used.

(2) When the reception is completed, the MSG control units 103 and 104, the external REG control units 105 and 106, and the like perform command packet transmission via the transmission internal arbiter 110, the transmission control unit 111, and the bus arbiter 112 ( ). The bus arbiter 112 is a circuit that controls the use permission GRT for the use request REQ of the split bus 3.

(3) When a reply to the transmitted command packet arrives from the split bus 3, it is notified to the reception buffer management section 113 via the decoder 114. The reception buffer management unit 113 controls the reception () of the reply packet from the bus connection control unit 51 of FIG. 4 as follows. The reply packet received is M
SG control unit 103, 104 or external REG control unit 10
When the destination is a control unit based on the control method of the present invention such as 5, 106, etc., it is temporarily stored in the common buffer of the reception buffer 116 common to these control units. In other cases, the reply packet is stored in each dedicated buffer.

(4) The destination of the reply packet is the MSG control unit 103, 104 or the external REG control unit 105, 1
If it is 06, after reception, the reception buffer management unit 113
Notifies them of the reception. MSG control unit 10
3, 104 and the external REG control units 105 and 106 perform appropriate protocol conversion for the reply via the transmission internal arbiter 117, the transmission control unit 118, and the protocol conversion unit 119, and return a response to the CPU bus 7. .

(5) When the MSG control units 103, 104 or the external REG control units 105, 106 complete the processing,
The reception buffer management unit 113 is notified of the completion of the processing, and the common buffer of the reception buffer 116 is released.

During the above processing, the reception buffer management unit 11
3 asserts the reply buffer status signal (-RPLBSY) (). Next, the operation of the bus connection control unit 51 will be described with reference to FIG. FIG. 4 shows a configuration example of the bus connection control unit 51 of FIG. 2, and the reception buffer 216 corresponds to the reply holding buffer 53 of FIG. The operation of the bus connection control unit 51 is almost the same as that of the protocol control unit 41 described in FIG. 3, but the bus connection control unit 51 does not perform protocol conversion or the like.

(1) When the command, address, and data () are input from the protocol control unit 41 via the split bus 3 to the bus connection control unit 51, the decoder 202
Through MSG control units 203, 204 or external REG
The control units 205 and 206 are notified.

MSG control units 203, 204 or external R
The EG control units 205 and 206 give instructions via the reception control unit 208, such as the storage position of the transmission buffer 209. (2) When the reception is completed, the MSG control units 203 and 204 or the external REG control units 205 and 206 perform command packet transmission to the system bus 6 shown in FIG. 2 via the transmission internal arbiter 210 and the transmission control unit 211. .

(3) On the other hand, when the bus connection control unit 51 receives a reply packet addressed to the MSG control units 203 and 204 or the external REG control units 205 and 206 via the system bus 6 of FIG. 2, the packet is received. Control unit 215
Under the control of 1), it is temporarily stored in the reception buffer 216 common to these control units.

(4) Next, the MSG control units 203 and 20
4 or the external REG control units 205 and 206 request the transmission packet management unit 52 to transmit the reply packet.
The transmission packet management unit 52 arbitrates the transmission of the MSG control units 203 and 204 or the external REG control units 205 and 206 by the transmission internal arbiter 217, and at the same time, the reply buffer status signal (-R from the protocol control unit 41).
(PLBSY) (), and if the content of the reply buffer status signal is not READY (+), the reply packet transmission is suspended. When the content indicated by the reply buffer status signal is READY (+), the transmission control unit 219 transmits the reply packet ().

FIG. 5 shows the reception buffer management unit 1 shown in FIG.
13 is a diagram for explaining the operation of FIG. 13, of which FIG.
Shows an example of input / output signals of the reception buffer management unit 113,
FIG. 5B shows an example of state transition as a state machine of the reception buffer management unit 113.

The reception buffer management section 113 has a decoder 1
14 indicating reception of a reply packet from xx. Receiving RCV and receiving from Empty (for example, MSG
0RCVing). The destination of xx is M
The SG control unit 103 represents MSG0, the MSG control unit 104 represents MSG1, the external REG control unit 105 represents ExREG0, and the external REG control unit 106 represents ExREG1 ( The same shall apply hereinafter).

When the reception is completed, xx.
RCVD is performed by the MSG control units 103, 104 or the external RE.
It is output to the G control units 105 and 106, and transits to a processing state (for example, MSG0Exc). After that, the MSG control units 103 and 104 or the external REG control units 105 and 1
When the processing of 06 is completed, the MSG control units 103 and 104
Alternatively, from the external REG control units 105 and 106, xx. Receiving CMP, transition to Empty. When the reception buffer management unit 113 is not empty, the reply buffer status signal (-PRLBSY) is asserted.

FIG. 6 is a diagram for explaining the operation of the transmission packet management unit 52, and FIG. 6A shows the transmission packet management unit 52.
6B shows an example of state transition of the transmission packet management unit 52 as a state machine.

The transmission packet management unit 52 uses the I waiting for permission.
In the DLE state, if the reply buffer state signal (-RPLBSY) from the outside is not asserted, the state transits to the transmission enable state ENABLE.

In this state, the MSG control units 203 and 204
Alternatively, when a transmission request (xx.RQ) is received from the external REG control units 205 and 206, xx. In response to ACK,
The state transits to the state during transmission (for example, MSG0Exc).
When any of the control units is in the transmitting state (xxExc), the transmission request SndREQ is output to the transmission internal arbiter 217, and the buffer address BF. ADR for each xxExc
Encode from the state of.

When receiving the transmission completion notification SndCMP from the transmission internal arbiter 217, the transmission is transited (xxExc) to the IDLE waiting IDLE. FIG. 7 is a diagram showing an example in which the present invention is applied to control of the split bus 63 between the cache control unit 62 and the memory control unit 64 as the second embodiment.

The memory control is essentially the same as the example shown in FIG. Cache control unit 6
2 is connected to the memory control unit 64 via the split bus 63. The memory control unit 64 is a device that controls access to the memory 65.

In the cache control unit 62, the CPU
Depending on the access 61, for example, registration (read access) to the cache line and copy back access of the replaced line accompanying it may occur at the same time. Also, a plurality of read requests may be suspended by the prefetch of the CPU 61.

In this case, the plurality of accesses are requested to the memory control unit 64, but their responses are controlled and returned by the reply buffer status signal (-RPLBSY). Reply buffer status signal is READ
If so, the memory control unit 64 responds with a reply. The cache control unit 62 receives a fixed amount of reply, and the cache control unit 62
Cache processing unit 62, the cache control unit 62 asserts the reply buffer status signal (-RPLBSY). In this state, the memory control unit 64 suspends the reply response. It is preferable that the number of replies that can be accepted at the same time be two or more so that no vacancy occurs in the processing in the cache control unit 62.

For example, it is possible to provide the cache control unit 62 with a plurality of receiving buffers. When the cache control unit 62 is provided with a plurality of reception buffers, as shown in FIG.
If 6'is provided as many as the number of receiving buffers, the input signals are connected in common, and among the output signals, the reply buffer status signal (-RPLBSY) is output by the AND logic 68, and the other signals are output by the OR logic 67. Good. It is also possible to provide the memory control unit 64 with a plurality of reception buffers.

FIG. 9 is a diagram showing an example in which a plurality of memory control units 64, 64 'are connected to the cache control unit 62 via a split bus 63 as a third embodiment.

The cache control unit 62 comprises means for outputting a common reply buffer status signal (-RPLBSY) to the plurality of memory control units 64, 64 '. Reply buffer status signal is READY (+)
, The memory control units 64, 64 'respond with a reply. The cache control unit 62 receives a fixed amount of reply, and the cache control unit 62
Cache processing unit 62, the cache control unit 62 asserts the reply buffer status signal (-RPLBSY). In this state, each memory control unit 6
4, 64 'hold the reply response.

Due to the bus arbitration, the cache control unit 62 has a certain memory control unit 64.
Or, even if the reply buffer status signal (-RPLBSY) is asserted immediately after receiving the reply from 64 ', the reply transmission from another memory control unit may not be stopped. R
This can be solved by, for example, asserting (PLBSY) when the reply buffer has a capacity capable of storing one reply.

FIG. 10 shows an example in which a plurality of cache control units 62 and 62 'and a plurality of memory control units 64 and 64' are provided as the fourth embodiment.

Each cache control unit 62,
The reference numeral 62 'includes means for outputting a reply buffer status signal (-RPLBSY) common to the control unit in the cache control unit for the plurality of memory control units 64, 64'. Each memory control unit 64, 64 '
When trying to send a reply, confirm that the reply buffer status signal of the destination cache control unit 62, 62 'is READY (+), and
In case of (+), reply is sent as it is, but R
If it is not EADY (+), the reply transmission is temporarily suspended, and if there is a response to another cache control unit, it is controlled to execute the processing.

[0056]

As described above, according to the present invention,
The physical quantity of the reply buffer can be reduced without degrading the performance of the split bus, and the memory can be effectively used.

[Brief description of drawings]

FIG. 1 is a principle block diagram of the present invention.

FIG. 2 is a diagram illustrating a block configuration example of the first embodiment.

FIG. 3 is a diagram illustrating a configuration example of a protocol control unit.

FIG. 4 is a diagram illustrating a configuration example of a bus connection control unit.

FIG. 5 is a diagram illustrating a reception buffer management unit.

FIG. 6 is a diagram illustrating a transmission packet management unit.

FIG. 7 is a diagram showing an example of a block configuration according to a second embodiment.

FIG. 8 is a diagram showing a configuration example when there are a plurality of reception buffer management units.

FIG. 9 is a diagram showing an example of a block configuration according to a third embodiment.

FIG. 10 is a diagram showing an example of a block configuration according to a fourth embodiment.

[Explanation of symbols]

1 first unit 2 Second unit 3 split buses 4 CPU 11 Processing control unit 12 Reply buffer management section 13 reply buffer 14 Reply buffer status signal transmitter 21 Transmission packet management unit 22 Reply hold buffer 23 Transmission holding section

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Claims (3)

(57) [Claims] 1. A bus usage right is released between a command packet transmission requesting processing and a reply packet reply for returning the processing result. As a result, a plurality of command packets are transmitted during the same period and a reply packet waiting state is set. In the split-type bus control method capable of multiplexing bus processing, the first unit that transmits a command packet via the split bus and requests processing and the second unit that accepts processing and returns a reply packet A unit exists, the first unit is provided with a reply reception buffer having a capacity smaller than a capacity necessary for receiving all reply packets for commands that can be transmitted during the same period, and the first unit accepts reply packets. The control signal notifying that the ready state or the processing completion of the reply packet received last time is notified. The second unit includes means for transmitting to the second unit, and the second unit confirms receipt of a control signal from the first unit for notifying a reply packet ready state or completion of processing of a previously received reply packet. , A split bus control system comprising means for controlling a reply packet to be returned to the first unit. 2. A bus usage right is released between a command packet transmission requesting processing and a reply packet reply for returning the processing result, and as a result, a plurality of command packets are transmitted during the same period and a reply packet waiting state is set. In the split bus control method capable of multiplexing bus processing, a first unit that transmits a command packet via the split bus and requests processing, and a plurality of first units that accept processing and return reply packets There are two units, and the first unit is provided with a reply receiving buffer having a capacity smaller than a capacity required for receiving all reply packets for commands that can be transmitted during the same period, and the first unit has a reply receiving buffer. Control signal notifying that the packet can be accepted or the processing of the previously received reply packet has been completed Is transmitted to the second unit, and each of the plurality of second units notifies the reply packet accepting state from the first unit or the completion of processing of the previously received reply packet. A split bus control system comprising means for confirming reception of the reply packet and returning a reply packet to the first unit. 3. A bus usage right is released between the transmission of a command packet requesting processing and the reply packet response for returning the processing result, and as a result, a plurality of command packets are transmitted during the same period, and a reply packet waiting state is set. In the split-type bus control method in which bus processing can be multiplexed, a plurality of first units each of which sends a command packet and requests processing via the split bus, and a reply packet which accepts the processing and returns a reply packet There are a plurality of second units, and each of the plurality of first units includes a reply reception buffer having a capacity smaller than a capacity required for receiving all reply packets for commands that can be transmitted during the same period. , Reply packet reception status of the local unit or processing of previously received reply packet The control signal for notifying completion is the second
And a control signal for notifying that each of the plurality of second units is ready to accept a reply packet from the first unit that requested processing or that processing of a previously received reply packet has been completed. A split bus control system comprising means for confirming reception of the reply packet and returning a reply packet to the first unit.