JP2000347989A - Data transfer system - Google Patents

Abstract

PROBLEM TO BE SOLVED: To improve the data transfer speed in a single mode without deteriorating the data transfer speed of a burst mode. SOLUTION: When a read access is given from a PCI(peripheral component interconnect/interface) bus 21, a PCI interface 12 decides whether the read access is single or burst read access. If a burst read access is decided, the interface 12 requests a memory interface 14 to return the read data in a synchronous transfer mode. Meanwhile, the interface 12 requests the interface 14 to return the read data in an asynchronous transfer mode in a single read access mode. In the synchronous transfer mode, the interface 12 fetches each of data from an internal bus and temporarily stores it for the clock switching and then outputs the data to the bus 21.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention is to supply data of a device operating on an internal clock to a device on the external bus in response to a request from a device on the external bus operating on an external clock different from the internal clock. Related to the data transfer method.

[0002]

2. Description of the Related Art In an information processing apparatus such as a personal computer or a workstation, a PCI (Peripheral Component Interconnect) is used.
eral Component Intercone
(ct / Interface) bus is widely used. The PCI bus can perform data transfer in a single mode in which one data is output following one address phase, and in a burst mode in which multiple data is output following one address phase. When the device connected to the PCI bus is a communication device such as a LAN controller, transmission / reception data is transferred in burst mode to / from a host device (personal computer or workstation main body), and control is performed. Information is generally transferred in a single mode.

In such a case, a device connected to the PCI bus often generates a request for burst mode access for data, and generates a single mode access request for control information. The request is accepted by a PCI interface connected to the internal bus. When the request is accepted, the data is read from a memory or the like, and the data is passed to the PCI interface via the internal bus. The PCI interface transfers data to a device in synchronization with a clock on a PCI bus.

[0004]

In a system in which control information is frequently transferred between a device connected to a PCI bus and a host device, a request for single mode access is frequently generated from the device. become. In the burst mode, many data are transferred at one time, so the effective transfer speed is high. However, in the single mode, only one data is transferred at a time. Then, in a system in which single mode access requests frequently occur, the overall information transfer speed is reduced.

Therefore, according to the present invention, in response to a request from a device on the external bus side operating on an external clock different from the internal clock, data of a device such as a memory operating on the internal clock is supplied to the device on the external bus side. It is an object of the present invention to provide a data transfer method capable of improving a data transfer rate in a single mode without reducing a data transfer rate in a burst mode.

[0006]

A data transfer method according to the present invention is connected to an external bus and an internal bus, and determines whether a request from a device connected to the external bus is a burst access or a single access. An interface means for inputting data via an internal bus by synchronous transfer for burst access and inputting data via an internal bus by asynchronous transfer for single access.

The interface means is configured to temporarily store data during synchronous transfer and output data to an external bus when final data is input, and to immediately output data input from an internal bus to an external bus during asynchronous transfer. . In addition, a signal line for handshake used for asynchronous transfer between the data generating side and the interface means and a signal line indicating synchronous / asynchronous are arranged on the internal bus.

[0008] The external bus may be a PCI bus, and the interface means may be a PCI interface. PC
The I interface is configured to determine whether to use synchronous transfer or asynchronous transfer according to the length of the ON period after the FRAME signal is turned on.

When the PCI interface decides to use synchronous transfer, the state of the signal line indicating synchronous / asynchronous is set to the synchronous state, and the data generating side synchronizes with the internal clock according to the state of the signal. Then, it is determined whether to output data to the internal bus or to output data to the internal bus using a signal line for handshaking.

[0010]

Embodiments of the present invention will be described below with reference to the drawings. FIG. 1 is a block diagram showing a configuration of a memory controller which is an example of a system to which a data transfer method according to the present invention is applied. A memory controller 1 shown in FIG. 1 includes a processor interface 11 for exchanging information with a processor 2, a memory interface 14 for inputting and outputting data to and from a memory 3, a PC
A PCI interface 12 for inputting / outputting data in response to a request from a device connected to the I bus 21;
The DMA interface 13 that performs DMA transfer of data in response to a request from a device connected to the MA bus 22
It is a configuration connected by an internal bus.

An arbiter 15 for arbitrating requests from the processor 2, the PCI bus 21 and the DMA bus 22 and transferring the requests to the memory interface 14 is also provided. In the internal bus shown in FIG. 1, a solid line indicates a command / write data bus, and a broken line indicates a read data bus.

FIG. 2 is a timing chart showing how synchronous transfer is performed on the internal bus in response to a burst transfer request from the PCI bus 21. FIG. 3 shows the PCI bus 2
FIG. 3 is a timing chart showing a state in which asynchronous transfer is performed on an internal bus in response to a burst transfer request from the first bus.
FIG. 4 is an explanatory diagram showing the function of each signal shown in FIG. 2 and FIG. As shown in FIGS. 2 and 3, the internal bus clock (CLK) and the PCI bus clock (PCICL)
The frequency of K) is different.

The devices connected to the PCI bus 21 are:
When requesting data from the memory 3, an address designating the PCI interface 12 is output to a PCI bus multiplex address / data (PCIAD) line, and F
RAME (cycle start signal) falls. afterwards,
IRDY (initiator ready signal) falls.

When the PCI interface 12 recognizes the request, it lowers DEVSEL (address response signal). Then, the process enters a phase of reading data from the memory 3 via the internal bus.

In the synchronous transfer shown in FIG. 2, data from the memory 3 is output to the internal bus as DATA (internal bus data) in synchronization with the internal clock. The PCI interface 12 takes in data on the internal bus. Then, TRDY (target ready signal) on the PCI bus falls, and data is output to the PCIAD line in synchronization with PCICLK. In FIG. 2, a period between two broken lines indicates a period during which synchronous transfer is performed.

In this embodiment, SYNC (return data synchronous transfer request signal) indicating synchronous transfer or asynchronous transfer and DTACK (handshake signal during asynchronous transfer) are added to the internal bus. I have. At the time of synchronous transfer,
As shown in FIG. 2, SYNC is activated (low level) at the start of data transfer on the internal bus.

In the asynchronous transfer shown in FIG. 3, the memory interface 14 outputs DT when internal bus data is output.
S (internal bus data valid signal) is activated (low level). PCI interface 12 that detected it
Fetches data on the internal bus and causes DTACK to fall. Then, TRDY on the PCI bus is lowered, and the data fetched from the internal bus is transferred to the PCI bus.
Output to the PCIAD line in synchronization with CLK. In addition,
When detecting that DTACK has fallen, the memory interface 14 raises DTS. In FIG. 3, a broken line indicates a section in which asynchronous transfer is performed.

As described above, in asynchronous transfer, DTS and D
The PC is transferred from the memory 3 by the handshake of TACK.
Data is transferred to the I interface 12. And
The PCI interface 12 immediately (through) the data fetched from the internal bus to the PCI bus 21. That is, in the synchronous transfer, the PCI interface 12
Temporarily accumulates the data fetched in synchronization with the internal bus clock, and stores those data in synchronization with PCICLK.
The clock transfer for outputting to the CI bus 21 is performed. In the asynchronous transfer, the clock transfer is performed on the internal bus.

FIG. 5 is a timing chart showing how synchronous transfer is performed in response to a single transfer request from the PCI bus 21. FIG. 6 is a timing chart showing how asynchronous transfer is performed in response to a single transfer request from the PCI bus 21. In the synchronous transfer shown in FIG. 5, the PCI interface 12 temporarily accumulates the data taken in synchronization with the internal bus clock, and
In synchronization with the PCI bus 21. In the asynchronous transfer shown in FIG. 6, the data fetched from the internal bus is transmitted to the PCI bus 21 through.

When a request is issued from the PCI bus 21,
If the request is a write access to the memory 3, the PC
When the I interface 12 receives the write command and the write data, the PCI bus 21 can be released. However, in the case of a read access, the PCI bus 21 remains occupied from when the request is generated until the read data is returned from the memory 3. Therefore, as a method of returning the read data as soon as possible, in this embodiment, synchronous transfer and asynchronous transfer are dynamically switched.

Comparing the timing charts of FIGS. 2 and 3, in the case of burst transfer, the synchronous transfer shown in FIG. It can be seen that the read data can be returned to the PCI bus 21 quickly. 2 and 3
In the example shown in (1), one burst is composed of four words, but if the number of transfer data in one burst is increased, the difference is further increased.

Comparing the timing diagrams of FIGS. 5 and 6, it can be seen that in the case of a single transfer, the asynchronous transfer shown in FIG. 6 can return read data to the PCI bus 21 earlier. 2, 3, 5 and 6
Indicates that the cutting line by the curve is omitted on the way. Therefore, although the clock number given to PCICLK is a continuous number, strictly speaking, it is a discontinuous number on both sides of the cutting line.

From the above, in this embodiment, P
When there is a read access from the PCI bus 21, the CI interface 12 is configured to determine whether the access is a single read access or a burst read access. Then, it is configured to request the memory interface 14 to return read data by synchronous transfer at the time of burst read access, and to request the memory interface 14 to return read data by asynchronous transfer at the time of single read access.

Hereinafter, the operation of the PCI interface 12 will be described in more detail with reference to FIGS. PC
When a device connected to the I bus 21 requests data from the memory 3, the device outputs an address designating the PCI interface 12 to the PCIAD line, and
The RAME signal falls. After that, IRDY falls. At this time, the device keeps the FRAME signal low for 2 PCICLKs or more in burst read access, and keeps the FRAME signal low for 1 PCICLK (address phase period) in single read access. Therefore, the PCI interface 12
Is determined to be a single read access when the FRAME signal is output for only one PCICLK clock, and is determined to be a burst read access when the FRAME signal is output for two or more clocks.

As shown in FIGS. 2 and 6, when the PCI interface 12 recognizes the request, the DEVSEL
(Address response signal) falls. Then, the process enters a phase of reading data from the memory 3 via the internal bus.
At this time, in the case of burst read access, data is taken in from the internal bus by synchronous transfer as shown in FIG.

In the synchronous transfer shown in FIG. 2, the PCI interface 12 first outputs the corresponding address of the memory 3 to AD (internal bus address), and makes ADS (internal bus address valid signal) active (low level). .
At this time, R / W (read / write signal) is set to a high level indicating read. Also, memory interface 1
SYNC is activated (low level) in order to request synchronous transfer to No. 4. When another interface is using the internal bus, the arbiter 15 waits for the internal bus access of the PCI interface 12.

When detecting the address of the AD, the memory interface 14 determines whether the synchronous transfer is requested by the SYNC or the asynchronous transfer is requested. In this case, since synchronous transfer has been requested, data is read out from the memory 3 for a predetermined number of transfers and CL
The data (DATA) is output to the internal bus in synchronization with K. Also, DTS (internal bus data valid signal) is set to low level. Also, EOD (final data display signal) is activated (low level) for the final data.

The PCI interface 12 fetches each data from the internal bus and temporarily stores the data for changing the clock. When the EOD is detected, the PCI bus 2
In step 1, TRDY is set to low level, and PCICL
Data is output to the PCIAD line in synchronization with K. When all data output is completed, TRDY is set to high level.

When detecting that the request from the PCI bus 21 is a single read access, the PCI interface 12 fetches data from the internal bus by asynchronous transfer as shown in FIG. In the asynchronous transfer shown in FIG.
The PCI interface 12 first outputs the corresponding address of the memory 3 to AD, and activates ADS. At this time, R / W is set to a high level indicating a read. In order to request the memory interface 14 for asynchronous transfer, SYNC is kept inactive (high level).

When detecting the address of the AD, the memory interface 14 determines whether the synchronous transfer is requested by the SYNC or the asynchronous transfer is requested. In this case, since asynchronous transfer is requested,
Only one word of data is read from the memory 3 and data (DATA) is output to the internal bus. At the same time, DTS is activated.

When the PCI interface 12 detects that DTS has gone low, it takes in data from the internal bus. Then, DTACK is activated. Also, the data fetched from the internal bus is
Output to the line and set TRDY to low level. In addition,
When detecting that DTACK has gone low, the memory interface 14 raises DTS. When detecting that the DTS has become high level, the PCI interface 12 raises DTACK.

As described above, in this embodiment, the PC
The I interface 12 determines whether the request from the PCI bus is a burst read access or a single read access, and if the request is a burst read access, inputs data by synchronous transfer from the internal bus and switches clocks. Data to the PCI bus 21.
In the case of single read access, data is input from the internal bus by asynchronous transfer, the clock is switched on the internal bus, and the data is transmitted to the PCI bus 21 through. That is, the internal bus transfer method is dynamically switched according to the burst read access and the single read access.

Therefore, the speed of single read access can be improved without lowering the data transfer speed in burst read access. Since only two signals (SYNC and DTACK) are added to the conventional system to realize such a data transfer system, there is no inconvenience that the system cannot be wired and the present system cannot be realized.

If the internal bus data transfer system is fixed to the synchronous system in order to give priority to the speed of burst read access, the speed of single read access cannot be increased. In such a case, in a system in which single read access frequently occurs, the overall data transfer speed is reduced. Further, if the internal bus data transfer method is fixed to the asynchronous method in order to give priority to the speed of frequent single read access, the speed of burst read access is reduced. However, according to the present method, such a problem does not occur.

In the above embodiment, P is used as the external bus.
Although the CI bus 21 is taken as an example, this system is a PCI bus 21
The present invention can be applied to any system in which the internal bus clock and the external bus clock are independent, without being limited to the system using. When it is necessary to save a buffer for temporarily storing data in the clock transfer part (the PCI interface 12 in the above example), asynchronous transfer as shown in FIG. 3 may be used at the time of burst transfer. .

[0036]

According to the present invention, the data transfer method is determined whether a request from a device connected to an external bus is a burst access or a single access,
For burst access, data is input via the internal bus by synchronous transfer. For single access, data is input via the internal bus by asynchronous transfer. There is an effect that the data transfer speed in the single mode can be improved without lowering the speed.

[Brief description of the drawings]

FIG. 1 is a block diagram illustrating a configuration of a memory controller.

FIG. 2 is a timing chart showing how synchronous transfer is performed in response to a burst transfer request.

FIG. 3 is a timing chart showing how asynchronous transfer is performed in response to a burst transfer request.

FIG. 4 is an explanatory diagram showing the function of each signal shown in FIGS. 2 and 3;

FIG. 5 is a timing chart showing how synchronous transfer is performed in response to a single transfer request.

FIG. 6 is a timing chart showing how asynchronous transfer is performed in response to a single transfer request.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 Memory system 2 Processor 3 Memory 11 Processor interface 12 PCI interface 13 DMA interface 14 Memory interface 15 Arbiter 21 PCI bus 22 DMA bus

 ──────────────────────────────────────────────────続 き Continuing on the front page (72) Inventor Masaharu Ejiri 5-7-1 Shiba, Minato-ku, Tokyo NEC Corporation F-term (reference) 5B060 CC03 CC05 5B061 DD05 DD06 DD09 DD11 FF04 GG06 RR03 5B077 AA23 AA24 BA08 BB05 BB06 FF12 MM02 5K034 AA01 CC01 DD01 FF01 FF12 GG02 HH01 HH06 HH63 KK12 PP01 PP03

Claims (6)

[Claims] 1. A clock related to an internal bus and a clock related to an external bus are independent, data is input via the internal bus in response to a request from a device connected to the external bus, and the input data is connected to the external bus. In a data transfer method for supplying data to a specified device, the device is connected to an external bus and an internal bus, and determines whether a request from the device is a burst access or a single access. A data transfer method comprising: interface means for inputting data via an internal bus through asynchronous data transfer for single access. 2. An interface means for temporarily storing data during synchronous transfer and outputting data to an external bus when final data is input, and immediately outputting data input from an internal bus to an external bus during asynchronous transfer. Data transfer method described. 3. The data bus according to claim 2, wherein a signal line for handshake used for asynchronous transfer between the data generating side and the interface means and a signal line indicating synchronous / asynchronous are arranged on the internal bus. Transfer method. 4. The data transfer method according to claim 3, wherein the external bus is a PCI bus, and the interface means is a PCI interface. 5. The data transfer method according to claim 4, wherein the PCI interface determines whether to use synchronous transfer or asynchronous transfer according to the length of the ON period after the FRAME signal is turned on. 6. The PCI interface sets the state of a signal line indicating synchronous / asynchronous to a synchronous state when it is decided to use synchronous transfer, and the data generating side synchronizes with an internal clock according to the state of the signal. 6. The data transfer method according to claim 5, wherein whether to output the data to the internal bus or to output the data to the internal bus using a signal line for handshaking is determined.