JP2003122701A - Interface and input/output device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To avoid segmentation of burst transfer even when write access and read access are mixed to an I/O device connected with a transfer type bus. SOLUTION: Write data is transmitted following a command indicating a write request in the case of the write access from a CPU 102 to an I/O device 100 and a command indicating a read request is transmitted to a group 105 of write registers as data strings by the burst transfer in the case of the read access. When a write detecting circuit 107 detects the write command, a data transfer circuit 109 takes out the write data following it from the group 105 of registers, writes it to an I/O functional part 104, when it detects the read command, reads the applicable data from the I/O functional part and stores it in a group 106 of read registers. After that, the CPU reads the data corresponding to the read command from the group 106 of registers by the burst transfer.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an interface and an input / output device (hereinafter referred to as an I / O device), and particularly to an I / O device connected to a transfer type bus represented by a PCI bus. The present invention relates to an interface for accelerating random access in which leads are mixed and an I / O device including the interface.

[0002]

2. Description of the Related Art In recent years, processor systems that utilize high-speed I / O devices such as graphic accelerators employ transfer-type buses such as a PCI bus to enable higher-speed burst transfer. However, a conventional I / O device generally has a configuration in which a command register group mapped to a specific address is provided for each function, and in such a configuration, writing of a series of command groups becomes a discontinuous address, There was a problem that burst transfer could not be applied.

As a technique for dealing with this problem, Japanese Unexamined Patent Publication No. 20
No. 00-137674. In this conventional technique, a continuous area on the PCI bus memory space is
SIMD (Single
It shows a method of writing a command or data set in the form of Instruntion Multiple Data) into the register group by burst transfer.

Generally, when accessing an I / O device from a CPU, a high-speed buffer is provided in the I / O device or the bus bridge for write access, and C
By writing the data to be written from the PU to this buffer, the CPU is released regardless of the speed difference between the CPU and the I / O device, and the next process can be started. However, in the case of read access, I
Since the / O device operates slower, the CPU must wait until the corresponding data becomes readable after the read command is issued from the CPU. As a solution to this problem, in Japanese Patent Laid-Open No. 7-210454, a controller for controlling memory access is provided with a read-ahead control circuit and a read-only buffer, and the read data is actually needed when the memory is read-accessed. The CPU issues a read-ahead command earlier than the command step, and the read-ahead control circuit reads the corresponding data from the memory and stores it in the read-only buffer. And CPU
Discloses a technique for speeding up read access by issuing a read command again when the relevant data is actually fetched and fetching the relevant data if it is in the read-only buffer. However, this technique does not assume continuous data transfer like a transfer type bus typified by a PCI bus, but accesses via a random type bus in which a gap occurs between data access. It was handled.

[0005]

DISCLOSURE OF THE INVENTION Problems to be Solved by the Invention
The conventional technique disclosed in Japanese Patent No. 674 is effective when all accesses from the processor to the I / O device are in the write direction, but when read access is performed, the commands and data included in the SIMD format are used. When burst transfer is divided between columns and read access and write access are mixed, there is a problem that burst transfer is further divided at the switching portion. According to the technique disclosed in Japanese Patent Laid-Open No. 7-210454, the read access cycle can be realized in a short time by the read-ahead control of read access. However, this technique cannot effectively use the burst transfer function in the burst transfer mode by the transfer type bus even if it is directly applied to the access sequence in which the read access is mixed.

An object of the present invention is, in a transfer type bus, even when a read access and a write access are mixed, or an access sequence in which addresses are discontinuous, at a write / read switching time or an address discontinuity portion. An object of the present invention is to provide an interface and an I / O device that can effectively use the burst transfer function by eliminating division of burst transfer that occurs.

[0007]

The present invention is an interface for controlling information exchange between a transfer type bus and an input / output device function section, and controls information transmission / reception with the transfer type bus. A transmission / reception control unit, a first register group capable of burst writing from the transfer type bus via the transmission / reception control unit, and a second register group capable of burst reading from the transfer type bus via the transmission / reception control unit. And when the first register group stores data indicating a write command for the input / output device function unit and subsequent write data, or data indicating a read command for the input / output device function unit, a write command or a read command And a command detecting means for detecting a write command when a write command is detected by this command detecting means. After the write command, the write data stored in the first register group is written to the address of the input / output device functional unit designated by the write command, and when the read command is detected by the command detecting means, Disclosed is an interface characterized by including data passing means for reading data from an address of the input / output device function unit designated by the read command and sequentially storing the data in the second register group.

Further, according to the present invention, the processing progress status of the data transfer means corresponding to the read command or the write command is monitored, and the status information can be read from the transfer type bus via the transmission / reception control means. Disclosed is an interface including an acquisition unit.

Further, according to the present invention, when the total number of bits of the write command and the write data corresponding thereto is less than the bit width of the transfer type bus and is input as one data, the data passing means is Disclosed is an interface having a function of extracting write data from the data and writing the write data to an input / output device function unit.

Further, the present invention discloses an input / output device having the above-mentioned interface.

[0011]

BEST MODE FOR CARRYING OUT THE INVENTION Embodiments of the present invention will be described below.
The CI bus will be described in detail with reference to the drawings. Figure 1
Is an I / O equipped with a bus interface according to the present invention.
In the block diagram showing the configuration example of the device, an I / O device 100 includes a processor 102 via a PCI bus 101.
It is configured to connect with. I / O device 100
Is a PCI bus interface 103, an I / O function unit 104 that provides main functions of an I / O device, and a PC.
PCI bus 10 via I-bus interface 103
Write register group 105 capable of burst writing from 1
And PCI via PCI bus interface 103
A read register group 106 capable of burst reading from the bus 101, a status register 111 capable of being read from the PCI bus 101 via the PCI bus interface 103, and a write from the PCI bus 101 to the write register group 105 are detected and written. In response to the write detection circuit 107 that generates the data number information 108 and the data number information 108 obtained from the write detection circuit, all access commands or write data written in the write register 105 are sequentially processed from the beginning, It is configured by a data transfer circuit 109 that transfers data to and from the O function unit 104, and a transfer monitoring circuit 113 that monitors the processing status of the data transfer circuit 109 and writes the processing progress information 112 to the status register 111. In the I / O device 100, the PCI interface 103 and the I / O function unit 104 are the same as the conventional ones, and therefore the description thereof is omitted.

The data transfer circuit 109 decodes the access command read from the write register group 105, and if the access command requests data write, it reads the data read from the area next to the write register group 105. , As write data to the I / O function unit 104. If the result of decoding the access command is a request for data read, the data is read from the I / O function unit 104 according to the request of the access command and stored in the read register group 106. Note that the data is stored in the read register group 106 in order from the top area.

The transfer monitoring circuit 113 monitors the operation of the data transfer circuit 109, generates the data transfer process progress information 112 to the I / O function unit 104 which is sequentially executed in response to the access command, and the status register 111. Write in. By reading the contents of the status register 111 via the PCI interface 103, the processor 102 can know the processing progress status of the data transfer requested by the access command.
As a result, the processor 102 can make a read access to the read register group 106 after confirming the end of data storage in the read register group 106 from the data transfer circuit 109, so that the access waiting state of the processor 102 can be avoided. You can

As an access command to write to the write register group 105, in addition to the data transfer request,
A processing request for the I / O function unit 104 may be included.
In this case, the access command may not be accompanied by the data transfer unless it is particularly necessary. Further, one access command may instruct a plurality of data accesses. In this case, for example, when the access command requests n data writes, n write data is written to the write register group 105 following the access command, and the data transfer circuit 1
09 reads out n pieces of data from the write register group 105 and performs a transfer process to the I / O function unit 104. When the access command requests to read n pieces of data, the data transfer circuit 109 receives n pieces of data from the I / O function unit 104 and stores them in the read register group 106.

If the total number of required bits of the access command and the write data is less than or equal to the bus bit width of the PCI bus 101, the write data may be included in the access command. In such cases, PC
The number of write accesses to the I bus 101 is reduced, and the access time can be shortened accordingly.

In a system having a configuration in which a host bus directly connected to a processor is connected to a PCI bus via a bridge, burst read may be possible only from a memory device directly connected to the host bus or bridge. . In such a system, a bus master function is provided in the PCI interface in the I / O device,
The I / O device itself serves as a master of the PCI bus to transfer the read data stored in the read register group to the memory device, so that the processor can burst-read the read data via the memory device.

The operation will be described below. FIG. 2 shows an example of access timing when write access and read access are alternately performed to a conventional I / O device via the PCI bus. On the PCI bus, the access destination address and data are sent using the same data line A / D, first the access destination address and then the data (generally in burst mode). The bus addresses of the four access target registers are A1 to A4 (A1 and A3 are write addresses, A2 and A4 are read addresses), and the access data to each register are shown by D1 to D4. In AP, the data phase is shown in DP, and the weight phase is shown in WP. In addition /
FRAME signal, C / BE signal, / IRDY signal, / T
The RDY signal is a signal conforming to the PCI bus shown for ease of understanding, and its operation is as defined by PCISIG. Therefore, its explanation is omitted here.

In the example of FIG. 2, since write access and read access are mixed, burst transfer is not established, and there is an address phase and a data phase for each access. Also, especially addresses A2 and A4
In the case of a read access to a register that has, there is a case where the data preparation period of the I / O device is necessary,
Here, the wait phase of 1 clock width is shown only for read access. Further, in general, in the access by the PCI bus, a blank period is inserted between the accesses, so that a blank period of one clock width is provided in the figure. This blank period is for avoiding a bus collision that occurs at the moment of switching between writing and reading.
A clock width is sufficient, but in a processor system with a standard configuration in which a processor is directly connected to a PCI bus via a bridge from a host bus, due to the latency of the bridge that occurs during synchronization processing between buses, Actually, it often takes several tens of clocks.

FIG. 3 shows an example of access timing when the same access as in FIG. 2 is performed on the I / O device of the present invention. The head address of the write register group 105 is AW, the head address of the read register group 106 is AR, and the access command data of each access cycle is DC1 to DC4 (DC1 and DC3 are write commands,
DC2 and DC4 are read commands, and the transfer data of each access cycle is shown by DD1 to DD4. As in the example of FIG. 2, the / FRAME signal, the C / BE signal,
The description of the / IRDY signal and the / TRDY signal will be omitted. In the example of FIG. 3, first, the write register group 10
After outputting the start address AW of No. 5 to the A / D bus, access command data DC1 to DC4 and write data D
D1 and DD3 are output as burst transfer data. This is because burst access is possible because write access may be made to a continuous area of the write register group 105. This write register group 10
After the access to 5 is completed, the read register group 106
Similarly, the data read from is performed by burst transfer. In the example of FIG. 2, the wait phase is inserted at the time of reading, but in the example of FIG. 3, there is a time interval between the issuance of the access command and the data reading. Therefore, during this period, the data set to the read register group 106 has already been completed. Therefore, no weight face is needed.

When an I / O device, which is much slower than the operation of the PCI bus, is targeted for access, it is meaningful to be able to separate access command issue and data read in this way. In the example of FIG. 2, unless the I / O device itself has the function of disconnecting the connection, the processor waits until the data preparation of the I / O device is completed, but in the example of FIG. By delaying the access to the read register group 106 according to the response speed of the / O device and accessing the read register group 106 after the read data is prepared, the wait phase of the processor 102 becomes unnecessary. Further, when such a method is adopted, by referring to the status register in which the processing progress information of the data transfer circuit 109 is stored, it is ensured that the data preparation is completed before the read register is accessed. May be.

[0021]

According to the present invention, even when read access is mixed with access to the I / O device connected to the transfer type bus, burst transfer can be effectively used to realize high-speed access processing. There is.

[Brief description of drawings]

FIG. 1 is a block diagram showing a configuration example of an I / O device provided with an interface of the present invention.

FIG. 2 is an example of access timing of a transfer type bus according to a conventional method.

FIG. 3 is an example of access timing of a transfer type bus according to the interface of the present invention.

[Explanation of symbols]

100 I / O device 101 PCI bus 102 processors 103 PCI bus interface 104 I / O function section 105 write register group 106 read register group 107 light detection circuit 108 Number of data information 109 data transfer circuit 111 Status register 112 Processing progress information 113 Delivery monitoring circuit

Continued front page    (72) Inventor Katsuyuki Kumasaka             3-1-1 Sachimachi, Hitachi City, Ibaraki Prefecture Stock Association             Hitachi, Ltd., Hitachi Works F-term (reference) 5B014 GC14 GD14                 5B061 AA00 DD06 FF06 RR02 RR03

Claims (4)

[Claims] 1. An interface for controlling information exchange between a transfer type bus and an input / output device function unit, and a transmission / reception control means for controlling information transmission / reception with the transfer type bus; A first register group capable of burst writing from the bus via the transmission / reception control means, a second register group capable of burst reading from the transfer type bus via the transmission / reception control means, and a first register group A command detection unit that detects a write command or a read command when data indicating a write command for the input / output device function unit and subsequent write data or data indicating a read command for the input / output device function unit is stored, When a write command is detected by this command detection means, And write the write data stored in the first register group to the address of the input / output device function section designated by the write command, and when the read command is detected by the command detection means, the write data is specified by the read command. An interface for reading data from the address of the input / output device function unit and sequentially storing the data in the second register group. 2. A status acquisition means capable of monitoring the processing progress status of the data transfer means corresponding to the read command or the write command and reading the status information from the transfer type bus via the transmission / reception control means. The interface of claim 1, wherein the interface is provided. 3. When the total number of bits of the write command and the write data corresponding to the write command is less than the bit width of the transfer type bus and the data is input as one data, the data passing means outputs the data from the data. The interface according to claim 1, having a function of extracting write data and writing the write data to an input / output device function unit. 4. An input / output device comprising the interface according to claim 1. Description: