JPH06149725A - Processor applied device - Google Patents

Abstract

PURPOSE:To provide a system which performs another process by a CPU during DMA(direct memory access) transfer as to a system which enables the DMA transfer by using a CPU for the center of control. CONSTITUTION:The address space of a memory is divided into at least two and the device is provided with switching means 407 and 408 which performs separation/coupling control over a DMA transfer processing system 402 and processing systems 401 and 403 by CPUs; and the processing systems by the CPUs are provided with one of the divided address spaces of the memory and the DMA transfer processing system is provided with the other. They are usable as communication buffer memories, the DMA transfer processing system and processing system by the CPUs are separated by the switching means at the time of the DMA transfer, and the processing system by the CPUs can be put in operation during the DMA transfer processing.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a processor application apparatus having a DMA controller for directly transferring data between the outside and a memory and a peripheral circuit for generating an interrupt to a CPU.

[0002]

2. Description of the Related Art In a computer system, direct memory access (hereinafter referred to as DMA) is generally used as a technique for performing high-speed data transfer between an external memory and a system internal memory. This technology is C
The data can be transferred between the outside and the memory by directly controlling the read / write of the memory without interposing the PU, so that the data transfer speed can be realized close to the operation speed of the memory. It is very advantageous for sending and receiving continuous data.

This DMA controls the address of the memory to be accessed and the read / write control independently of the CPU.
In a computer system having a MA controller and a peripheral circuit for generating an interrupt to a CPU,
After setting the read start address or write start address and the number of bytes to be accessed in the DMA controller and disconnecting the CPU from the system bus,
When the controller is started, in the read mode, the memory is read from the above start address in the order of the number of bytes and is read out and sent to the data bus in the system bus.In the write mode, the read operation starts from the above start address. It is said that the data on the data bus in the system bus is fetched and written while the memory is accessed by the number of bytes in the order of addresses.

An example of a conventional communication system using DMA is shown in FIG. In FIG. 5, 41 is a CPU
42 is a DMA (direct memory access) controller, 43 and 44 are interface LSIs respectively, 45 is a memory, and 46 is a data bus to which these are connected. Further, 51 and 52 are serial communication paths having different transmission rates, and the communication system of FIG.
52 shows a system for exchanging data with 52 in real time.

The CPU uses, for example, a microprocessor to execute a program to perform arithmetic operations and various controls, and also performs address control of the memory necessary for program execution and data input / output operations. .

The communication path 51 is an interface LSI 4
3, the communication path 52 is an interface LSI
Connected to 44. Interface LSI 43
Reference numerals 44 and 44 denote LSIs for data communication between the inside and the outside respectively. In the reception mode, serial data is received, converted into parallel data and output, and in the transmission mode, parallel data to be transmitted is converted into serial data. In the reception mode, the reception data from the corresponding communication path of the communication paths 51 and 52, which are serial communication paths, is taken in and is placed on the data bus 46, which is a parallel bus. In the transmission mode, the parallel data on the data bus 46 is fetched and output to the corresponding communication path in the transmission mode.

Further, it is assumed that the communication path 51 is a low-speed transmission path that can be sufficiently made even by the data operation processing by the CPU 41, and the communication path 52 is a high-speed transmission that cannot be made by the data operation processing through the CPU 41. If the data is received from the communication path 51, the interface LSI 43 connected to the low-speed communication path 51 receives C from the communication path 51.
An interrupt request is issued to the PU 41, and the CPU 41
To receive this received data, and
Under the control of 41, the data on the data bus 46 can be fetched and the fetched data can be transmitted to the communication path 51.

The interface LSI 44 connected to the high-speed communication path 52 transfers data between the communication path 52 and the data bus 46 under the control of the DMA controller 42, and the memory 45 is a CPU 41. Alternatively, read / write access is performed under the control of the DMA controller 42, and data can be exchanged with the data bus 46. The memory 45 stores various programs executed by the CPU 41, and is also used as a data area, a work area of the CPU 41 for executing a program, a buffer memory for data transmission, and the like.

The DMA controller 42 has a memory 45 of C
This is a controller for directly performing the read / write control of the memory 45 without the intervention of the PU 41. When performing the DMA control, the CPU 41 is stopped and the read / write control and the address control are performed. Now, let us consider a process when data is received from one communication path 51 and transmitted to the other communication path 52.

The arrival of data received from the communication path 51 depends on the state of the partner device on the transmission side facing the interface LSI 43 via the communication path 51.
At this time, when data arrives continuously, the time interval, that is, the minimum value of the period is T.

As a processing method of the CPU 41 for receiving data under such conditions, an interrupt request from the interface LSI 43 is accepted, and a buffer memory (memory 45 in this example) is received each time data arrives. (Provided above) is generally used. Also, the instructions to be executed by the CPU 41 are usually in the memory 45.
It is stored in, and in order for the CPU 41 to operate,
Access to the memory 45 is required.

On the other hand, regarding the data transfer to the high speed communication path 52, it is ideal that the DMA controller 42 performs the DMA transfer between the memory 45 and the interface LSI 44 if the transfer rate is relatively higher than that of the communication path 51. However, the received data from the communication path 51 interrupts the CPU 41 each time it is fetched by the interface LSI 43, and the fetched data is temporarily stored in the buffer memory area of the memory 45 by the CPU 41. Since the data stored in the area is sent to the interface LSI 44 and sent to the communication path 52, when receiving the reception data from the communication path 51 in real time, the interrupt processing from the interface LSI 43 accompanying the reception data acquisition And input associated with this interrupt processing Considering that processing is required in CPU41 that said that the process of storing such the buffer memory over data, DMA transfers to force the stop of the CPU practical, had become difficult.

[0013]

In a system in which a CPU is used as a control center and data is transferred between two communication paths having different transmission speeds, when the data transfer needs to be performed in real time, If the transmission speed is low, an interface for exchanging data with the communication path is used under the control of the CPU, an interface for temporarily storing the data in the buffer memory, reading it, and exchanging data with the communication path on the transmission side. This read data may be sent out via the C, but if the transmission line is high speed, C
It would not be in time if it was transferred under the control of the PU.

When high speed transmission is required, D is generally used.
The MA transfer is performed, but this puts the CPU in the stopped state and D
Since the MA controller carries out read / write control and address control, when it is necessary to perform real-time reception when the receiving side has a low speed, CP
It's hard to stop U.

That is, in order to perform data transfer in real time, since an input / output interface which requires control of the CPU is used, it is necessary to perform a response process to an interrupt accompanying the data transfer of this interface. The DMA transfer that forces the CPU to stop is effectively
It is not available, and therefore DM is used for data transfer between the buffer memory and the input / output interface of the high-speed side communication path
There is a problem that A cannot be used, and there is a problem that the system design is greatly restricted.

Therefore, the object of the present invention is to
It is an object of the present invention to provide a processor application device capable of realizing a system capable of simultaneously processing other processes such as data reception from a communication path during high-speed DMA transfer with the communication path.

[0017]

In order to achieve the above object, the present invention is configured as follows. That is, in a system in which a memory, a processor, and direct memory access means are connected via a bus, the memory is directly accessed by the direct memory access means instead of the memory access control by the processor. In a processor application system capable of transferring data between a bus and the outside, in order to separate / couple control of a direct memory access transfer processing system by a direct memory access means and a processing system by a processor, Is provided with a switching means for switching control, and the address space of the processor is divided so that one is allocated to the processing system of the processor and the other is allocated to the direct memory access transfer processing system to arrange the memory, and Direct memory access The configure to have a separated controlled to processing functions to the switching means at the time of the scan transfer.

[0018]

In the above structure, the direct memory access (DMA) transfer processing system and the processing system by the processor (CPU) are provided with switching means for switching control of the bus in order to separate / couple the processing system. At the time of transfer processing, the CPU controls the switching means to separate the processing systems. Therefore, the DMA transfer processing system and the CPU processing system are separated as hardware, and the CPU processing system can continue its own operation independently of the DMA transfer processing.

As described above, according to the present invention, the address space of the memory is divided into at least two, and the switching means for separating / combining the DMA transfer processing system and the processing system by the CPU is provided and the division is performed. One of the memory address spaces is provided to the processing system by the CPU, and the other is provided to the DMA transfer processing system so that they can be used as buffer memories for communication, and the DMA transfer processing system by the switching means at the time of DMA transfer. And the processing system by the CPU are separated so that the processing system by the CPU can operate during the DMA transfer processing.
The processing by the CPU can be continued during the MA transfer processing.

[0020]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention will be described below with reference to the drawings. Here, an example applied to an exchange is shown in a block diagram in FIG.

In FIG. 1, reference numeral 1 is an exchange main body (PB).
X), 2a to 2n are port processors, 4a, and
4b is a remote shelf. The port processors 2a to 2n are for interfacing with real terminals (for example, telephone terminals, facsimile terminals, office lines), and are usually housed in the exchange main body 1.

The remote shelves 4a and 4b are interfaces for expanding a normal interface between the CPU inside the exchange and the port processors 2a to 2n to the outside of the exchange main body 1.

In the present system, the port processors 2a to 2n shown in the figure are installed at a line distance outside the range (outside the allowable range) of the line around which the line accommodated in the exchange main body 1 can be routed. Therefore, the remote shelf 4a
Of the remote shelves 4a, 4
By connecting a digital leased line 5 between b, the remote shelves 4a,
4b is installed oppositely, and the port processors 2a to 2n are connected to the exchange main body 1 by connecting the port processors 2a to 2n via one remote shelf 4b (remote shelf on the remote site). It is assumed that That is, it is assumed that the real terminals on the remote side are respectively connected to the port processors 2a to 2n on the remote side.

The present system having such a configuration corresponds to a case where the extension mains are distributed over a wide range of distances including remote offices when the exchange main body 1 is a private branch exchange (PBX). .

FIG. 2 shows the internal structure of the remote shelves 4a and 4b. Remote shelves 4a and 4b are CPUs
401, XPC (X.25 protocol controller)
402, interface LSI 403, main memory 404, DMA buffer memory 405, data bus 406, bus arbiter 407, bus buffer 408
It is composed by.

Of these, the CPU 401 is a processor that plays a central role in control in the remote shelf, and uses, for example, a microprocessor. The CPU 401 also sends a data image according to the packet format of the communication protocol “X.25” to the main memory 4.
No. 04 on the XPC 402
The main memory 404 to the XPC 402.
It has a function of controlling the data developed above to be DMA-transferred.

Further, the XPC 402 is a communication protocol "X.
It is a communication control LSI that supports the "5" protocol, has a built-in DMA function, receives a start address and the number of bytes to be DMA-transferred from the CPU 401, and receives data for a specified number of bytes from this start address. Is read out and sent to the communication path 502, or the address is sequentially updated from the start address until the designated number of bytes is reached, and the received data from the communication path 502 is written.

Further, the XPC 402 notifies the CPU 401 of the start of the execution of the DMA function and also gives a signal for notifying it to the bus arbiter 407 during the DMA execution period.
The arbiter 407 can grasp the current state of the XPC 402 by this signal.

The data bus 406 of the CPU 401 has a bus buffer 408 interposed in the middle so that it can be divided into the left and right areas A and B in the figure with the bus buffer 408 as a boundary. The bus 406 can be divided into left area A and right area B or can be integrated.

Further, 501 and 502 are communication paths, the communication path 502 is a digital leased line, and control information is transmitted by the X.25 protocol. Communication path 50
1 is a low-speed communication path, for example, port processors 2a to 2n
One end is connected to the interface (in the case of the exchange side) connected to the system bus inside the exchange main body (PBX) 1 (in the case of a remote place), and interrupts can be continuously generated at the minimum cycle value T = 125 μs. . In the following, the low-speed communication path will be described as the exchange main body (PBX) 1 side.

The communication interface LSI 403 includes an interface of the exchange main body 1 and the remote shelf 40.
3 is a circuit for exchanging data with the data bus 3, and is connected to the area A side of the data bus 406. Then, the communication interface LSI 403 captures data each time it receives data from the exchange main body 1, and then executes CP.
Interrupt request to U 401, CPU 40
In response to the request from No. 1, the data on the data bus 46 is taken in and sent to the communication path 51.

Therefore, when the CPU 401 receives this interrupt request, it interrupts the current processing and accepts the interrupt request, and the communication interface L is received by this interrupt request.
The data taken in to SI403 is transferred to the data bus 406.
Is output to the main memory 404 and is temporarily stored in a predetermined area of the main memory 404.

The main memory 404 holds various control programs and data of the CPU 401, and is connected to the area A side of the data bus 406. DM
The A buffer memory 405 is a memory for temporarily holding data to be DMA-transferred, and is connected to the area B side of the data bus 406.

The bus arbiter 407 is the data bus 40.
6 is an arbitration circuit that performs control for dividing or integrating 6 into areas A and B, and operates under the control of the CPU 401 to control the bus buffer 408.
Such an arbitration operation is performed. The bus buffer 408 receives a control signal from the bus arbiter 407,
It may be in a state of passing data or in a high impedance state.

In this system, as shown in FIG.
Of the address space of the U 401, the CPU 401
, A program storage area E1 is defined as a storage area for the control program and data necessary for executing the program, and a first buffer area E2 for storing data exchanged with the communication interface LSI 403 is defined.
Furthermore, a second buffer area E3 for DMA transfer, which is used for storing data for DMA transfer, is defined and allocated to different address areas. Of these, the program storage area E1 and the first buffer area E2 are main areas. It is allocated to the allocation address of the memory 404, and the second
The buffer area E3 of is allocated to the allocation address of the DMA buffer memory 404.

Then, the bus arbiter 407 controlled by the CPU 401 controls the bus buffer 408 to divide the data bus 406 into two areas A and B at the time of DMA transfer by the XPC 402, and DMA transfer is performed. As a result of being controlled so as to release the division of the two areas A and B when not opened, the area A of the data bus 406 is completely separated from the area B which is the DMA transfer processing system even during the DMA transfer processing. It can be operated independently. The operation of this system having such a configuration will be described.

It is assumed that transmission data arrives from the PBX side via the communication path 501 with a minimum period of 125 μs. This transmission data is fetched by the communication interface 403, and the communication interface 403 outputs an interrupt request to the CPU 401 every fetching. When the CPU 401 receives an interrupt request, it interrupts the process and accepts this request,
The data fetched by the communication interface 403 is stored in the first buffer area E2 of the main memory 404.

In this way, the transmission data transmitted from the PBX side is fetched by the communication interface 403, and the main memory 40 is processed by the interrupt processing at each time.
It is stored in the first buffer area E2 of No. 4.

The data stored in the first buffer area E2 of the main memory 404 is the communication path 502.
To the DMA buffer memory 405
Transferred to. This transfer is sequentially performed by the CPU 401 when the transfer processing routine is executed. When a predetermined amount of data is accumulated in the DMA buffer memory 405 by the transfer processing, the CPU 401 instructs the XPC 402 to transfer to the communication path 502.

At this time, the CPU 401 sends out to the data bus 406 the start address of the area where the data to be transferred is stored in the address space of the DMA buffer memory 405 and the number of bytes to be transferred to the data bus 406, and the XPC
Set it to 402. And the bus arbiter 407
To place the bus buffer 406 in a high impedance state, which causes the bus arbiter 407 to
Keeps bus buffer 408 in a high impedance state. Therefore, the data bus 406 is divided into two areas A and B by the bus buffer 408 in the high impedance state, and the areas are completely isolated from each other.

On the other hand, the XP which has received the information of the start address and the number of bytes to be transferred and has also received the DMA transfer command.
The C 402 controls the reading of the buffer memory 405 while sequentially updating the address from the start address, and sends the read data to the communication path 502.

At this time, the area A of the data bus 406 divided by the bus buffer 408 is not affected by the DMA transfer. Therefore, CPU 4
01 makes it possible to execute the control program without being forced to stop the operation by the DMA. Therefore, an interrupt request generated from the communication interface 403 can be accepted each time transmission data arrives from the PBX side via the communication path 501, and the reception process can be continued.

In addition, the XPC 402 ends the DMA transfer when the reading is completed by the number of bytes to be transferred, and notifies the bus arbiter 407. As a result, the bus arbiter 407 releases the high impedance state of the bus buffer 408, and integrates the divided areas A and B of the data bus 406.

As described above, the mapping of the buffer memories corresponding to the two different communication paths 501 and 502 is made independent, and the independent buffer memories are DM'd.
The A processing system and the CPU processing system can be divided into two, and both processing systems can be separated, so that the DMA processing system and the CPU processing system can be operated separately in parallel. Even if the XPC 402 is performing the DMA transfer process with the communication path 502, the CPU
The buffer 401 can perform buffering processing in real time in response to an interrupt from the communication interface LSI 403.

The DMA transfer of the received data from the communication path 502 is performed by receiving the data from the communication path 502.
The communication interface 403b requests DMA transfer, which causes the XPC 402 to issue a DMA processing request to the CPU 401, which causes the CPU 401 to set the start address and the number of bytes in the XPC 402, and to instruct DMA transfer, -A command is issued to the arbiter 407 to put the bus buffer 408 in a high impedance state. Therefore, the data bus 406 is divided into two areas A and B by the bus buffer 408 in the high impedance state, and the areas are completely isolated from each other.

On the other hand, the XP which has received the information of the start address and the number of bytes to be transferred and which has received the DMA transfer command
The C 402 controls the writing of the received data of the XPC 402 to the buffer memory 405 while sequentially updating the address from the head address.

At this time, the area A of the data bus 406 divided by the bus buffer 408 is not affected by the DMA transfer. Therefore, CPU 4
01 makes it possible to execute the control program without being forced to stop the operation by the DMA.

The XPC 402 ends the DMA transfer when the writing is completed for the number of bytes to be transferred,
Notify the Bus Arbiter 407. This allows the bus
The arbiter 407 solves the high impedance state of the bus buffer 408 and integrates the divided areas A and B of the data bus 406.

The case where the XPC 402 directly transfers data to and from the communication path 502 has been described above as an example.
The MA transfer system can also be configured to exchange data with the communication path 502 by DMA transfer with an interface LSI for communication interposed. An example thereof is shown in FIG. The configuration of FIG. 4 is basically the same as that of FIG. 2 except that a communication interface LSI is also provided in the DMA transfer system.

In this case, 403a is an interface LSI for low speed communication and 403b is an interface LSI for high speed communication, and the interface LSI 403a is the same as that described in FIG.

Interface LSI 40 for high speed communication
3b receives the data from the communication path 502 and then XPC 4
02, a DMA transfer request is issued, and received data is sequentially output to the data bus 406 by a DMA control signal, or data from the data bus 406 is fetched and output to the communication path 502.

Further, the XPC 402 uses the communication protocol "X. 2
It is a communication control LSI that supports the "5" protocol, has a built-in DMA function, receives the start address and the number of bytes to be DMA-transferred from the CPU 401, and directly accesses the buffer memory 4405. Control is performed such that data of a specified number of bytes is read from the start address and is sent to the data bus 406, or the address is sequentially updated until the specified number of bytes is reached from the start address while writing to the buffer memory 405. is there. Further, the XPC 402 notifies the CPU 401 of the start of the execution of the DMA function, and the bus arbiter 407 is executed during the DMA execution period.
To give it a signal
The bus arbiter 407 receives the signal from the XPC 40.
It is possible to grasp the current status of the second item.

In this system having such a configuration, the low-speed communication system for transmitting / receiving the transmission / reception data under the control of the CPU is the same as the operation of the system described in FIG. In addition, the transmission data transferred to the DMA buffer memory 405 is DMA
When transferring, the CPU 401 commands the XPC 402 to transfer to the communication path 502.

At this time, the CPU 401 sends to the data bus 406 the information of the start address of the area in which the data to be transferred is stored in the address space of the DMA buffer memory 405 and the number of bytes to be transferred, and the XPC
Set it to 402. And the bus arbiter 407
To place the bus buffer 406 in a high impedance state, which causes the bus arbiter 407 to
Keeps bus buffer 408 in a high impedance state. Therefore, the data bus 406 is divided into two areas A and B by the bus buffer 408 in the high impedance state, and the areas are completely isolated from each other.

On the other hand, the XP which has received the information of the start address and the number of bytes to be transferred and has also received the DMA transfer command.
The C 402 controls the reading of the contents of the buffer memory 405 while sequentially updating the address from the start address.
The read data is used for the communication interface LSI 40.
3b, communication interface LSI 403
b transmits the fetched data to the communication path 502.

At this time, the area A of the data bus 406 divided by the bus buffer 408 is not affected by the DMA transfer. Therefore, CPU 4
01 makes it possible to execute the control program without being forced to stop the operation by the DMA. Therefore, an interrupt request generated from the communication interface 403a can be accepted each time transmission data arrives from the PBX side via the communication path 501, and the reception process can be continued.

In addition, the XPC 402 ends the DMA transfer when the reading is completed by the number of bytes to be transferred, and notifies the bus arbiter 407. As a result, the bus arbiter 407 releases the high impedance state of the bus buffer 408, and integrates the divided areas A and B of the data bus 406.

The DMA transfer of the received data from the communication path 502 is performed by receiving the data from the communication path 502.
The communication interface 403b requests DMA transfer, which causes the XPC 402 to issue a DMA processing request to the CPU 401, which causes the CPU 401 to set the start address and the number of bytes in the XPC 402, and to instruct DMA transfer, -A command is issued to the arbiter 407 to put the bus buffer 408 in a high impedance state. Therefore, the data bus 406 is divided into two areas A and B by the bus buffer 408 in the high impedance state, and the areas are completely isolated from each other.

On the other hand, the XP which has received the information of the start address and the number of bytes to be transferred and has also received the DMA transfer command.
The C 402 sequentially updates the address from the above-mentioned start address, and stores the communication interface L in the buffer memory 405.
Write control of the received data of SI 403b is performed.

At this time, the area A of the data bus 406 divided by the bus buffer 408 is not affected by the DMA transfer. Therefore, CPU 4
01 makes it possible to execute the control program without being forced to stop the operation by the DMA.

The XPC 402 ends the DMA transfer when the writing is completed for the number of bytes to be transferred,
Notify the Bus Arbiter 407. This allows the bus
The arbiter 407 solves the high impedance state of the bus buffer 408 and integrates the divided areas A and B of the data bus 406.

As described above, according to the present invention, the address space of the memory is divided into at least two, and the DM
A switching means for controlling separation / coupling between the A transfer processing system and the processing system by the CPU is provided, and one of the address spaces of the divided memory is provided to the processing system by the CPU
In addition, the other is provided by being distributed to the DMA transfer processing system, and each can be used as a buffer memory for communication.
During MA transfer, the DMA transfer processing system and the CPU processing system are separated by the switching means so that the CPU processing system can be operated during the DMA transfer process. This allows the CPU to operate during the DMA transfer process. The processing can be continued, and other processing by the CPU can be executed while performing the DMA processing, and it is possible to perform a design that makes full use of the potential performance of the system. The present invention is not limited to the embodiments described above and shown in the drawings, but can be appropriately modified and implemented within the scope of the invention.

[0063]

As described above in detail, according to the present invention,
It is possible to provide a microprocessor application device that can realize a system capable of simultaneously processing other processes such as data reception from a communication path during execution of high-speed DMA transfer with the communication path.

[Brief description of drawings]

FIG. 1 is a system block diagram showing the overall configuration of an embodiment of the present invention.

FIG. 2 is a block diagram showing details of a main part of FIG.

FIG. 3 is a memory map for explaining the allocation status of memory space in this system.

FIG. 4 is a block diagram showing another embodiment of the present invention.

FIG. 5 is a block diagram for explaining a conventional example.

[Explanation of symbols]

1 ... Switch (PBX) main body, 2a, 2b, to 4n ... Port processor, 5 ... Digital dedicated line, 41, 401 ...
CPU, 42 ... DMA controller, 402 ..., 40
3, 403a, 403b ... Communication interface LSI,
45 ... Memory, 404 ... Main memory, 405 ... DMA
Buffer memory, 406 ... Data bus, 408 ... Bus buffer, 407 ... Bus arbiter, 501, 502
… Communication path.

Claims (1)

[Claims] 1. A system in which a memory, a processor and a direct memory access means are connected via a bus, and the memory is directly accessed by the direct memory access means instead of the memory access control by the processor. In a processor application system that enables data transfer between the memory and the outside, direct memory access means
In order to separate / couple the memory access transfer processing system and the processing system by the processor, switching means for switching the bus is provided, and the address space of the processor is divided so that one of the processing system of the processor and the other A processor characterized in that the memory is allocated to a direct memory access transfer processing system, and the processor is provided with a processing function that causes the switching means to perform separate control during direct memory access transfer. Applied equipment.