JPH041819A - Data block controller - Google Patents

Abstract

PURPOSE:To process the data received via a buffer of the large capacity as well as a long block by providing the internal bus adaptors having the buffers of the small capacity into the host interface control circuits and the formats and connecting these adaptors to each other via the internal buses. CONSTITUTION:The adaptors 32 - 35 containing the buffers of the small capacity are provided into the host interface control circuits 23 and 24 and the formats 27 and 28 respectively. These adaptors 32 - 35 are connected to each other via the internal buses 36. Therefore the buses 36 are never occupied even while a long block is being processed with use of the adaptors 32 - 35. Thus the data received via the buffers 25 and 26 of the large capacity and a long block received via the adaptors 32 - 35 can be processed at one time. Then the data processing efficiency is improved.

Description

[Detailed Description of the Invention] [Summary] This invention relates to a data block control device that controls the transfer of data blocks that are less than or equal to the buffer capacity and long and large blocks that are greater than or equal to the buffer capacity. The purpose of the present invention is to provide a data block control device that can improve efficiency, and includes a host interface control circuit that controls data transmission and reception with a host computer, a buffer in which data is written and read by the host interface control circuit, and and a formatter that performs formatting for transmitting and receiving data between the buffer and the drive, and are connected to each other by an internal bus, each of the host interface control circuits and the Each formatter was configured to be provided with an adapter having a small capacity buffer connected via the internal bus.

[Industrial Field of Application] The present invention relates to a data block control device that controls the transfer of data blocks that are smaller than a buffer capacity and long and large blocks that are larger than a buffer capacity.

In a file control device having a data buffer, such as a magnetic tape control device, when attempting to read or write a block with a data length larger than the buffer capacity, writing to the buffer and reading from the buffer must be performed in parallel. On the other hand, if the buffer is connected to and shared by a plurality of magnetic tape control devices via a common bus, other magnetic tape control devices cannot use the common bus and buffer while the long block is being processed.

Therefore, it has been desired to be able to use a buffer and a common bus in one magnetic tape controller while the other magnetic tape controller is using long blocks.

[Prior Art] As a conventional data block control device, for example, the 11th
There is something like the one shown in the figure.

In FIG. 11, reference numerals 1 and 2 are magnetic tape control devices, and these magnetic tape control devices 1 and 2 are connected to interface control circuits 4 and 5 that control the transmission and reception of data from the host computer 3, and interface control circuits 4 and 5 that control data writing and reading. buffer 6.7, buffer 6.7 and drive 8,
It has formatters 10 and 11 that perform formatting for transmitting and receiving data to and from 9.

The magnetic tape control devices 1 and 2 are configured to be cross-called via a common bus 12, and the interface control circuit 4 and formatter 10, the interface control circuit 4 and formatter 11, and the interface control circuit 5 and formatter 11. Operation is possible by a combination of the interface control circuit 5 and formatter 10.

Therefore, each interface control circuit 4, 5 can perform read/write processing using the vacant formatters 10, 11. FIG. 12 shows the data flow in this conventional example.

[Problems to be Solved by the Invention] However, in such a conventional data block control device, while a long block is being processed, the bus and buffer cannot be used by other magnetic tape control devices. Even if there are two magnetic tape controllers, only one can operate at the same time, so there is a problem in that the data processing efficiency is not good.

The present invention has been made in view of such conventional problems, and provides a data block control device that can process long blocks and normal data blocks simultaneously and improve processing efficiency. It is intended to.

[Means to solve the problem] FIG. 1 is a diagram explaining the principle of the present invention.

In FIG. 1, 23.24 is a host interface control circuit that controls data transmission and reception with the host computer, and 25.26 is the host interface control circuit 2.
3.24 is a buffer in which data is written and read; 27 and 28 are formatters that perform formatting for transmitting and receiving data between the buffer 25 and 26 and the drive; 36 is an internal bus; - 35 are adapters having small capacity buffers connected to each of the host interface control circuits 23, 24 and each of the formatters 27, 28 via the internal bus 36.

[Operation] Each host interface control circuit and each formatter is provided with an adapter having a small capacity buffer, and the adapters are connected to each other by an internal bus.

Therefore, the internal bus is not occupied even during processing of long blocks using the adapter. That is, data processing via a large-capacity buffer and processing of a long block via an adapter can be performed simultaneously.

As a result, data processing efficiency can be improved.

[Example] Embodiments of the present invention will be described below based on the drawings.

FIGS. 2 to 10 are diagrams showing an embodiment of the present invention.

First, to explain the configuration, in Fig. 2, 21.22
are magnetic tape control devices, and these magnetic tape control devices 21. ．． 22 includes host interface control circuits 23 and 24, buffers 25 and 26, and formatters 27 and 28, respectively.

The host interface control circuits 23.24 write the data received from the host computer 29 into the buffers 25.26 during writing, and transfer the data in the buffers 25.26 to the host computer 29 during reading. The formatter 27.28 reads the data in the buffer 25.26 when writing, formats it into a data block format, and writes it to the drive 30.31. When reading, the formatter 27.28 demodulates the signal read from the drive 30.31. Take out the buffer 25.
Write to 26. Data is read and written to the buffers 25.26 by the host interface control circuits 23.24, and data is also read and written by the formatters 27.28.

Internal bus adapters 32-35 are provided in the host interface control circuits 23, 24 and formatters 27, 28, respectively.

36 is an internal bus, host interface control circuit 23.24 and formatter 27.28
are connected to an internal bus 36 via internal bus adapters 32 to 35, and the internal bus 36 is connected to buffers 25 and 26, respectively.

The internal bus adapters 32 to 35 each have a small capacity buffer of 256 bytes, as shown in FIG.
have. Data is written from the host interface control circuit 23.24 or the formatter 27.28 into the buffer 36.37 under the control of the write control circuit 39;
．． 24 or formatters 27 and 28 under the control of the read control circuit 40. Note that 41 is a register that temporarily stores data, and 42 is a generating circuit that generates a control word.

For data blocks smaller than the buffer capacity, data is transferred between internal bus adapters 32 to 35 and buffers 25 and 26, as shown in FIG. This is called buffer access mode (hereinafter referred to as BAM). In this BAM mode, the number of words to be transferred in one packet communication and the start address of the buffers 25 and 26 are specified. In one packet communication, the first one word of control word (CTW) and 64 words of data word (DTW) are transferred. The structure of the control word (CWT) in BAM mode is shown in FIG.

For long blocks larger than the buffer capacity, the fifth
As shown in the figure, the host interface control circuit 23
．． 24 internal bus adapter 32.33 and formatter 27.28 internal bus adapter 34.
Data is transferred to and from 35. This is called direct access mode (hereinafter referred to as DAM). In this DAM mode, the number of words to be transferred in one packet communication and the communication partner are specified. Control word in DAM mode (C
The configuration of the WT is shown in FIG.

Both BAM and DAM modes use the buffers 37 and 38 of the internal bus adapters 32 to 35.
By performing packet communication with the other party's buffer 37, 38 or buffer 25, 26 in units of 256 bytes, and by controlling the priority of the start request line from the internal bus adapters 32 to 35, the communication can be started using the internal bus even when a long block is being processed. 36 is prevented from being exclusively used.

Next, the operation will be explained.

FIG. 8 shows an example of DAM mode. This example shows the transfer of a large block from the host interface control circuit 23 to the formatter 27. Data received by the host interface control circuit 23 from the host computer 29 is transferred to the formatter 27, and the formatter 27 writes and formats the data. Convert to drive 30
．． 31.

The data received from the host computer 29 is first
When 256 bytes of data are stored in the buffer 43 of the internal bus adapter 32 of the host interface control circuit 23 and accumulated, transfer to the buffer 44 of the internal bus adapter 34 of the formatter 27 is started. During this time, data from the host computer 29 to the host interface control circuit 23 is transferred to the buffer 45.
Transfer continues. host computer 29
The data transfer rate between the host interface control circuit 23 and the host interface control circuit 23 is set to be slower than the data transfer rate between the internal bus adapters 32 to 35. Therefore, during data transfer to buffer 45, buffer 4
3 and the bath sofa 44 has been completed.

Next, when 256 bytes of data are stored in the buffer 45, data transfer from the buffer 45 of the host interface control circuit 23 to the buffer 46 of the formatter 27 is started.

When the formatter 27 receives 256 bytes of data to the buffer 44, it starts writing data to the drives 30, 3]. Formatter 27 then transfers the data in buffer 46 to drive 30.31.

In this way, a large block is transferred.

In addition, 47 and 48 in FIG. 8 are control word generation circuits, and 49
．． 50 is a read/write control circuit, and 51.52 is a DAM recognition circuit.

Next, FIG. 9 shows protocols for one packet communication in each mode of BAM and DAM.

In BAM mode, a data word is transferred following a control word, and when the transfer is complete, a response good (RP C
) is responded to. In DAM mode, the other party's buffer 37.
38 is in use, the target buffers 37 and 38 respond with a response busy (RPB) using a control signal (IBCA), and transfer is inhibited. Thereafter, when the transfer is completed, a response good (RPC) is sent as a response.

Next, four internal bus adapters 32 are shown in FIG.
An example is shown in which the internal buses 36 and 35 are simultaneously using the internal bus 36.

Internal bus adapters 32-35 connect host computer 29 and host interface control circuit 23.2.
Data transfer rate and formatter between 4 and 27.28
The data transfer speed of the internal bus 36 is 4 bytes, and the data transfer speed of the internal bus 36 is 4 bytes. Therefore, as shown, internal bus 36 is used in a time-sharing manner by host interface control circuit 23.24 and formatter 27.28.

In this way, data processing via the large capacity buffers 25 and 26 can be performed even during processing of long and large blocks.

[Effects of the Invention] As described above, according to the present invention, an internal bus adapter having a small capacity buffer is provided in each host interface control circuit and each formatter, and the devices are connected to each other by an internal bus. As a result, it is possible to process data via a large-capacity buffer at the same time as processing a large block. As a result, data processing efficiency can be improved.

[Brief explanation of drawings]

Fig. 1 is a diagram explaining the principle of the present invention, Fig. 2 is a block diagram showing an embodiment of the invention, Fig. 3 is a configuration diagram of the adapter, Fig. 4 is a diagram showing the data flow in BAM mode, Figure 5 is a diagram showing the data flow in DAM mode, Figure 6 is in BA
The configuration diagram of CTW in M mode, Figure 7 is the CTW in DAM mode.
TW configuration diagram, Figure 8 is a diagram explaining the operation in DAM mode, Figure 9 is a diagram showing the packet communication protocol, Figure 10 is a diagram explaining the usage state of the internal bus, and Figure 11 is a diagram showing the conventional example. , FIG. 12 is a diagram showing a conventional data flow. In the figure, 21.22...magnetic tape control device, 23.24...
・Host interface control circuit, 25.26...
Large capacity buffer, 27.28...Formatter 29...Host combiner, 30.31...Drive, 32-35...Internal bus adapter, 36...
・Internal bus, 37.38.43-46...Small capacity buffer, 39
...Write control circuit, 40...Read control circuit, 41...Register, 42.47.48...Control word generation circuit, 49.5
0...Read/write control circuit, 51.52...DA
M recognition circuit.

Claims (1)

[Claims] Host interface control circuits (23) and (24) that control data transmission and reception with the host computer, and buffers (23) and (24) in which data is written and read by the host interface control circuits (23) and (24).
25), (26), and formatters (27), (28) that perform formatting for transmitting and receiving data between the buffers (25), (26) and the drive.
and connected to each other by an internal bus (36), the host interface control circuits (23), (24) and the formatters (27), (28) have A data block control device characterized in that adapters (32 to 35) each having a small capacity buffer are connected via a bus (36).