JPS61173555A - Connecting method of communication controller - Google Patents

Abstract

PURPOSE:To obtain a device suitable for connecting both many intermediate- speed and low-speed circuits and a small number of high-speed circuits by providing data holding means, address holding and updating means, and transfers byte number holding and updating means for plural channels, and further providing a means which fixes the channels of the address holding and updating means and transfer byte number holding and means as circuits. CONSTITUTION:When high-speed circuits are connected, four channels are assigned for each circuit as to a data holding circuit 11 and a control information holding circuit 14. One address holding and updating circuit 12 and one transfer byte number holding and updating circuit 13 are fixed for every circuit. Channels of the data holding circuit 11, address holding and updating circuit 12, transfer byte number holding and updating circuit 13, and control information holding circuit 14 are specified through a signal line 108 and when data are read out of and written in circuit adapters 551-55n, a channel corresponding to a circuit address specified through a signal line 112 is specified. A signal line 109 is for fixing channels of the address holding and updating circuit 12 and transfer byte number holding and updating circuit 13, and realized bit by setting a certain bit of the signal line 108 to a fixed value.

Description

DETAILED DESCRIPTION OF THE INVENTION [Industrial Application Field] The present invention is used for connecting an information processing device to a communication line. The present invention relates to a communication control device that connects both medium-low speed lines and high-speed lines.

〔overview〕

In a communication control device connection method that adaptively connects information processing equipment terminals to communication lines with different communication speeds, hardware suitable for the number of lines and performance is used for medium-low speed lines, and the above-mentioned hardware is used for high-speed lines. By fixedly using multiple pieces of data retention means and information retention means for one line in the hardware, the capacity of the data retention means can be increased for high-speed line connections, and the efficiency of hardware usage can be increased. This makes it possible to improve the connection efficiency, and to obtain good connection effects for both multiple connections of medium and low-speed lines and connections of a small number of high-speed lines.

[Conventional technology]

Conventionally, in communication control equipment that connects communication lines, in order to control data transfer between the buffer memory inside the communication control equipment and the line adapter, address retention is used to hold and update a number of buffer memory addresses corresponding to the number of lines. update means, data holding means for holding sent and received data,
Hardware resources such as transfer byte number holding/updating means for holding and updating the number of transfer bytes and control information holding means for holding control information for controlling data transfer are provided.

[Problem that the invention seeks to solve]

However, when connecting many medium-speed or low-speed lines with the same hardware, and when connecting a small number of high-speed lines,
It is necessary to prepare address holding/updating means, data holding means, transfer byte count holding/updating means, and control information holding means corresponding to the number of medium-speed or low-speed lines connected, and at high speeds. When a line is connected, it is necessary to consider the capacity of the data holding means that does not cause any performance problems. The above hardware resources were not used effectively.

The present invention solves the above problems, and makes it possible to increase the capacity of data holding means for high-speed line connections, making it possible to use the hardware resources efficiently, and connecting a large number of medium- and low-speed lines. It is an object of the present invention to provide a method for connecting a communication control device that is suitable for both cases where a small number of high-speed lines are connected.

[Means for solving problems]

The present invention provides a data holding means for holding transmission/reception data for a line, and an address holding/updating means for holding and updating a buffer memory address for data transfer between the data holding means and a buffer memory in a communication control device. , a transfer byte number holding/updating means for holding and updating the number of transfer bytes for performing the data transfer, and a control information holding means for holding control information for controlling the data transfer for a plurality of channels. In a communication control device that connects a high-speed line, means is provided for fixing the channel numbers of the address holding/updating means and the transfer byte number holding/updating means, and when connecting a medium-low speed line, the data holding and address When controlling a high-speed line by controlling the data transfer between the line adapter and the buffer memory by associating the channel numbers of the holding/updating means, the number of transferred bytes holding/updating means, and the control information holding means with the line number of the medium/low speed line. In this case, the address holding/updating means and transfer byte count holding/updating means use one fixed channel number per line, and the data holding means and control information holding means use a plurality of channels per line. The present invention is characterized in that it is configured to control data transfer between the adapter and the buffer memory.

[For production]

In order to efficiently connect medium-speed, low-speed, and high-speed information sharing connection lines, the present invention uses a plurality of hardware per line to maintain data. A sufficient data storage area is obtained in the means, so that "overrun" does not occur during transmission, and when receiving, even if the buffer memory is delayed, the data to be transmitted is prepared in the data holding means, and "underrun" does not occur.
It doesn't happen either. Since the capacity of the data holding means and control information holding means per line can be easily expanded in this way, it is possible to reliably connect medium-low speed lines and high-speed lines.

〔Example〕

Next, an embodiment of the present invention will be described in detail with reference to the drawings.

FIG. 1 is a block diagram of a line common control section of an apparatus according to an embodiment of the present invention, which controls data transfer between a buffer memory in a communication control apparatus and a line adapter connected to a line. FIG. 2 is a block diagram schematically showing a communication control device including a line common control section 1 and its peripheral devices, which is an embodiment of the present invention, and the peripheral devices include a processor section 2, a host interface control section 3, It is composed of a buffer memory 4 and line adapters 510 to 51n.

Does signal line 20 use the above communication system? 2 is a schematic diagram of the memory bus of the II device, including the 4-byte data lines of FIG. 1, as well as address lines and control lines; FIG. Signal line 40 is a schematic diagram of a line adapter bus and includes a 1-byte data line, as well as address lines and control lines.

In FIG. 1, the line common control unit l of the present invention has 64 channels with a capacity of 4 bytes per channel, a data holding circuit 11 for holding transmitted and received data, and 64 channels with a capacity of 3 bytes per channel. An address holding/updating circuit 12 that has a channel and holds and updates the address of the buffer memory; and a transfer byte number holding/updating circuit that has 64 channels with a capacity of 2 bytes per channel and holds and updates the number of transferred bytes. 13 and 64 channels with a capacity of 1 byte per channel, and holds control information necessary for data transfer control (control information holding circuit 14 and a control unit that controls the entire line common control unit). It is composed of a circuit 15.

The signal line 101 is a bidirectional 4-byte data line and is connected to the memory bus data line 21. The signal line 102 is a 3-byte address line and is connected to the memory bus address line 22. Signal line 103 is memory bus input control 'a2
3, and includes memory bus response signals and the like. The signal '41A104 is connected to the memory bus output control line 24 and includes a memory bus request signal and the like. Signal line 105
is a signal indicating the state of the transfer byte number holding/updating circuit 13 and a control signal line for the transfer byte number holding/updating circuit 13. The signal \a106 is a signal indicating the state of the address holding/updating circuit 12 and a control signal line for the address holding/updating circuit 12.

The signal line 107 is a signal indicating the state of the control information holding circuit 14 and a signal line for the control information holding circuit 14 . A signal line 108 is a signal line indicating channel numbers of the data holding circuit 11, the address holding/updating circuit 12, the transfer byte number holding/updating circuit 13, and the control information holding circuit 14. The signal line 109 is connected to the address holding/updating circuit 12 when a high-speed line is connected.
and a signal line for fixing the channel number of the transfer byte number holding/updating circuit 13.

The signal line 110 is a control signal line for the data holding circuit 11, and the signal line 111 connected to the data holding circuit 11 is a 1-byte bidirectional data line, and is connected to the line adapter bus data line 41. Signal line 112 is a line address signal line and is connected to line adapter bus address line 42 . The signal line 113 connected to the line control circuit 15 is connected to the line adapter bus input control line 43, and includes an interrupt signal line from the line adapter. Line control circuit 1
The signal line 114 connected to the line adapter bus output control '1IIA44 includes a read/write control line for the line adapter.

Next, the operation of the apparatus according to the embodiment of the present invention will be explained.

FIG. 3 is a diagram showing an example of control when a medium-low speed line is connected. Data holding circuit 11, address holding update circuit 12
, the channel number CHO of the transfer byte number holding/updating circuit 13 and the control information holding circuit 14, -------...--1
CH63 is the line number LNO,------------
, is compatible with LN63. Note that even line numbers indicate receiving lines, and odd numbers indicate transmitting lines.

The reception line is controlled as follows. When a reception instruction is issued from the processor section 2 in FIG. control information. The holding circuit 14 initializes the channel corresponding to the line number specified by the command, and instructs the line adapters 551 to 55n (FIG. 2) of the line number specified by the command to start receiving operations.

Each of the line adapters 551 to 55n generates a reception interrupt signal every time one character of data is received.

The circuit common control unit 1 is connected to the line adapter 5 by a signal line 112.
51 to 55n are scanned line by line, and an interrupt signal is detected through the signal line 113.

When the reception interrupt signal is detected, the line common control unit 1 controls the signal line 114 to transfer the received data of the line adapters 551 to 55n to the line adapter bus data line 41 and the signal line 1.
11 to a predetermined byte position specified by the address of the buffer memory of the data holding circuit 11, the transfer byte number holding/updating circuit 13 is updated, and the control information holding circuit 14 is stored at a predetermined byte position specified by the address of the buffer memory of the data holding circuit 11. Sets a flag indicating that valid data has been stored in the byte position.

Thereafter, the received data from the line adapters 551 to 55n are stored in the data holding circuit 11 in the same manner. Data holding circuit 1
When 4 bytes of data are stored in 1, it is detected by the flag of the control information holding circuit 14. ), signal line 104
A write request to the buffer memory 4 is output by controlling the buffer memory 4. When the bus control unit (not shown) detects through the signal line 103 that this write request has been accepted, the address holding/updating circuit 12 and the data holding/updating circuit 1
1 is sent to the memory bus 20 via the signal line 102 and the signal line 101, and written to the buffer memory, and the contents of the address holding/updating circuit 12 are updated.

Thereafter, the above operation is repeated in the same manner until the designated number of transfer bytes is completed or until a termination interrupt is reported from the line adapters 510 to 51n.

Next, control of the transmission line will be explained.

When a transmission instruction is issued from the processor unit 2 to the line common control unit 1, the address of the transmission buffer placed on the buffer memory 4 is stored in the address holding update circuit 12, and the transmission is performed as in the case of the reception line. The data byte length is stored in the transfer byte number holding/updating circuit 13, and the control information holding circuit 14 is initialized.

Next, a read request is made to the buffer memory 4 (FIG. 2), and when the read request is accepted, the contents of the address holding/updating circuit 12 are output to the memory bus, and the data at this address is stored in the data holding circuit 11. , updates the contents of the address holding/updating circuit 12.

Furthermore, it instructs the line adapter to start transmission operation.

The line adapter immediately outputs a transmission interrupt signal.

Thereafter, a transmission interrupt signal is output every time one character of data is transmitted. When the circuit common control unit 1 detects a transmission interrupt signal, the circuit common control unit 1 transmits data to the data holding circuit 11.
The content of a predetermined byte position specified by the panzer memory address of is written to the line adapter via the line adapter bus 40 as transmission data.

Thereafter, the transmission data of the data holding circuit 11 is written to the line adapter in the same manner. Once all the requests read from the buffer memory 4 have been written to the line adapter, a read request is made again from the buffer memory 4, and the above operation is repeated in the same manner until the transfer of the designated number of transfer bytes is completed.

FIG. 4 shows an example of control when a high-speed line is connected. In this case, the data holding circuit 11 and the control information holding circuit 14
Four channels are allocated to each line. The address holding/updating circuit 12 and transfer byte number holding/updating circuit 13 are fixed to one per line.

When the receiving line is in operation, data is written to the buffer memory 4 every time 4 bytes of received data are stored in the data holding circuit 11. Even if the completion of writing to the buffer memory 4 is delayed due to the influence of the control of the processor 2 (Fig. 2), a 12-byte storage area is prepared in the data holding circuit 11 for each line, so a reception line overrun will not occur. Hateful. Similarly, when the transmission line is in operation, the data holding circuit 11 reads out and stores 16 bytes of transmission data per line from the buffer memory 4, and then instructs the line adapter to start transmission.

Thereafter, each time 4 bytes of transmission data is written to the line adapter, it is read from the buffer memory 4. As in the case of operation of the receiving line, even if there is a delay in reading from the next buffer memory 4, 12 bytes of transmission data are prepared in the data holding circuit 11 per line, so underrun of the sending line is unlikely to occur.

The signal line 108 specifies the channels of the data holding circuit 11, the address holding/updating circuit 12, the number of transfer bytes holding/updating circuit 13, and the control information holding circuit 14, and is connected to the line adapter 55.
When reading and writing data from 1 to 55n, signal line 1
The channel corresponding to the line address specified in 12 is specified.

The signal line 109 fixes the channels of the address holding/updating circuit 12 and transfer byte count holding/updating circuit 13, and can be realized by setting a certain bit of the signal line 108 to a fixed value.

When connecting high-speed lines in this manner, it is possible to easily expand the capacity of the data holding circuit 11 and control information holding circuit 14 per line.

〔Effect of the invention〕

As explained above, the present invention has a plurality of channels of data holding means, address holding/updating means, and transfer byte number holding/updating means, and means for fixing the channels of the address holding/updating means and the transfer byte number holding/updating means. By having this, there is an effect that a communication control device suitable for both connecting a large number of medium-low speed lines and connecting a small number of high-speed lines can be realized.

[Brief explanation of the drawing]

FIG. 1 is a block diagram of a line common control unit according to an embodiment of the present invention. FIG. 2 is a schematic block diagram of a communication control device including an embodiment of the present invention and its peripheral devices. FIG. 3 is a control program configuration diagram when a low-speed line is connected. FIG. 4 is a control program configuration diagram when a high-speed line is connected. 1... Line common control section, 2... Processor section, 3.
... Upper interface control unit, 4... Buffer memory, 510-51n... Line adapter, 11... Data holding circuit, 12... Address holding update circuit, 13
...Transfer byte number holding update circuit, 14...Control information holding circuit, 15...Control circuit, 20...Memory bus, 21...Memory bus data line, 22...Memory bus address line , 23... memory bus input control line, 24
...Memory bus output, 40...Line adapter bus,
41... Line adapter bus data line, 42... Line adapter bus address line, 43... Line adapter bus input control line, 44... Line adapter output control line, 10
1.111...Data holding circuit read/write data line, 102...Memory address line, 103...Memory input control line, 104...Memory output system? IL line, 10
5... Transfer byte number holding update circuit control signal, 106.
...Address holding update circuit control signal, 107... Control information holding circuit control signal, 108... Channel address, 109... Channel fixing signal, 110... Data holding circuit control signal, 112... Line adapter address, 113...Line adapter input control line, 114...
・Line adapter output control line.

Claims (1)

[Claims] (1) Data holding means for holding data sent and received for the connection line, and address holding for holding and updating a buffer memory address for data transfer between the data holding means and the buffer memory in the communication control device. an updating means; a transfer byte number holding/updating means for holding and updating the number of transfer bytes for the data transfer; and a control information holding means for holding control information for controlling the data transfer; In a method of connecting a communication control device that allows connection of both a line and a high-speed line, when connecting a medium-low speed line by making it possible to fix the channel numbers of the above-mentioned address holding/updating means and transfer byte count holding/updating means. In order to control the data transfer between the line adapter and the buffer memory, the channel numbers of the data holding means, the address holding/updating means, the number of transferred bytes holding/updating means, and the control information holding means are made to correspond to the line number of the medium/low speed line. and when connecting a high-speed line, the address holding/updating means and transfer byte number holding/updating means use one fixed channel number per line, and the data holding means and control information holding means use A method for connecting a communication control device, characterized in that data transfer and control are performed between a line adapter and a buffer memory by using a plurality of channels per line.