JPS636893B2 - - Google Patents

Info

Publication number
JPS636893B2
JPS636893B2 JP55005757A JP575780A JPS636893B2 JP S636893 B2 JPS636893 B2 JP S636893B2 JP 55005757 A JP55005757 A JP 55005757A JP 575780 A JP575780 A JP 575780A JP S636893 B2 JPS636893 B2 JP S636893B2
Authority
JP
Japan
Prior art keywords
computer
data
receiving
computers
transferred
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired
Application number
JP55005757A
Other languages
Japanese (ja)
Other versions
JPS56103753A (en
Inventor
Shigetake Nakaosa
Koichi Kunimasa
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Hitachi Ltd
Original Assignee
Hitachi Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi Ltd filed Critical Hitachi Ltd
Priority to JP575780A priority Critical patent/JPS56103753A/en
Publication of JPS56103753A publication Critical patent/JPS56103753A/en
Publication of JPS636893B2 publication Critical patent/JPS636893B2/ja
Granted legal-status Critical Current

Links

Classifications

    • GPHYSICS
    • G06COMPUTING; CALCULATING OR COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F15/00Digital computers in general; Data processing equipment in general
    • G06F15/16Combinations of two or more digital computers each having at least an arithmetic unit, a program unit and a register, e.g. for a simultaneous processing of several programs
    • G06F15/163Interprocessor communication
    • G06F15/173Interprocessor communication using an interconnection network, e.g. matrix, shuffle, pyramid, star, snowflake
    • G06F15/17337Direct connection machines, e.g. completely connected computers, point to point communication networks
    • G06F15/17343Direct connection machines, e.g. completely connected computers, point to point communication networks wherein the interconnection is dynamically configurable, e.g. having loosely coupled nearest neighbor architecture

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Physics & Mathematics (AREA)
  • Theoretical Computer Science (AREA)
  • Mathematical Physics (AREA)
  • Software Systems (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Information Transfer Systems (AREA)
  • Multi Processors (AREA)

Description

【発明の詳細な説明】 本発明は、複数の電子計算機を接続してデータ
転送を行なう計算機間のデータ転送方式に関する
ものである。
DETAILED DESCRIPTION OF THE INVENTION The present invention relates to an inter-computer data transfer method that connects a plurality of electronic computers and transfers data.

このような計算機間データ転送方式にはチヤネ
ル結合方式が一般に用いられている。チヤネルと
は中央処理装置の指令を受けて入出力装置を制御
する装置で、チヤネル結合方式は、そのチヤネル
を直接結合し、電子計算機間で情報を伝達する方
式である。
A channel coupling method is generally used for such inter-computer data transfer method. A channel is a device that controls input/output devices in response to instructions from a central processing unit, and the channel coupling method is a method of directly coupling these channels to transmit information between electronic computers.

このようなチヤネル結合方式では、次のような
問題があるため、高速に処理を行なうことができ
なかつた。
With such a channel combination method, high-speed processing has not been possible due to the following problems.

(1) 1回の情報伝達で、送信用および受信用計算
機のそれぞれに2回の割込みが発生するので割
込み処理のオーバヘツドが大きい。
(1) One time of information transmission generates two interrupts in each of the sending and receiving computers, so the overhead of interrupt processing is large.

(2) 相手の計算機を1つの入出力装置とみなし、
標準的な入出力手順に従つて送受信を行なうの
でオーバヘツドが大きい。
(2) Treat the other party's computer as one input/output device,
Since transmission and reception are performed according to standard input/output procedures, overhead is large.

本発明の目的は、高速に計算機間のデータ転送
を行なえるようにした計算機間データ転送方式を
提供することにある。
An object of the present invention is to provide an inter-computer data transfer method that allows data transfer between computers at high speed.

このような目的を達成するために、本発明では
データ転送を制御する制御手段と、スイツチ手段
とを備え、制御手段の制御に基づいて、送信側お
よび受信側電子計算機をスイツチ手段を通して接
続し、送信側電子計算機の主記憶装置からのデー
タを受信側電子計算機の主記憶装置へ転送するよ
うにしたことに特徴がある。
In order to achieve such an object, the present invention includes a control means for controlling data transfer and a switch means, and a transmitting side computer and a receiving side computer are connected through the switch means based on the control of the control means, The feature is that data from the main memory of the sending computer is transferred to the main storage of the receiving computer.

以下、本発明の実施例を図面により詳細に説明
する。
Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings.

第1図は本発明による計算機間データ転送方式
を実現する装置のブロツク図である。
FIG. 1 is a block diagram of an apparatus for realizing an inter-computer data transfer system according to the present invention.

図において、1はデータ転送を制御する計算機
結合装置、2はスイツチマトリツクス、3,4は
電子計算機を示す。電子計算機3において、31
は演算制御装置、32は記憶制御装置、33は主
記憶装置を示し、電子計算機4において、41は
演算制御装置、42は記憶制御装置、43は主記
憶装置を示す。
In the figure, 1 is a computer coupling device for controlling data transfer, 2 is a switch matrix, and 3 and 4 are electronic computers. In electronic computer 3, 31
32 is an arithmetic control device, 32 is a storage control device, and 33 is a main storage device. In the electronic computer 4, 41 is an arithmetic control device, 42 is a storage control device, and 43 is a main storage device.

この例では、電子計算機が送信側と受信側の2
台の場合について示したが、それに限定されるも
のでないことは言うまでもない。
In this example, a computer is used on both the sending and receiving sides.
Although the case of a stand is shown, it goes without saying that the present invention is not limited thereto.

第1図において、電子計算機3が送信側計算機
となつて、それから受信側の電子計算機4へ情報
を伝送する場合を考える。
In FIG. 1, consider the case where computer 3 acts as a sending computer and then transmits information to computer 4 on the receiving side.

送信側電子計算機3では、送信準備として送信
要求を示す制御情報と送信すべき情報を主記憶装
置33に用意し、また、受信側電子計算機4で
は、受信準備として、受信要求を示す制御情報を
主記憶装置43に用意する。
The sending computer 3 prepares control information indicating a transmission request and information to be sent in the main storage device 33 in preparation for transmission, and the receiving computer 4 prepares control information indicating a reception request in preparation for reception. Prepared in the main storage device 43.

次に、計算機結合装置1での処理について述べ
る。
Next, the processing in the computer coupling device 1 will be described.

まず、スイツチマトリツクス2を切換えて、電
子計算機3の記憶制御装置32を接続し、この記
憶制御装置32に読出し信号を送り、主記憶装置
33から制御情報を読み出す。このように読み出
された制御情報から受信側電子計算機4を識別
し、該当する記憶制御装置42を接続するために
スイツチマトリツクス2を切換える。
First, the switch matrix 2 is switched, the storage control device 32 of the computer 3 is connected, a read signal is sent to the storage control device 32, and control information is read from the main storage device 33. The receiving computer 4 is identified from the control information thus read out, and the switch matrix 2 is switched in order to connect the corresponding storage control device 42.

次に、送信側電子計算機4の記憶制御装置42
に読出し信号を送り、主記憶装置43から制御情
報を読出す。このようにして、両電子計算機3お
よび4の主記憶装置33および43から読出した
制御情報から、転送する情報が位置する番地と転
送情報量を識別し、転送情報を送信側の電子計算
機3の主記憶装置33から読み出して受信側の電
子計算機4の主記憶装置43へ書込む。
Next, the storage control device 42 of the sending computer 4
The control information is read from the main storage device 43 by sending a read signal to the main storage device 43 . In this way, the address where the information to be transferred and the amount of information to be transferred are identified from the control information read from the main storage devices 33 and 43 of both computers 3 and 4, and the transferred information is transferred to the computer 3 on the sending side. It is read from the main storage device 33 and written to the main storage device 43 of the computer 4 on the receiving side.

情報の転送が終了すると、送信側の主記憶装置
33へ送信完の制御情報を書込むとともに、受信
側の主記憶装置43へ受信完了の制御情報を書込
む。そして、受信側電子計算機4で受信した情報
を処理するために、上述したように、主記憶装置
43から読出された制御情報により指定されたタ
スクを起動可能状態にする。
When the information transfer is completed, control information indicating completion of transmission is written into the main storage device 33 on the sending side, and control information indicating completion of reception is written into the main storage device 43 on the receiving side. Then, in order to process the information received by the receiving computer 4, the task specified by the control information read from the main storage device 43 is made ready for activation, as described above.

第2図は第1図の計算機結合装置1およびスイ
ツチ2の具体的構成の一例を示す。
FIG. 2 shows an example of a specific configuration of the computer coupling device 1 and switch 2 shown in FIG.

計算機結合装置1において、11は汎用演算装
置、12はメモリ、13はデータカウンタ、14
―3および14―4はそれぞれ送信側および受信
側計算機3および4に接続するスイツチマトリツ
クス2を制御するスイツチコントロール、15―
3および15―4はそれぞれ送信側および受信側
制御情報バツフア、16―3および16―4はそ
れぞれ送信側および受信側アドレスバツフア、1
7―3および17―4はそれぞれ送信側および受
信側データバツフアである。
In the computer coupling device 1, 11 is a general-purpose arithmetic unit, 12 is a memory, 13 is a data counter, and 14
-3 and 14-4 are switch controls for controlling the switch matrix 2 connected to the sending and receiving computers 3 and 4, respectively; 15-
3 and 15-4 are transmitting and receiving side control information buffers, respectively; 16-3 and 16-4 are transmitting and receiving side address buffers, respectively;
7-3 and 17-4 are transmitting side and receiving side data buffers, respectively.

また、スイツチマトリツクス2において、SW
1〜SW12はスイツチを示す。
In addition, in switch matrix 2, SW
1 to SW12 indicate switches.

以下、図面によりデータ転送手順を詳細に説明
する。
The data transfer procedure will be explained in detail below with reference to the drawings.

計算機結合装置1では、データを送る記憶制御
装置32に接続するためにスイツチコントロール
14―3にスイツチSW1,2,3,4,5,6
をオンにするビツトをセツトする。
In the computer coupling device 1, switches SW1, 2, 3, 4, 5, 6 are connected to the switch control 14-3 in order to connect to the storage control device 32 that sends data.
Set the bit to turn on.

また、データを受け取る記憶制御装置42に接
続するためにスイツチコントロール14―4にス
イツチSW7,8,9,10,11,12をオン
にするビツトをセツトする。
Further, in order to connect to the storage control device 42 that receives data, a bit is set in the switch control 14-4 to turn on the switches SW7, 8, 9, 10, 11, and 12.

それにより、任意の方向にデータを転送でき
る。また、スイツチSWの組数を増やせば3台以
上の計算機を接続できる。
This allows data to be transferred in any direction. Also, by increasing the number of switch SWs, three or more computers can be connected.

次に、送信側計算機3の主記憶装置33から情
報を読み出す手順につき説明する。
Next, a procedure for reading information from the main storage device 33 of the sending computer 3 will be explained.

送信側アドレスバツフア16―3に主記憶装置
33から読み出すデータのアドレスADDRをセ
ツトし、続いて、送信側制御情報バツフア15―
3に読出し要求のビツトRREQをセツトし、それ
らの信号を記憶制御装置32に送る。
The address ADDR of the data to be read from the main storage device 33 is set in the sending side address buffer 16-3, and then the sending side control information buffer 15-3 is set.
The read request bit RREQ is set to 3 and these signals are sent to the storage controller 32.

記憶制御装置32は、アドレスバツフア16―
3のアドレスADDRを取り込むと応答信号RESP
を返す。この応答信号は、送信側制御情報バツフ
ア15―3の対応するビツトをセツトし、読出し
要求のビツトをリセツトする。
The storage control device 32 has an address buffer 16-
When address 3 ADDR is taken in, response signal RESP is generated.
return it. This response signal sets the corresponding bit of the transmitting side control information buffer 15-3 and resets the bit of the read request.

記憶制御装置32は、アドバンス信号ADVを
送り、主記憶装置33から読み出したデータ
DATAを送信側データバツフア17―3にセツ
トする。
The storage control device 32 sends an advance signal ADV to read the data read from the main storage device 33.
Set DATA to the sending data buffer 17-3.

さらに、受信側計算機4の主記憶装置43へ情
報を書込む手順につき説明する。
Furthermore, a procedure for writing information to the main storage device 43 of the receiving computer 4 will be explained.

計算機結合装置1の汎用演算装置11は、受信
側データバツフア17―4にデータをセツトす
る。次に、受信側アドレスバツフア16―4に主
記憶装置43へ書き出すデータのアドレス
ADDRをセツトし、続いて、受信側制御情報バ
ツフア15―4に書込み要求のビツトWREQを
セツトし、それらの信号を記憶制御装置43へ送
る。記憶制御装置43は、データDATAとアド
レスADDRを取り込むと応答信号RESPを返す。
この応答信号は、受信側制御情報バツフア15―
4の対応するビツトをセツトし、書込み要求のビ
ツトをリセツトする。
The general purpose arithmetic unit 11 of the computer coupling device 1 sets data in the receiving side data buffer 17-4. Next, the address of the data to be written to the main storage device 43 is stored in the receiving side address buffer 16-4.
ADDR is set, and then the write request bit WREQ is set in the receiving side control information buffer 15-4, and these signals are sent to the storage control device 43. When the storage control device 43 takes in the data DATA and address ADDR, it returns a response signal RESP.
This response signal is sent to the receiving side control information buffer 15-
4 and resets the write request bit.

上述した実施例からも解るように、本発明によ
れば次のような効果が得られる。
As can be seen from the embodiments described above, the following effects can be obtained according to the present invention.

(1) データ転送は、計算機結合装置が各計算機と
独立に行なうので、送受信計算機では、データ
転送の同期をとることを目的とした割込み処理
が不要である。
(1) Data transfer is performed by the computer coupling device independently of each computer, so there is no need for interrupt processing for the purpose of synchronizing data transfer in the transmitting and receiving computers.

(2) データ転送終了後、送受信計算機は通信完了
処理が不要である。
(2) After the data transfer is completed, the sending and receiving computers do not need to perform communication completion processing.

【図面の簡単な説明】[Brief explanation of the drawing]

第1図は本発明による計算機間データ転送方式
を実現する装置の一実施例の構成図、第2図は第
1図の具体的構成の一例の構成図である。 1……計算機結合装置、2……スイツチ、3,
4……電子計算機、33,43……主記憶装置。
FIG. 1 is a block diagram of an embodiment of a device for realizing an inter-computer data transfer system according to the present invention, and FIG. 2 is a block diagram of an example of the specific structure of FIG. 1... Computer coupling device, 2... Switch, 3,
4...Electronic computer, 33,43...Main storage device.

Claims (1)

【特許請求の範囲】[Claims] 1 それぞれ記憶制御装置を有する複数個の電子
計算機用でデータ転送を行う装置であつて、デー
タ転送を制御する制御手段と、上記複数個の電子
計算機の記憶装置のそれぞれと上記制御手段とを
スイツチを介して結合される制御線及びデータ線
を有するスイツチ手段とを有し、かつ上記制御手
段が汎用演算装置と上記汎用演算装置の動作に基
き上記スイツチを開閉するスイツチコントロール
部と上記スイツチ手段を介して、データを転送す
べき上記電子計算機の送受信制御情報およびアド
レスをとり込む送受信制御情報バツフアおよび送
受信アドレスバツフアとを有してなり、データ転
送すべき送信側電子計算機の記憶装置からのデー
タを上記スイツチ手段および上記制御手段を介し
て受信側計算機の記憶装置に転送することを特徴
とする電子計算機間のデータ転送方式。
1 A device for transferring data for a plurality of computers each having a storage control device, the device comprising: a control means for controlling data transfer; and a switch between each of the storage devices of the plurality of computers and the control means. a switch means having a control line and a data line coupled to each other via a general-purpose arithmetic unit; a transmitting/receiving control information buffer and a transmitting/receiving address buffer for taking in the transmitting/receiving control information and address of the computer to which the data is to be transferred, through which the data is transferred from the storage device of the transmitting computer to which the data is to be transferred; A data transfer method between computers, characterized in that the data is transferred to a storage device of a receiving computer via the switch means and the control means.
JP575780A 1980-01-23 1980-01-23 Data transmission system between electronic computers Granted JPS56103753A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP575780A JPS56103753A (en) 1980-01-23 1980-01-23 Data transmission system between electronic computers

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP575780A JPS56103753A (en) 1980-01-23 1980-01-23 Data transmission system between electronic computers

Publications (2)

Publication Number Publication Date
JPS56103753A JPS56103753A (en) 1981-08-19
JPS636893B2 true JPS636893B2 (en) 1988-02-12

Family

ID=11619984

Family Applications (1)

Application Number Title Priority Date Filing Date
JP575780A Granted JPS56103753A (en) 1980-01-23 1980-01-23 Data transmission system between electronic computers

Country Status (1)

Country Link
JP (1) JPS56103753A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
GB2565005B (en) * 2016-05-17 2022-07-06 Nec Corp Analysis device, analysis method, and storage medium storing program

Families Citing this family (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5848160A (en) * 1981-09-16 1983-03-22 Nec Corp Multiprocessor system
JPS5848159A (en) * 1981-09-16 1983-03-22 Nec Corp Multiprocessor system
JPS5848158A (en) * 1981-09-16 1983-03-22 Nec Corp Multiprocessor system
FR2531827A1 (en) * 1982-08-13 1984-02-17 Irlande Jean Paul DEVICE FOR CONTROLLING FILE TRANSFERS BETWEEN COMPUTERS
FI78995C (en) * 1988-02-17 1989-10-10 Valtion Teknillinen Distributed wiring system.
JP2575557B2 (en) * 1990-11-13 1997-01-29 インターナショナル・ビジネス・マシーンズ・コーポレイション Super computer system

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5326638A (en) * 1976-08-25 1978-03-11 Toko Inc Multiiinput data processor
JPS5425136A (en) * 1977-07-28 1979-02-24 Ibm Interrchannel adapter
JPS54129942A (en) * 1978-03-31 1979-10-08 Fujitsu Ltd Direct transfer system between sub-systems

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5326638A (en) * 1976-08-25 1978-03-11 Toko Inc Multiiinput data processor
JPS5425136A (en) * 1977-07-28 1979-02-24 Ibm Interrchannel adapter
JPS54129942A (en) * 1978-03-31 1979-10-08 Fujitsu Ltd Direct transfer system between sub-systems

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
GB2565005B (en) * 2016-05-17 2022-07-06 Nec Corp Analysis device, analysis method, and storage medium storing program

Also Published As

Publication number Publication date
JPS56103753A (en) 1981-08-19

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