JP3463845B2 - Data transmission control device - Google Patents

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a network system of a cyclic communication system in which each node such as a computer connected via a communication line holds common data, and in particular, each common memory The present invention relates to a data transmission control device capable of guaranteeing simultaneity of transmission information in blocks, that is, making common memory of each station the same.

[0002]

2. Description of the Related Art Cyclic communication is one of communication methods in a computer network system. In this cyclic communication, a common memory (common memory) is interposed between a plurality of computers connected to a network, and the data in the memory in the network control unit of each computer is made to coincide with each other at a constant cycle. Computers can refer to the same data at approximately the same time. In such a system, since the data in the common memory is rewritten at a constant cycle, a response time close to this cycle can be obtained and the response time can be shortened. Further, since the access to the common memory is performed by a read command and a write command on the program, there is no overhead of communication control software and the like, and the load on the computer can be greatly reduced.

As a conventional technique of a system using cyclic communication, for example, there is one disclosed in Japanese Patent Publication No. 64-8501. This prior art device is composed of a transmission control circuit that interfaces with a bus, a transmission control processor that controls the interface, a timer, a common memory, and the like, and the processor uses the timer to circulate the transmission right. If the transmission right is monitored within a limited time determined in advance, the transmission control circuit broadcasts its own information in the common memory to other stations (broadcast communication: br
When a frame from another station is received, the data is stored in the area corresponding to the transmitting station in the common memory so that multiple stations share the same information.

A conventional data transmission control device will be described below with reference to the drawings. FIG. 9 is a block diagram showing a configuration example of a data communication system using a conventional data transmission control device. The station 1 is connected to the transmission line 4 and can perform data transmission with another processing device (not shown) connected to the transmission line 4. The station 1 is configured to include a computer processing device 2 and a data transmission control device 3. Further, the data transmission control device 3 comprises a processing device interface means 5, a common memory 6, and a transmission path access means 7.

FIG. 10 shows an example of the state of the memory space of the common memory 6. The common memory 6 comprises a transmission area 6a and a reception area 6b. Figure 9
The operation of the data communication system using the conventional data transmission control device 3 will be described with reference to FIG. When the processing device 2 tries to update the unique information of its own station (processing device 2) in another processing device connected to the data transmission path 4, first, the processing device 2 stores in the common memory 6 of the data transmission control device 3. The unique information of the own station is written in the transmission area 6a. The unique information of the own station written in the transmission area 6a is broadcasted at regular intervals (hereinafter, referred to as "transfer cycle"). The station that has received the unique information of the processing device 2 stores it in the corresponding area. Such a data transfer operation is performed independently of the operation on the processing device side, and the processing device is the common memory 6 of the data transmission control device 3.
Only by writing the unique information of its own station in the transmitting area 6a of 1, the unique information of its own station is transferred to the receiving area of the common memory which can be referred to by other processing devices and which is defined for the transmitting station. The other processing device is the reception area 6 of the common memory 6.
The output data of the processing device can be received by reading b when necessary. A similar technique is disclosed in Japanese Patent Laid-Open No.
There is a CPU output data control circuit disclosed in Japanese Patent Laid-Open No. 101538. This configuration is for writing and reading
A plane transmission memory is provided, and time division communication is performed by switching and using these. The plane transmission memory is used as a so-called alternation buffer.

[0006]

However, in the prior art using the common memory and the alternate buffer, the operation of broadcasting the data in the transmission area in the common memory to other data transmission control devices is performed by the processing device. Since the processing is performed independently of the operation, the data transmission control device writes the unique information of its own station in the transmission area while the processing device is writing the unique information of its own station with a certain capacity in the transmission area of the common memory. If it is time to send information to another station, the speed of access from the processing device to the common memory and the speed at which the data transmission control device sends data are different. There is a problem that the data is transferred to another processing device before the update of the unique information of the own station is completed.

That is, the problem shown in FIG. 11 arises. As shown in (a), the memory for transmission 101 and the memory for transmission 102 are provided, and the data A is updated in the area designated by the CPU 103 in the memory for transmission 101. At this time, the transmission memory 102 is connected to the transmission path 4. After the update of the data A is completed, the transmission memory 101 and the transmission memory 102 are switched as shown in (b). In (b), the CPU 103 updates the data B in the designated area in the transmission memory 102. At this time, when the common memory is switched to the state of (a) again without data transmission from the transmission memory 101, the contents of the transmission memory 101 (data A) are changed as shown in (c). Has not been transferred to the transmission memory 102 (processing for storing the same data in another memory), the updated data and the last updated data A ′ are transmitted from the transmission memory 2 to the transmission path 4. There is a problem that That is, although the data A has been updated, the contents of the last update will be transmitted. For this reason, in the cyclic communication, the simultaneity of data is guaranteed only in the unit of data update from the processing device, and there is no guarantee that the data at the preceding and following addresses are at the same time. Therefore, no special consideration is required when handling information in units of data updates from the processor, but when handling multiple data as blocks, for example, the software adds check data to the beginning and end of the data. , It is necessary to process the data after confirming that all data is completely prepared on the receiving side.

Furthermore, when the data in the transmission area is broadcast-transmitted to other stations after the update of the unique information of the own station from the processing device to the transmission area of the common memory is completed, the received data is transmitted to the common memory. When the processing device connected to the receiving station reads the transmission area of the common memory during writing in the area, the processing device receiving the data cannot receive all the updated unique information of the own station.

An object of the present invention is to provide a data transmission control device capable of guaranteeing the simultaneity of transmission / reception data in each data block of the common memory by preventing the processing device side and the transmission line side from accessing the common memory at the same time. To do.

[0010]

According to the present invention, one station is constituted by a combination of a processing device for executing a writing and reading process and a transmission line access means for controlling an interface to the transmission line, and the station is connected via the transmission line. In a data transmission control device for exchanging data with another station, two common memories each having a transmission area in which unique information is written by the processing device and a reception area for receiving data from another station; Transmission path access means for controlling the interface to the communication path, common memory switching means for switching the connection destination of each of the common memories to the transmission path access means and the processing device, and processing connected to the common memory switching means and the processing device The common memory switching device is provided with a device interface means. Comprises a buffer connected to each of said common memory in order to store the address and data contents written in the writing to the common memory connected to the processor interface means side,
After the transmission from the common memory connected to the transmission line access means side to the transmission line is completed, data is written from the buffer to a predetermined address of the non-writing common memory, and the common memory for transmission and reception is stored. Disclosed is a data transmission control device characterized by matching the contents.

According to this construction, each of the two (two) common memories has a transmission area and a reception area, and is connected to the common memory connected to the processor interface means side and to the transmission path access means side. Two common memories are switched by the common memory switching unit in response to the completion of writing the unique information to the common memory connected to the processing device interface unit side. As a result, it is possible to prevent the data transfer to the common memory while writing the unique information to the common memory connected to the processor interface means side, and to guarantee the simultaneity of the data.

[0012]

BEST MODE FOR CARRYING OUT THE INVENTION Embodiments of the present invention will be described below with reference to the drawings. FIG. 1 is a block diagram showing an embodiment of a data transmission control device of the present invention and a configuration of a data communication system using the same. The data transmission control device 13 according to the present invention includes a processing device interface means 5 and a transmission line access means 7 having the same configuration as the conventional one, common memories 8 and 9, and the common memories 8 and 9.
Write buffer 10,1 connected to
1, common memory 8 and 9 and write buffer 10 (WB
1), 11 (WB2) and a common memory switching means 12 connected to the processor interface means 5 are added.

FIG. 2 is an explanatory diagram showing usage divisions of the memory spaces of the common memories 8 and 9. As shown in FIG. 2, the common memory 8 (first common memory) is a transmission area 8a.
And a receiving area 8b, and the common memory 9 (second common memory) includes a transmitting area 9a and a receiving area 9b.

FIG. 3 is an explanatory view showing the principle of memory transfer in the common memories 8 and 9. Here, a system in which data is transmitted and received among three stations (station 1, station 2, station 3) and each station includes a number of common memories (A, B, C) corresponding to the number of stations is illustrated. ing. The common memory A corresponds to the common memory 8 and the common memories B and C correspond to the common memory 9. Further, the controller corresponds to a configuration including the common memory switching unit 12 and the write buffer.

The common memory A is written by the controller A, the common memory B is written by the controller B, and the common memory C is written by the controller C. Therefore, in the own station, the common memory A is used for transmitting to the common memories B and C of other stations, and the common memories B and C are used for writing the received data from other stations. For example, the data written in the common memory A of the station 1 is transmitted to the transmission path 4 by being periodically broadcast.
The stations 2 and 3 receive the data transmitted from the other stations through the transmission path 4 and store it in the corresponding area of the common memory within a fixed time. This processing means that the common memory of each of the stations 1 to 3 holds the data of the same content, that is, the simultaneity of the data is obtained. The data reference from the controller can be devoted to simple memory read / write processing that is not conscious of communication, and as a result, responsiveness can be improved.

In the configuration of FIG. 3, switching of the common memory A and the common memories B and C by the controller of the own station is performed, for example, by connecting the common memory A to the transmission line 4 and connecting the common memories B and C to the controller side. If so, the common memory A is switched from the transmission line 4 to the controller side, and the common memories B and C are switched from the controller side to the transmission line 4.

Next, the operation of the data communication system using the data transmission control device 13 of the present invention will be described with reference to FIGS. 1 and 2. By the common memory switching means 10, the connection destination of the common memory 8 is switched from the data transmission path 4 side to the processing device 2 side, and the common memory 9 is switched from the processing device 2 side to the transmission path 4 side. In this connection state, transmission data is read from the transmission area 9a of the common memory 9 for each transfer cycle and transmitted to the processing device of another station (not shown) via the data transmission path 4. here,
A case will be described in which the unique information of its own station is generated in the processing device 2 and writing is performed in the common memory of the data transmission control device 13. The processing device 2 executes writing to the common memory 8. The data transfer process from the station 1 to another station while the writing of the unique information of the own station from the processing device 2 to the common memory 8 is not completed, the common memory 9 disconnected from the processing device 2 and connected to the transmission line 4 is connected. Is performed using.
Then, when the writing of the unique information of the own station is completed,
The common memory switching means 12 switches between the common memory 8 connected to the processing device 2 side and the common memory 9 connected to the data transmission path 4 side, and the common memory 8 passes through the common memory switching means 12. Is connected to the transmission line access means 7, and the common memory 9 is connected to the processing device 2 side.

As described above, during writing in one common memory, data simultaneity is guaranteed by reading from the other common memory. That is, data transfer (reading) of the common memory 8 does not occur while the processing device 2 is writing to the common memory 8, and the simultaneity of data can be guaranteed. Or later,
Data simultaneity is guaranteed by switching the common memory connected to the processing device 2 side and the common memory connected to the data transmission line 4 side. However, when the two common memories are switched and used, there is a problem that the contents of the two common memories become inconsistent unless the contents of the two common memories are matched before the switching occurs. That is, in FIG. 2, the transmission area 8 is set by the processing device 2.
When the common memory 8 connected to the processor interface means 5 side and the common memory 9 connected to the transmission path access means 7 side are switched after the area 81 of a is updated, the data end update of the common memory 9 is performed. Since the data is not updated in the area 91, the mismatch of contents occurs between the common memory 8 and the common memory 9 after switching the common memory.

In order to solve this problem, the write buffers 10 and 11 are used in the present invention. That is, the write buffer 11 (WB2) is interposed between the common memory switching unit 10 and the common memory 9 to update the contents of the common memory 8 connected to the processing device interface unit 5 side from the processing device 2 and at the same time. The content address and data are held in the write buffer 11. Then, after the transmission from the area 91 of the common memory 9 connected to the transmission path access means 7 side to the data transmission path 4 is completed, the data in the area 91 of the common memory 9 is updated by the write buffer 11, and the common memory 8 And the contents of the common memory 9 are matched. After that, the common memory switching means 12 switches between the common memory 8 connected to the processing device interface means 5 side and the common memory 9 connected to the transmission path access means 7 side. This can prevent the contents of the two common memories from becoming inconsistent.

When the common memory 9 is connected to the processor interface means 5 side and the common memory 8 is connected to the transmission path access means 7 side, the common memory 9 is connected.
At the same time that the contents of the above are updated, the address and data of the updated contents are held in the write buffer 10, and thereafter, by performing the same processing as described above, it is possible to prevent inconsistency between the contents of the two common memories.

The above description is about the case where the unique information of the own station is written in the transmission area, but it is determined that the unique information is received from another station other than the station 1 and corresponds to the transmitting station in the common memory. The case of storing the reception specific information in the area can be similarly explained. That is, when the station 1 receives the unique information from another station, the common memory switching means 12 connects the common memory 8 and the processing device 2 and separates the connection between the common memory 8 and the data transmission path 4. On the other hand, the common memory 9 is separated from the processing device 2 side by the common memory switching means 10 and is connected to the transmission path access means 7. The unique information received via the data transmission path 4 and the transmission path access means 7 for each transfer cycle is stored in the area 9b of the common memory 9 defined for the transmitting station.

Further, the processing device 2 is the data transmission control device 1
When reading the received data from the other station from the common memory of No. 3, the processing device 2 reads the received data from the common memory 8. At this time, the reception of data from another station is performed by using the common memory 9 which is separated from the processing device 2 side and connected to the transmission path 4 side until the reading from the common memory 8 to the processing device 2 is completed. Done. Then, when the reading of the unique information of the other station from the common memory 8 is completed, the common memory switching means 12 switches between the common memory 8 and the common memory 9, and the common memory 8 is connected to the data transmission path 4 side. , The common memory 9 is connected to the processing device 2 side. In this state, the processing device 2
Is performing read processing on the common memory 9,
Data reception (writing) is not performed to the common memory 8, and data simultaneity is guaranteed. Or later,
By performing the operation of switching the common memory connected to the processing device 2 side and the common memory connected to the data transmission path 4 side, the simultaneity of data is always guaranteed.

FIG. 4 is a block diagram showing the detailed structure of the common memory switching means 12. In the figure, 14 is a data transmission control device bus connected to the processing device interface means 5 and the transmission path access means 7, and 15 is a communication controller MPU connected to the data transmission control device bus 14.
(Micro Processing Unit), 16 is a timer connected to the data transmission control device bus 14, and 17 is a DMA (Direct Memory) connected to the data transmission control device bus 14.
Access) controller, 18 is a transmission / reception buffer memory connected to the data transmission control device bus 14, 19 is a first selector connected to the data transmission control device bus 14, and 20 is the data transmission control device bus 14 and A second selector connected to each common memory, 21 is a first access detection circuit connected to the common memory 8 and the selector 19, and 22 is a second access detection circuit connected to the common memory 9 and the selector 19. is there. These 15-22
Are installed in the data transmission control device 13. Since the other members are the same as those shown in FIG. 1, the description thereof will be omitted.

Next, the operation of the common memory switching means 12 of FIG. 4 will be described. MPU15 for communication controller
Sends a transfer command to the DMA controller 17 at regular intervals based on the output of the timer 16. The DMA controller 17 transfers the transmission data from the common memory 8 or the common memory 9 to the transmission / reception buffer memory 18, and at this time, the common memory 9 is selected by the selector 20. When the transmission data is written from the common memory 9 to the transmission / reception buffer memory 18, the communication controller M
A response signal is returned to PU15. The transmission data written in the transmission / reception buffer memory 18 from the common memory 9 is further transmitted to the data transmission line 4 through the transmission line access means 7. While the unique information of the own station is not updated from the processing device 2, the data is periodically transmitted from the common memory 9 to the data transmission line 4 as described above. On the other hand, when the unique information of the own station is newly generated in the processing device 2, the processing device 2 writes the unique information of the own station in the common memory 8 or the common memory 9. In this case, the selector 19
The common memory 8 is selected by.

As described above, the common memory switching means 12 can separately switch between the common memory connected to the processor interface means 5 side and the common memory connected to the transmission path access means 7. Next, some of the methods of detecting the start and end of writing when the processing device 2 writes the unique information of its own station in the common memory 8,
This will be described with reference to the flowcharts of FIGS. First, the first method will be described based on the flowchart of FIG. First, when there is a write from the processing device 2 to the address of the transmission area of the common memory 8 or 9 (step S501), the timer 16 starts counting (step S502). Then, before the preset time is reached for another address of the common memory 8, the timer 16
While the count value of is written (step S50
3) It is assumed that the processing device 2 is writing the unique information of its own station (step S504), and the writing is terminated when there is no access even if the preset time is reached.
This set time depends on the RAM (Ra
It is set to be longer than the access time of ndom Access Memory). For example, it is determined by measuring the access time. After that, the write buffer 10 or 11 updates the data in the common memory connected to the transmission path access unit 7 side to make the data in the two common memories match (step S505). After that, the common memory switching means 12 switches between the common memory 8 and the common memory 9 (step S506).

The flowchart of FIG. 6 shows a second method of detecting the start and end of writing the unique information of the own station. Unique information of its own station is generated (step S601),
At the end of writing the unique information of its own station to the common memory 8 connected to the processing device interface means 5,
A flag (not shown) provided in the data transmission control device 13 (accessible from the processing device and the data transmission control device side) is set to indicate the end of writing (step S602). After checking this flag, it is determined whether or not communication is being performed on the common memory 9 side (step S603). If communication is being performed on the common memory 9 side, the contents of the common memory 8 and the common memory 9 are matched (step S604). After that, the common memory switching means 12 switches between the common memory 8 and the common memory 9 (step S605).

The flowchart of FIG. 7 shows a third method of detecting the start and end of writing the unique information of the own station. Unique information of its own station is generated (step S701),
The access of a specific address (here, the final address) in the transmission area 8a in the common memory 8 connected to the processing device interface means 5 is monitored (step S702), and the specific address is accessed. Writing ends at the time. Further, it is determined whether or not communication is performed on the common memory 9 side (step S703). If communication is not being performed, the common memory switching means 12 switches between the common memory 8 and the common memory 9 (step S704).

Further, FIG. 8 shows a fourth method of detecting the start and end of writing the unique information of the own station. Unique information of its own station is generated (step S801), and access to all addresses in the common memory 8 connected to the processor interface means 5 is monitored (step S80).
2). When it is determined in step S802 that there is an access, the writing ends at that point. Further, it is determined whether or not communication is being performed on the common memory 9 side (step S803). If there is no communication,
The common memory switching means 12 switches between the common memory 8 and the common memory 9 (step S80).
4).

As described above, the start and end of writing the unique information of the own station is detected by the method described above. In this way, the common memory switching unit 12 can know the timing of switching the common memory by detecting the writing and the end of the unique information.

Next, the operation of FIG. 4 after the writing of the unique information of the own station from the processing device 2 to the common memory 8 is completed will be described. The common memory switching means 10 (i) finishes writing the unique information of its own station to the common memory 8, and (ii) finishes writing the transmission data from the common memory 9 to the transmission / reception buffer memory 18, When the two conditions when the response signal is returned to the communication controller MPU 15 are satisfied, the common memory switching unit 1
Reference numeral 2 executes switching between the common memory 8 connected to the processing device 2 side and the common memory 9 connected to the data transmission line 4 side. After this switching, the common memory 8 is connected to the data transmission line 4 side, and the common memory 9 is connected to the processing device 2 side. After that, the transmission data is written from the common memory 8 to the transmission / reception buffer memory 18 at regular intervals. This transmission data is sent to the data transmission line 4 via the transmission line access means 7. When the unique information of its own station is newly generated in the processing device 2, the common memory 9 is selected by the common memory switching means 10, and the processing device 2 writes the unique information of its own station in the common memory 9.

[0031]

As described above, according to the present invention, since the common memory has two surfaces and the common memory switching means for switching between these surfaces is provided, the unique information can be stored in the common memory connected to the processing device interface means. Data is not transferred to the common memory during writing, and the simultaneity of transmission information can be guaranteed in each block of the common memory in cyclic communication.

[Brief description of drawings]

FIG. 1 is an embodiment of a data transmission control device of the present invention,
It is a block diagram which shows the structure of the data communication system using this.

FIG. 2 is an explanatory diagram showing usage divisions of a memory space of a common memory according to the present invention.

FIG. 3 is an explanatory diagram showing the principle of memory transfer in the common memory according to the present invention.

FIG. 4 is a block diagram showing a detailed configuration of common memory switching means according to the present invention.

FIG. 5 is a flowchart showing a first example of a writing start and end detection method when the processing device writes its own unique information in the common memory.

FIG. 6 is a flowchart showing a second example of a writing start and end detection method when the processing device writes the unique information of its own station in the common memory.

FIG. 7 is a flowchart showing a third example of a writing start and end detection method when the processing device writes the unique information of its own station in the common memory.

FIG. 8 is a flowchart showing a fourth example of the method of detecting the start and end of writing when the processing device writes the unique information of its own station in the common memory.

FIG. 9 is a block diagram showing a configuration example of a data communication system using a conventional data transmission control device.

10 is an explanatory diagram showing a state of a memory space of the common memory in FIG. 9. FIG.

FIG. 11 is an explanatory diagram showing transmission of end update data when the replacement buffer is applied to cyclic communication.

[Explanation of symbols]

1 station 2 processing equipment 4 transmission lines 5 Processor interface means 7 Transmission line access means 8, 9 common memory 8a, 9a transmission area 8b, b reception area 10,11 write buffer 12 Common memory switching means 13 Data transmission control device

─────────────────────────────────────────────────── --- Continuation of front page (56) References JP-A-5-22307 (JP, A) JP-A-2-77935 (JP, A) JP-A-4-101538 (JP, A) JP-B 8- 2057 (JP, B2) (58) Fields investigated (Int.Cl. ⁷ , DB name) H04L 13/08

Claims (6)

(57) [Claims] 1. A single station is configured by a combination of a processing device that executes write and read processing and a transmission path access unit that controls an interface to the transmission path, and data is exchanged with another station via the transmission path. In the data transmission control device, two common memories each having a transmission area in which unique information is written by the processing device and a reception area for receiving data from another station, and a transmission path access that controls the interface to the transmission path Means, a common memory switching means for switching each connection destination of the common memory to the transmission path access means and the processing device, and a processing device interface means connected to the common memory switching means and the processing device, The common memory switching means is the processing device interface. The common connected to the transmission path access means side, including a buffer connected to each of the common memories for storing the address and data of the write contents at the time of writing to the common memory connected to the face means side. After the transmission from the memory to the transmission path is completed, data is written from the buffer to a predetermined address of the common memory that is not being written, and the contents of the common memory for transmission and the common memory for reception are matched. apparatus. 2. The common memory switching means controls so that the processing device interface means and the transmission line access means are not simultaneously accessed to the same block of the common memory connected to the processing device interface means side. Further, when the common memory connected to the processing device interface means side is updated, the data of the same block of the common memory on the processing device side and the common memory on the transmission line side is updated before switching the connection of the common memory. The data transmission control device according to claim 1, which is performed. 3. The common memory switching means does not access another address of the common memory within a predetermined time from the access to the common memory connected to the processing device interface means side, 3. The data transmission according to claim 2, wherein the data update of the same block is executed on condition that the transmission from the common memory connected to the transmission path access means side to the transmission path is not being executed. Control device. 4. The common memory switching means sets a write end flag in a register at the end of writing the unique information by the processing device to the common memory connected to the processing device interface means side, and
3. The data transmission according to claim 2, wherein the data update of the same block is executed on condition that communication from the common memory connected to the transmission path access means side to the common transmission path is not being executed. Control device. 5. The common memory switching means has access to a specific address of the common memory connected to the processing device interface means side, and
3. The data transmission control according to claim 2, wherein the data update of the same block is executed on condition that communication from the common memory connected to the transmission path access means side to the transmission path is not being executed. apparatus. 6. The common memory switching means has access to all addresses of a transmission block of the common memory, and communication from the common memory connected to the transmission path access means side to the transmission path is possible. The data transmission control device according to claim 2, wherein the data update of the same block is executed on condition that it is not being executed.