JPH1011353A - Data transmission equipment - Google Patents

Abstract

PROBLEM TO BE SOLVED: To prevent a communication arithmetic part from reading out data which are stored in a memory while a arithmetic part are recording data in the memory. SOLUTION: Data from a sequence processing part 1 are recorded in a sequence buffer in a dual-port memory 2 and the communication processing part 3 reads data out of a communication buffer in the memory 2. An address switching circuit 4 exchanges the address of the sequence buffer with the address of an intermediate buffer in the memory 2 after finishing recording the data in the sequence buffer. Further, an address switching circuit 4 exchanges the addresses of the communication buffer and intermediate buffer, but performs the address exchanging between the communication buffer and intermediate buffer only when the address exchanging between the sequence buffer and intermediate buffer is performed after last exchanging is done.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention belongs to the technical field of data transfer in a control arithmetic unit or the like.

[0002]

2. Description of the Related Art FIG. 4 shows a configuration of a sequencer remote I / O system for transferring an operation result of a sequence operation process to a remote I / O system. In the figure,
The sequence processing unit 01 is a device that performs a control operation according to a predetermined procedure, and data of the operation result is sequentially recorded in the dual port memory 02. The communication processing unit 03 reads data recorded in the dual port memory 02,
The data is transmitted to the remote I / O 05 connected to the control target or the like.

In the apparatus, a sequence processing unit 01
Every time a predetermined operation is performed, the data of the operation result is sequentially overwritten and recorded in the dual port memory 02, and the communication processing unit 03 reads and records the data recorded in the dual port memory 02 at regular time intervals. Sending.

[0004]

As described above, in the conventional sequencer remote I / O system, while the sequence processing unit 01 is recording data in the dual port memory 02, the data is recorded in the dual port memory 02. The contents may be read out by the communication processing unit 03, and correct data may not be transmitted to the remote I / O05.

[0005]

In order to solve the above-mentioned problems, the present invention provides a first memory area for recording data from an arithmetic processing unit and a second memory area for storing data to be sent to an external device.
And the third relaying between the two memory areas
Memory device having the following memory area, a communication processing device for transmitting data recorded in the second memory area in the memory device to an external device, and completion of data transmission from the arithmetic processing device to the first memory area Then, an address exchange circuit for exchanging addresses or contents of the first memory area and the third memory area and exchanging addresses or contents of the second memory area and the third memory area at a desired timing is provided. It is characterized by having.

[0006]

1 to 3 show an embodiment of a sequencer remote I / O system according to the present invention. In this embodiment, the dual port memory 2 has 3
It is divided into two areas. In these three memory areas, there are buffers called a sequence buffer, a communication buffer, and an intermediate buffer. The sequence buffer is a buffer for writing the data of the operation result in the sequence processing unit 1, the communication buffer is a buffer for the communication processing unit 3 to read out data, and the intermediate buffer is a relay between the two buffers. This is a buffer for performing

In FIG. 1, the sequence processing unit 1 overwrites the operation result data in a sequence buffer in the dual port memory 2 every time a predetermined operation is performed.
Then, every time the writing of data to the buffer is completed, a sequence buffer update command 10 is transmitted to the address switching circuit 4.

On the other hand, the communication processing unit 3 sends a communication buffer update command 11 to the address switching circuit 4 at regular time intervals.
And reads the data recorded in the communication buffer.

When the address switching circuit 4 receives the sequence buffer update command 10 from the sequence processing section 1 or the communication buffer update command 11 from the communication processing section 3, it operates as follows. (1) When the sequence buffer update command 10 is received, a flag indicating that the command has been received is set, and the address of the sequence buffer in the dual port memory 2 and the address of the intermediate buffer are exchanged. (2) When the communication buffer update command 11 is received, whether or not the flag of (1) is set, that is, the address exchange of (1) is performed after the previous communication buffer update command 11 is received. Check if the flag is on, exchange the address of the intermediate buffer with the address of the communication buffer, and lower the flag. If the flag is not on, exchange both addresses and do not exchange the current address. To maintain.

FIG. 2 shows an example of the configuration of the address switching circuit 4. In the figure, the state holding circuit 22 determines whether or not the information of the existing area of each buffer in the dual port memory 2 and the address of the intermediate buffer after address exchange with the sequence buffer have been exchanged with the communication buffer (the flag is set). If the flag is not set, it means that the exchange is being performed).

When a sequence buffer update command 10 or a communication buffer update command 11 is transmitted to the address switching circuit 4, the state switching circuit 21 determines the held information based on the command and the current information held in the state holding circuit 22. To update. Then, the updated held information is sent to the address generation circuit 23. The address generation circuit 23 assigns the address of the memory area newly allocated to the sequence buffer or the communication buffer (that is, the address of the memory area previously allocated to the intermediate buffer) to the dual port memory 2 according to the information held by the state holding circuit 22. Send to

FIG. 3A shows the allocation state of each buffer in the dual port memory 2. The figure shows
When each area obtained by dividing the dual port memory 2 into three is defined as a memory area A, a memory area B, and a memory area C, a total of 6 patterns of the allocation state of the sequence buffer, the intermediate buffer, and the communication buffer are provided for these memory areas.
Indicates that there is a type. For example, when the memory area A is an area that can be allocated to the intermediate buffer, the memory area B is an area that can be allocated to the communication buffer, and the memory area C is an area that can be allocated to the sequence buffer, the allocation state number “5” is assigned. It is in the state.

FIG. 3B shows how the contents of the state holding circuit 22 in the address switching circuit 4 transition for each allocation state in the dual port memory 2 shown in FIG. 3A. Is shown. From the figure,
For example, when the sequence buffer update command 10 is issued in a state where the allocation state number is “5” and the flag is not set, the state changes to a state where the flag is set in the allocation state number “6”, and then the communication buffer is set. Update command 1
When 1 is output, it can be seen that the state transitions to a state in which the flag is not set at the allocation state number “1”.

If the communication buffer update command 11 is issued while the flag is not set, the state returns to the same allocation state and flag state as before. This is because there is no point in exchanging the address of the communication buffer with the address of the intermediate buffer where no new data exists. If the sequence buffer update command 10 is issued while the flag is set, that is, while the updated data is stored in the intermediate buffer, the address of the sequence buffer and the intermediate buffer are set while the flag is set. Exchange with the address. This is the communication processing unit 3
In order to satisfy the request to transmit the latest data of the sequence operation result.

[0015]

According to the present invention, the communication processing apparatus can always receive the latest one of the operation result data of the operation processing apparatus accurately. Also,
Since there is no need to synchronize the arithmetic processing unit and the communication processing unit, the above-described effect can be obtained with a relatively simple device configuration.

[Brief description of the drawings]

FIG. 1 is a configuration diagram of a sequencer remote I / O system according to an embodiment of the present invention.

FIG. 2 is a configuration diagram of an address switching circuit of the sequencer remote I / O system of FIG. 1;

FIG. 3 is a state diagram showing a state in which a buffer is allocated to a memory area and a state in which the address of the buffer is exchanged.

FIG. 4 is a configuration diagram of a conventional sequencer remote I / O system.

[Explanation of symbols]

 01, 1 Sequence processing unit 02, 2 Dual port memory 03, 3 Communication processing unit 4 Address switching circuit 05, 5 Remote I / O device 10 Sequence buffer update command 11 Communication buffer update command 12 Sequence buffer address 13 Communication buffer address 015, 15 Data 21 State switching circuit 22 State holding circuit 23 Address generation circuit

Claims (1)

[Claims] 1. A first memory area for recording data from an arithmetic processing unit, and a second memory area for storing data to be sent to an external device.
And the third relaying between the two memory areas
Memory device having the following memory area, a communication processing device for transmitting data recorded in the second memory area in the memory device to an external device, and completion of data transmission from the arithmetic processing device to the first memory area And an address exchange circuit for exchanging addresses or contents of the first memory area and the third memory area and exchanging addresses or contents of the second memory area and the third memory area at a desired timing. A data transmission device, comprising: