JP2505298B2 - Variable bus width designation method and variable bus width information reception method in split bus - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION [Table of Contents] [Outline] [Industrial Fields of Application] [Prior Art] Diagram for explaining bus width information transfer in a conventional non-split bus (FIG. 8) In a conventional split bus (FIG. 9) for explaining bus width information transfer of the present invention [Problems to be solved by the invention] [Means for solving the problem] [Operation] FIG. Detailed view of the essential part of the present invention in the circuit (3rd
Fig.) Detailed view of answer creation unit (Fig. 4) Fig. 2 Diagram showing transmission / reception sequence example in the embodiment (Fig. 5) Diagram showing answer creation timing (Fig. 6) Command and answer format, and reception management FIG. 7 is a diagram showing a write information format in each storage position of the buffer and the transmission management buffer (FIG. 7) [Embodiment] [Effect of the invention] [Outline] Bus width information is returned to an access request source
Say Answer. ), The variable bus width specification method and variable bus width information reception method in the split bus with the purpose of enabling the incorporation of a unit that handles data with an arbitrary data width into the system. In a data processing system for transmitting and receiving information between a plurality of units connected to each other, a bus width information output unit for outputting bus width information within the predetermined bus width to the receiving unit, and a return to the transmitting unit. A bus width information insertion unit for inserting bus width information into an answer is provided, and the answer in which the bus width information output from the bus width information output unit is inserted is returned as an answer to a command from the transmitting user. In addition, a bus width information extraction unit that extracts the bus width information from the received command is provided, and the extracted bus It was constructed as to receive information received subsequent to the command according to the information.

[Industrial applications]

The present invention relates to a variable bus width designation method and a variable bus width information reception method in a split bus that returns bus width information to an access request source together with a transmission / reception result (hereinafter referred to as an answer).

Recently, a multiprocessor system has been adopted as a system for configuring a control unit such as a computer and an electronic exchange, and there is a split bus system as a bus system for constructing the multiprocessor system. This is because it is effective to reduce the bus occupation rate in the multiprocessor system and prevent the performance from deteriorating.

[Conventional technology]

The reason why the bus occupancy ratio can be lowered is as follows.

In a multiprocessor system adopting a conventional bus system that is not a conventional split bus system, while a bus in the system is allowed by a processor and the bus is used, only the processor is allowed to use the bus. Because it is given.

However, the split bus system does not have such a limitation. This is because the single piece of hardware is used at different times for an access request to a processor via a single piece of hardware constituting a bus and an answer to this request. Therefore, it is possible to share a single bus among a plurality of processors and carry out different processing for each processor.

[Problems to be Solved by the Invention]

In any of the above bus systems, a device having a data width different from the bus width specific to the bus (hereinafter, referred to as
It is called a unit. The system may be constructed by connecting 100 _{1 to} 100 _n . The aforementioned processor is connected to this unit. As a hardware configuration that allows such a system configuration, in the conventional bus system, a bus width information line 106 is provided in addition to the data line 102 and the address line 104 as shown in FIG.

When an access is made from a unit of the plurality of units to the other unit via the bus width information line 104, data and address are transferred through the data line 102 and the address line 104. , Bus width information line 106
Bus width information is transferred via. By receiving this bus width information at the receiving unit, the receiving unit can recognize the bus width of the data to be transferred, and the data can be transmitted and received. The bus width information line 106 is also occupied and used similarly to the data line 102 and the address line 104 (see (1), (2) and (3) in FIG. 8).

However, in the split bus system, a single bus (see 103 in FIG. 9) is used in a time-divisional manner as described above. In this system, the command and address (eg, , (1) in FIG. 9
Before the answer (for example, refer to AN in (1) of FIG. 9) is returned to its own unit for C1 and A), the command and address of another unit (for example, C2 in (1) of FIG. 9) And B) are transmitted, there is no control means for permitting transmission / reception of data having a data width different from the bus width of the bus. Therefore, if the conventional split bus system is used as it is, Units with different data width cannot be used.

The present invention has been created in view of such problems,
It is an object of the present invention to provide a variable bus width designation system and a variable bus width reception system in a split bus that enables incorporation of a unit that handles data with an arbitrary data width into a system.

[Means for solving the problem]

FIG. 1 shows a block diagram of the principle of the present invention. As shown in this figure, the first invention (see (A) of FIG. 1) has a plurality of units 4 _i (i = 1, 2,
..., n) in a data processing system for transmitting and receiving information between them, a bus width information output unit 6 for outputting bus width information to the receiving unit, and the bus width information for an answer returned to the transmitting unit. A bus width information insertion unit 8 for inserting bus width information of the output unit 6 is provided, and the bus width information of the bus width information output unit 6 is inserted as an answer to a command received from the transmission unit via the split bus 2. Configured to send back answers.

A second aspect of the invention (see FIG. 1B) is that in the data processing system, the receiving unit is provided with a bus width information extracting unit 7 that extracts bus width information from a received command, and the extracted bus is extracted. It is configured to receive the information received following the command according to the width information. 9
Is an information capturing unit.

[Action]

When the answer to the command received from the transmitting unit via the split bus 2 is returned, the bus width information output unit 6 inserts the bus width information into the answer in the bus width information inserting unit 8 to the transmitting unit. Send it back.

The information received following the command is fetched by the information fetching unit 9 which responds to the bus width information extracted from the command.

Therefore, the receiving unit can recognize the data width received via the split bus 2, and the transmitting unit can recognize the data width received from the receiving unit via the split bus 2. ,
It becomes possible to connect to the split bus 2 a unit that handles data having an arbitrary data width within the data width of the split bus 2.

〔Example〕

FIG. 2 shows an embodiment of the present invention. This embodiment shows an example implemented in the system configuration shown in FIG. Second
The interface circuit 20 shown has the same status in the system as the interface circuit in the unit shown in FIG. The interface circuit 20, the receiver 30, the driver
32, reception register 34, system bus reception management unit 35, reception buffer (RB) 36, reception management buffer (RSB) 38, internal bus interface circuit 40, transmission register 42, transmission buffer (SB) 44, system bus transmission management unit 45 and a transmission management buffer (SSB) 46. The receiver 30 and the driver 32 are connected to the system bus 103, and the driver 48 and the receiver 50 are connected to the internal bus 105. The system bus reception management unit 35 generates a pointer according to the received command, and outputs from the pointer the reception buffer write address of the number of write units necessary for writing the amount of data received from the pointer into the reception buffer 36. A reception management buffer write address which is generated and under the control of the system bus reception management unit 35 is generated. The reception management buffer write address is a value updated by +1 prior to the writing. The formats of commands and answers on the system bus 103 and the format of information written to the storage positions of the reception management buffer 38 and the transmission management buffer 46 are (1) and (2), (3) and (3) of FIG. 7, respectively. It shows in (4).

FIG. 3 is a detailed diagram of a main part of the present invention in the interface circuit 20. The internal bus access control unit 60 receives the data from the reception buffer 36 and outputs each output from the reception management buffer 38, that is, the pointer P and the read / write information R /.
W, bus width information BW, number of bytes BT, source unit number S
U, receive other information ETC. Further, the internal bus access control unit 60 generates a reception buffer read address and a reception management buffer read address in response to the pointer P and sends them to the reception buffer 36 and the reception management buffer 38 to access the internal bus 105. . The internal bus access control unit 60 also responds to the result of access (read or write) to the internal bus 105, and gives an answer creation instruction and byte count.
Output BT and other information ETC.

The answer creating unit 62 that receives the answer creating instruction also receives the bus width information BW and the transmission source unit number SU from the reception management buffer 38. The answer creating unit 62 supplies the data to the transmission buffer 44, while the pointer P, the number of bytes BT, and other information ET are sent to the transmission management buffer 46.
Supply C. The information is written in the corresponding buffer by the transmission buffer write address and the transmission management buffer write address supplied in parallel with the supply. Transmission buffer 44 and transmission management buffer
The system bus transmission management unit 45 supplies the transmission buffer read address and the transmission management buffer read address to 46.

The details of the answer creating section 62 are shown in FIG. 4. The answer creating section 62 includes a source unit number register (SUR) 6
4, a selector (SEL) 66, a transmission buffer write address creation unit 68, and a timing control unit 70. The timing control unit 70 receives the answer creating instruction. The selector 66 is responsive to the selection signal from the timing control unit 70, the data from the internal bus access control unit 60, the transmission source unit number SU from the transmission source unit number register 64, and the bus width information from the reception management buffer 38. BW and other information ETC from the answer creating unit 62 are selectively selected and supplied to the transmission buffer 44. The writing of the input information in the transmission buffer 44 is performed by the transmission buffer write address creation unit 68.
The data is written from the storage location specified by the head transmission buffer write address (address determined by the transmission pointer). At the time of this writing, the timing control unit 70
A transmission buffer write signal (SB write signal) is supplied from the to the transmission buffer 44. The transmission pointer is transferred to the transmission management buffer 46 together with the byte number information from the internal bus access control unit 60 and other information ETC, and is stored in the storage location designated by the transmission management buffer write address from the answer creating unit 62. Written. At the time of this writing, the transmission control buffer write signal (SSB write signal) is sent from the timing control unit 70 to the transmission control buffer 46.
Supplied to

2 to 4, the system bus 103 corresponds to the split bus 2 of FIG. 1 and includes units 100 ₁ and 100 _2.
Corresponds to unit 4 _i . Receiver 30, reception register
34, the system bus management unit 35, and the reception management buffer 38 correspond to the bus width information extraction unit of FIG. 1, and include an internal bus interface circuit 40, a transmission buffer 44, a system bus management buffer 45, a transmission management buffer 46, and a transmission register. 42, driver
Reference numeral 32 corresponds to the bus width information insertion unit in FIG.

 The operation of the present invention under the above configuration will be described below.

First, a read operation from a receiving unit accessed by another processor via the split bus system bus 103 will be described.

The receiving unit receives the received contents in the receiving buffer 36 via the receiver 30 and the receiving register 34. The reception is performed by analyzing a 32-bit width command set in the reception register 34 (see the read command C2 in FIG. 5. A is an address, and this address is also 32 bits wide). . That is, the read / write information insertion area 208
However, when the transmission destination unit number DU of the transmission destination unit number insertion area 202 of the command set in the lead R matches the number of the unit, the reception is started. One unit of reception management information corresponding to the data written in the reception buffer 36, that is, the above-mentioned pointer P, read information R, bus width information BW, byte number BT, source unit number SU, and other information ETC is reception management. It is written in the buffer 38. Read information R in the reception management information,
Bus width information BW, source unit number SU, other information ET
C is in the received command, that is, read information R of the read / write information insertion area 208 and bus width information insertion area 206
Of the bus width information BW, the transmission source unit number SU of the transmission source unit number insertion area 204, and other information ETC of the other information insertion area 210, and the pointer P is the system bus reception management unit 3
It is a pointer of the value at the read command reception time managed by 5, and the number of bytes BT is the value obtained by counting the number of bytes of the data transferred following the command by the system bus reception management unit 35. To be done. The reception buffer 36 designated by the pointer P read from the reception management buffer 38 by the reception management buffer read address transmitted from the internal bus access control unit 60 in a predetermined relationship with the reception of this data, for example, in parallel. The data is read from the storage position of the read / write information R read from the reception management buffer 38, the bus width information BW, the number of bytes BT, the source unit number SU, and other information. The ETC is used to access the internal bus 105. This access itself follows the conventional method.

The operation of transmitting data transferred from the internal bus 105 in response to the read command will be described below.

When the result of the access (read) to the internal bus 105 is transferred to the internal bus access control unit 60,
The internal bus access control unit 60 sends an answer creating instruction signal to the answer creating unit 62 (see (2) in FIG. 6).
The "L" level selection signal is sent from the timing controller 70 which receives the answer creation instruction signal (see (5) in FIG. 6).
Is output. By this selection signal, answer information is first sent to the transmission buffer 44 via the selector 66 (see AN in (8) of FIG. 6). At the same time, the timing control unit 70 generates a transmission buffer write address generation signal, and the transmission buffer write address generation unit 68 generates a transmission pointer P in response to the transmission buffer write address generation signal. The answer information is the transmission pointer P from the transmission bus write address creation unit 68.
When the SB write signal (see (4) in FIG. 6) from the timing control unit 70 is applied to the storage position of the transmission buffer 44, that is, the head position of the transmission information, it is written. The transmission source unit number DU from the reception management buffer 38 is stored in the transmission destination unit number storage area in the storage location where the answer information (see (2) in FIG. 7) is written, and in the transmission source unit number storage area. Source unit number register 64
The self unit number SU sent from the bus width information storage area is the bus width information BW from the reception management buffer 38, and the other information storage area 230 is other information generated by the internal bus access control unit 60. ETC is stored. Bus width information BW from the transmission pointer P and the reception management buffer 38,
In addition, the byte count information BT from the internal bus access control unit 60
The other information ETC is first stored in the storage position of the transmission management buffer 46 designated by the transmission management buffer write address (see (6) in FIG. 6) under the management of the answer creating unit 62, and the timing control unit 70. It is written when the SSB write signal (see (3) in FIG. 6) is applied.

After the answer information is written in the transmission buffer 44, the "H" level selection signal output from the timing control unit 70 causes the internal bus access control unit 60 to select the access result data. The access result data has a data width determined by the bus width information BW, that is, a 32-bit width. The data is sequentially written from the storage position next to the storage position designated by the transmission pointer (see D1 and D2 in (8) of FIG. 6). The address used for this writing (see (7) in FIG. 6) is created from the transmission pointer P. At the completion of this writing, the number of bytes BT and other information ETC determined according to the amount of data written in the transmission buffer 44 by the writing,
The transmission management transferred from the internal interface circuit 60 is written in the byte number storage area in the transmission management information storage area of the buffer 46 and other information storage areas.

Writing to the transmission management buffer 46 and a predetermined relationship,
For example, in parallel, the transmission management buffer 46 is read by the read address determined by the read control by the system bus transmission management unit 45. The read address becomes the above-mentioned transmission management buffer write address, and the reading of the transmission management buffer 46 is caused.
By this reading, the transmission management information is read from the transmission management buffer 46. The reading from the storage position of the transmission buffer 44 designated by the transmission pointer P in the transmission management information is caused. The transmission information read first is answer information, and this answer information is transmitted from the driver 32 to the system bus 10 via the transmission register 42.
Sent to 3, and sent to the access request source. In the transmission, the bus width information in the transmission management information read from the transmission management buffer 46 is used, and the answer is transmitted via the system bus 103 with a width of 32 bits (see FIG. 2). 100 ₂ reference, AN2 see FIG. 5). AN2 is an answer to the command C2). The answer format on the system bus 103 is as shown in (2) of FIG.
Reference numerals 6 and 230 denote a destination unit number insertion area, a transmission source unit number insertion area, a bus width information insertion area, and other information insertion areas, respectively.

After this answer is transmitted, the transmission pointer P
From the storage location next to the number of bytes in the transmission management information BT
The reading up to the storage location determined by is continued. The data width is, for example, 32 as in the above answer.
It is a bit width.

Then, at the access request source, the bus width information BW in the answer transferred via the system bus 103 is fetched, and the data transferred subsequently is fetched in the bus width information BW, for example, 32 bits wide. .

Next, the write operation to the receiving unit accessed from another processor via the split bus system bus 103 will be described.

This operation is the same as the read operation from the receiving unit except as described below. First, the read / line information insertion area in the received 32-bit width command is the write information W, and the 32-bit width address A is
Transferred simultaneously via the 64-bit wide system bus 103. Secondly, the command and the address are followed by the 64-bit wide data, and thirdly, the number of bytes written to the reception management buffer 36 is received. Fourth, the number of bytes forming the data. Fourth, the number of bytes written in the transmission management buffer 46 is “0” because there is no data to be transmitted,
Therefore, only the 32-bit wide answer AN2 is written in the transmission buffer 44. The remaining 32 bits (hatched portion in FIG. 5) written in the transmission management buffer 46 together with AN2 are meaningless data.

An example of the write operation to the receiving unit having only such a difference is shown in FIG. 5 for the command C1, the address A, the data D, and the answer A1. The command C1, the address A, and the data D are information transferred to the receiving unit, and the answer A1 is information transferred from the receiving unit.

It should be noted that in the above embodiment, an example in which the bus width information BW sent from the transmission source to the transmission destination is inserted into the answer to the access of the transmission source and returned to the transmission source has been described, but it is prepared in advance at the transmission destination. Alternatively, the bus width information BW may be inserted in the answer and returned to the transmission source.

〔The invention's effect〕

As is clear from the above description, according to the present invention, since the bus width information is returned from the receiving unit to the transmitting unit via the split bus, any data width within the data width of the split bus can be obtained. It is possible to connect a unit that handles the above data to the split bus.

[Brief description of drawings]

FIG. 1 is a block diagram of the principle of the present invention, FIG. 2 is a diagram showing an embodiment of the present invention, FIG. 3 is a detailed view of the essential parts of the present invention in an interface circuit, and FIG. FIG. 5, FIG. 5 is a diagram showing an example of a transmission / reception sequence in the embodiment of FIG. 2, FIG. 6 is a diagram showing an example of an answer creation timing, and FIG. 7 is a command and answer format, and a reception management buffer and a transmission management buffer. FIG. 8 is a diagram showing a write information format of each storage position, FIG. 8 is a diagram for explaining information transfer on a non-split bus, and FIG. 9 is a diagram for explaining information transfer on a split bus. 1 to 4, 2 is a split bus (system bus 103), 4 _i is a unit (units 100 ₁ and 100 ₂ ), and 6 is a bus width information extraction unit (receiver 30, reception register 34, system bus management). The unit 35 and the reception management buffer 38) and 8 are bus width information insertion units (internal bus interface circuit 40, transmission buffer 44, system bus management buffer 45, transmission management buffer 46, transmission register 4).
2, driver 32).

Claims (2)

(57) [Claims] 1. A data processing system for transmitting / receiving information between a plurality of units (4 _i ) (i = 1, 2, ..., N) to which a split bus (2) having a constant bus width is connected. A bus width information output unit (6) for outputting the bus width information of the constant bus width to the receiving unit, and a bus width information inserting unit (8) for inserting the bus width information in an answer returned to the transmitting unit. ) Is provided, and an answer in which the bus width information output from the bus width information output unit (6) is inserted is returned as an answer to the command received from the transmission unit via the split bus (2). Variable bus width specification method for split buses. 2. A data processing system for transmitting / receiving information between a plurality of units (4 _i ) (i = 1, 2, ..., N) connected to a split bus (2), the receiving unit including: A variable bus in a split bus, characterized in that a bus width information extraction unit (7) for extracting bus width information from a received command is provided, and information received subsequently to the command is received according to the extracted bus width information. Width information reception method.