KR950009763B1 - A method of data transmission and synchronization between two cpu's - Google Patents

Abstract

checking whether an access flag is '0' to use a common buffer area and if the access flag is not '0', returning to a start point; if the access flag is '0', equalizing the access flag to a CPU_ID of a transmitting side, reading the access flag to check whether a usage right of a dual port RAM is ensured and checking whether the read access flag is the same as a user's CPU_ID; returning to the start point because the common buffer area is occupied by a counterpart's CPU, if the access flag is different from the user's CPU ID; if same, checking whether an empty flag is '1', returning to the start point, if not '1', and write data in a data area by equalizing the empty flag to '0', if the empty flag is '1'; and equalizing a reader to a receiving side's CPU_ID, equalizing a full flag to '1', and equalizing the access flag to '0', to thereby complete the transmitting side's processing operation.

Description

How to transfer and synchronize data between CPUs in a two CPU system

1 is a block diagram of a system to which the present invention is applied;

2 is a buffer structure diagram on a dual port RAM.

3 is a flow chart of mutual exclusion in data transmission using control flags.

* Explanation of symbols for main parts of the drawings

1,3 CPU 2: Dual Port RAM

The present invention is a method for realizing data transfer and synchronization between CPUs by changing the structure of a data transmission / reception buffer in software according to the nature of data to be transmitted by using dual port RAM efficiently in a system composed of multiple CPUs. It is about.

In general, there is a method of using shared memory to exchange data between two boards having independent CPUs, but as a shared memory, two unidirectional non-storage (FIRST-IN FIRST-OUT: FIFO) memories are used. There is a method for sending and receiving data and a method for sending and receiving data between the dual port RAM. Among the methods using FIFO, the buffer size and structure for sending and receiving are fixed in hardware. It is difficult to effectively use the buffer according to the situation, and when there is an error situation in which the other party does not read the data while both FIFO memories are filled with transmission data, there is no way to solve it. The dual port RAM shared memory does not have the limitation of FIFO memory, but due to the fact that the same address can be accessed from both CPUs at the same time, mutual exclusion between programs becomes difficult. In many cases, they used to behave like memory, failing to take advantage of the dual port RAM.

Accordingly, an object of the present invention is to provide a method for efficiently controlling dual port RAM to realize data transmission and synchronization between two boards (CPUs).

In order to achieve the above object, the present invention provides a data transmission and synchronization method of a system comprising a first and a second CPU and a dual port RAM; The sender's processing procedure checks whether the access flag is 0 in order to use the common buffer area and returns a nonzero value (if the access flag is not 0, it indicates that the other CPU is using the common buffer area). If the flag is 0, the access flag is the CPU_ID of the transmitting side, and the first step of checking whether the same as the CPU_ID of the dual port RAM is read again to check whether the license of the dual port RAM is secured, and performing the first step. If the access flag is different from its CPU_ ID, it means that the common buffer area is allowed to the other CPU. If it is equal, it checks whether the empty flag (EMPTY -FLAG) is 1, that is, it is an empty buffer. If it is 1, the empty flag is set to 0 and the data is written to the data area. After performing the second step, the reader is set as the receiving CPU_ ID and the full flag is set. The FULL FLAG is set to 1, the access flag is set to 0, and the third step of terminating is performed. The receiving procedure is performed by using a next butter pointer. (4) Investigate whether (the buffer containing its CPU_ID in the common buffer's leader field) finds whether the data on the sending side has arrived, that is, whether Man-flag is 1; after performing the fourth step, Man-Flag If it is not 1, it returns and if it is 1, it checks whether the access flag is 0 to secure the buffer. If it is not 0, it repeatedly checks whether the access flag is 0. If 0, the access flag is the receiving CPU_ ID and the access flag is received. After performing the fifth step of checking whether the CPU_ID is at the side, if the CPU_ID is not at the receiving side, perform the following steps. After the sixth step and the sixth step, the empty flag is set to 1, and if it is determined that the empty buffer is empty, the access flag is set to zero and the seventh step ends.

Hereinafter, with reference to the accompanying drawings will be described in detail the present invention.

1 is a schematic block diagram of a system to which the present invention is applied, in which 1 and 3 represent CPUs and 2 represents dual port RAMs.

As shown in the figure, the CPU 1 is composed of a dual port RAM 2 connected to an address bus and a data bus, and a CPU 3 connected to an address bus and a data bus to the dual port RAM 2. do.

Referring to the operation of the data transmission device having the above configuration, the dual port RAM (2) is to independently apply the address input, data input and output and control signals to each CPU (1, 3) to access simultaneously, Separately, each CPU (1,3) can access the memory independently of the other board. In this case, it is not a problem when two CPUs (1, 3) try to read the same address at the same time. However, when two CPUs try to write to a specific address at the same time, only one CPU is allowed to write. It is configured to enter the forced wait cycle in hardware and wait until the opponent write operation is completed. Here, the contention of the write operation for a specific address of the dual port RAM 2 may be solved in hardware, but the contention of the write operation for a certain area on the dual port RAM 2 may not be solved by the hardware method. After obtaining the license for the area by the hardware solution, write the data to be sent to the board, and then transfer the license of the area so that the other board can take the data.

2 shows the structure of a buffer on dual port RAM 2 for two boards through dual port RAM 2 to transmit data.

The access flag region 4 may have three values as flags for controlling the usage rights for the region of the dual port RAM 2. A value of 0 indicates that no one is using the dual port RAM (2) area, a value of 1 indicates that the CPU (1) is using the dual port RAM (2) area, and 2 indicates a CPU in the dual port RAM (2) area. (3) indicates that it is in use.

The reader area 5 indicates which CPU receives data through a specific buffer on the dual port RAM 2 and classifies the data according to each of the three values. 1 indicates a buffer used by the CPU 2 for sending data and used by the CPU 1 for receiving data, and 2 indicating a buffer used by the CPU 1 for sending data and receiving the data from the CPU 2.

The FULL-FLAG 6 is a signal flag for informing the receiving CPU that the data to be sent to the receiving end is written to the buffer on the dual port RAM 2, and the sending CPU only uses the data when the data is exhausted. -Change the flag from 0 to 1, and after the data has been read, the receiving CPU changes the man-flag from 1 to 0.

The EMPTY-FLAG (7) is a signal flag sent by the receiver to the transmitter so that the receiver can read the data on the receiver and use it again. The CPU changes the blank flag from 0 to 1, and once the sending CPU runs out of data, it changes the blank flag from 1 to 0.

The next buffer pointer (NEXT-BUFFER-POINTER) 8 is used to divide the dual port RAM area having a fixed size into several buffers and indicates the start address of the next buffer.

BUFFER-SIZE (9) Indicates the size of data (i.e., number of bytes) the sender wants to send to the receiver via the buffer on the dual port RAM (2). The data area (DATA-AREA) 10 is a flag used by the sender to handle data sent to the receiver and to secure a license before using the buffer. FULL FLAG (5) means that one CPU has finished writing data to the other side in the common buffer area on the dual port RAM (2). Empty flag (6) FLAP (6) indicates the dual port RAM sent by the other side. Indicates completion of data read on (2).

3 is an execution flowchart for realizing mutual exclusion, where (A) is a sender flowchart and (B) is a receiver flowchart.

First, the processing procedure of the transmission side flow checks whether or not the access flag is 0 to use the common buffer area, and returns it if it is not 0 (if the access flag is 0, it indicates that no one uses the common buffer area). ), The access flag is sent from the CPU_ID (CPU (1) or CPU (2): either) (12) and the access flag is sent from the access flag to confirm that the dual port RAM 2 is licensed. Check whether it is equal to CPU_ID (13). At this time, even if two CPUs attempt to secure a usage right at the same time, only one CPU is selected. If the result of the survey (13) is different, return and if it is equal, check whether the co-flag is 1, that is, an empty buffer (14). Write data to the data area (16). Next, the reader (READER) is the receiving side CPU_ID, only (17) is set to -1, and the access flag is set to 0 (18).

Then, the processing procedure of the receiving side finds the receiving buffer among the buffers on the dual port RAM 2 by using the next buffer pointer and checks whether the receiving side CPU_ID is received (20). If it is CPU_ID, it is checked whether the data of the transmitting party has arrived, that is, if the Man-flag is 1 (21). If only the flag 21 is returned as a result of the investigation 21, it is returned if the access flag is 0 to secure the license of the buffer (22). If the result of the check 22 does not equal 0, it is repeatedly checked whether the access flag is 0. If 0, the access flag is set to the receiving side CPU ID (CPU (1) or CPU (2) either) (23). It is checked whether the access flag is the receiving side CPU_ID (24). If the result of the value 24 is not the receiving CPU_ID, the process 22 or less can be performed, and if the receiving CPU ID, the Man-flag is set to 0 (25) and read from the data area (26). When the empty flag is set to 1 and the empty buffer is confirmed to be empty, the access flag is set to 0 and the process ends.

Therefore, the present invention is used for command / response processing between the main control unit of the G4 facsimile and the communication control unit, communication of transmission / reception document data and communication between two boards in an error situation, and two CPUs in a system composed of multiple CPUs, There is an effect that can be applied to data transfer between boards.

Claims (1)

In the data transmission and synchronization method of a system composed of the first and second CPUs (1, 3) and the dual port RAM (2), the processing procedure on the transmitting side is that the access flag is 0 in order to use the common buffer area. If it is not 0, it returns. (If the access flag is not 0, it indicates that the other CPU is using the common buffer area.) If the access flag is 0, the access flag is set as the sender CPU_ ID. In order to confirm whether the license is secured, the access flag reads the access flag again to check whether it is equal to its CPU_ID, and after performing the first steps (11 to 13), the access flag is assigned to its CPU_. If it is different from ID, it means that common buffer area is allowed to the other CPU. If it is equal, it checks whether the empty flag (EMPTY-FLAG) is 1. After the second steps (14 to 16) of writing lag to 0 and writing data to the data area, and performing the second steps (14 to 16), the reader (READER) is the receiving side CPU_ ID. FLAG) is set to 1, the access flag is set to 0, and then terminated by the third step (17 to 19). The processing procedure of the receiving side is for receiving of the buffer on the dual port RAM using the next buffer pointer. Step 4 (20, 21), which finds a buffer (a buffer containing its CPU_ID in the leader field of the common buffer) and checks whether the data on the sending side has arrived, that is, whether the man flag is 1; After (20,21), if Man-Flag is not 1, it returns and if it is 1 it checks to see if the access flag is 0 to license the buffer. If it is not 0, it repeatedly checks if the access flag is 0 and if it is 0 Set the flag as the receiving CPU_ ID and the access flag is received. After the fifth step (22 to 24) of checking whether the CPU_ID is applied or the fifth CPU (22 to 24) is performed, if the receiving CPU_ ID is not the same, the process is performed below. After the sixth step (25, 26) of reading from the data area and the sixth step (25, 26), the empty flag is set to 1 and the access flag is set to 0 when the empty buffer is confirmed. Method of data transfer and equalization between CPUs, characterized in that performed in seven steps (27, 28).