JPH0115100B2 - - Google Patents

Description

[Detailed description of the invention]

[Field of the Invention] The present invention relates to a data transfer system, and more particularly, to a system for transferring data between a data transmitting/receiving device that transmits and receives data over multiple lines and a central control unit (CC). [Prior Art] Generally, in data transfer between a data transmitting/receiving device that transmits/receiving data over multiple lines and a CC, in order to provide independence between processing within the data transmitting/receiving device and processing at the CC, the data transmitting/receiving device and the CC are A method is used in which a sending/receiving queue buffer is provided between the two and the transferred data is stored as a queue. In such a system, writing/reading of the queue buffer has conventionally been controlled by pointer control using pointers such as a write pointer, fetch pointer, execution pointer, etc., and the free status of the queue buffer is determined by the value of each pointer. It was determined and controlled by comparison. Therefore, in order to know the status of the queue buffer, first read the pointer and calculate the value of the counter that makes up the pointer. It was determined that there was no free area in the queue. As described above, in the queue write/read method based on pointer control, the process of reading the status of the queue buffer is complicated, and data transfer is inefficient. [Object of the Invention] An object of the present invention is to efficiently transfer data using the queue buffer. [Summary of the Invention] In order to achieve the above object, the present invention adds bits indicating the status of the receiving queue buffer and the transmitting queue buffer to the data read by the CC,
Regarding the receiving queue buffer, when there is data, it is possible to read the data continuously within a predetermined cycle, and regarding the transmitting queue,
This allows CC to know whether the buffer is empty or not without accessing the transmitting buffer. In addition, an indication that can distinguish the size of the free area of the buffer is added to the bit added to the data read by the CC that indicates the status of the transmitting buffer, and data with different block lengths can be written to the transmitting buffer. It's designed to be done efficiently. Furthermore, when the line-compatible buffer, which transfers and stores data in the transmitting queue buffer for transmission processing within the data transmitting/receiving device, becomes empty, the completion of transmission for that line is reported to the CC via the receiving queue buffer. By doing so,
This is to prevent overflow of the line-compatible buffer of the line that sent the data. [Embodiment of the Invention] Fig. 1 shows an example of a system to which the present invention is applied, in which 1 is a data terminal device, 2 is a call path switch of an exchange, 3 is a central control unit (CC) of an exchange, and 4 is a data transmission/reception unit. Device 5 is the SP bus. The data terminal device 1 and the data transmitting/receiving device 4 are connected by a communication path switch 2, and the data transmitting/receiving device 4 and
The CCs 3 are connected by an SP bus 5. Reference numeral 6 designates a transmission/reception processing circuit, a line compatible buffer memory, etc. of the data transmission/reception device 4, 7 a transmission/reception queue buffer, and 8 an SP bus interface circuit.
The data transmitting/receiving device 4 is composed of 6, 7, and 8. The data transmitting/receiving device 4 transmits data from the data terminal device 1 to the unit 6 through the communication path switch 2.
unit 6 receives the data and loads it into the receiving buffer of unit 7.
performs sending processing and sends it to the data terminal device 1. The data loaded into the receiving queue buffer No. 7 is transferred to the CC 3 through the SP bus interface circuit 8 and the SP bus 5, and similarly, the data sent from CC3 is transferred through the SP bus 5 to the sending queue buffer No. 7. FIG. 2 is an explanatory diagram of data transfer according to the present invention in the queue buffer. 7 and 8 in Figure 2 are the first
They are similar to 7 and 8 in the figure, with 9 being a transmitting queue buffer and 10 being a receiving queue buffer. Reference numeral 11 is a bit that indicates the state of the transmitting buffer 9 determined by the hardware logic using a pointer indicating the data storage position of the register that constitutes the transmitting buffer 9, and 12 is a bit that similarly indicates the state of the receiving buffer 9. . 1
3 is answer data read from the receiving queue buffer 10. The CC3 periodically accesses the receiving queue buffer 10, and the answer data 13 obtained by adding receiving and transmitting queue buffer status display bits 11 and 12 to the read data is obtained from the CC3.
will be forwarded to. The CC3 can determine the validity of the read received data and control the subsequent reading based on the queue buffer status display bits displayed in the answer data 13, and can also know the status of the transmitting queue buffer at the same time.
For example, when writing transmission data to the transmission queue buffer 9, it is possible to control the writing of transmission data without having to take the trouble to access the status of the buffer. Table 1 shows an example of the queue buffer status display at this time.

〔Effect of the invention〕

As explained above, in conventional pointer control, it was necessary to perform calculations to know the status of the queue buffer, but in the present invention, the read data of the receiving queue buffer is provided with bits indicating the status of both queue buffers, so the status of the queue buffer is easily
This has the advantage that the CC can be known and therefore the queue write/read can be easily controlled. Furthermore, since the state of the transmission queue buffer can be distinguished from the writing of long and short data, and a transmission completion report is provided, transmission data of multiple lines can be transferred very efficiently.

[Brief explanation of drawings]

FIG. 1 is a block diagram of an example of a system targeted by the present invention, FIG. 2 is an explanatory diagram of data transfer of the present invention in FIG. 1, and FIGS. 3 and 4 are diagrams of writing/reading of queue data according to the present invention. It is a conceptual diagram. 1...Data terminal device, 2...Call path switch of the exchange, 3...Central control device of the exchange, 4...
Data transmitting/receiving device, 5... SP bus, 6... Transmitting/receiving processing circuit, line compatible buffer memory, etc., 7...
Q buffer, 8...SP bus interface circuit, 9...Transmit buffer, 10...Receive buffer, 11...Transmit buffer status display bit, 12...Receive buffer status display bit, 13...Answer data for receiving buffer read , 14...Line compatible buffer memory, 15...Transmission processing circuit, 16...Reception processing circuit.

Claims (1)

[Claims] 1. In a method of transferring data between a data transmitting/receiving device that transmits/receives data over multiple lines and a central control unit (CC) via a transmitting/receiving queue buffer, a command to read data from the receiving buffer from the CC is provided. When receiving the data, the data transmitting/receiving device adds bits indicating the status of the receiving queue buffer and the transmitting queue buffer to the data read from the receiving queue buffer, and transfers the data to the CC. 2 The bit indicating the status of the transmit queue buffer is
An indication is given to distinguish the size of the free area of the transmitting buffer, and when writing data to the transmitting buffer, it is possible to write data with a long block length if there is sufficient free space. 2. The data transfer method according to claim 1, wherein data having different block lengths can be efficiently written to the transmission queue buffer by making the data discrimination possible. 3. In a method of transferring data between a data transmitting/receiving device that transmits/receiving data over multiple lines and a central control unit (CC) via a transmitting/receiving queue buffer, the data transmitting/receiving device performs transmission processing within the data transmitting/receiving device. When the line corresponding buffer, which is used to transfer and store the data of the transmitting queue buffer, becomes empty, the transmission completion of the corresponding line is reported to the CC using the read data of the receiving queue buffer, and the CC receives the report. A data transfer method characterized in that the transmission data for the corresponding line is written to the transmission queue after receiving the report, and if the transmission queue becomes ready for data writing before receiving the report, data of another line is written.