KR100686304B1 - Method for controlling access to public bank of dual port memory - Google Patents

Abstract

A method for controlling access to a public bank of a dual port memory is provided to permit the other process to access the public bank even if one process accesses and uses the public bank by allocating the public bank simultaneously permitting the access to two hosts. In case that an access request is received from the hosts connected to two ports at the same time, process priority of both hosts is determined(S402). The host having the higher priority processes data stored in the public bank by transferring a process grant signal to the port of the host having the high process priority and the host having the lower priority accesses the public bank by transferring an access grant signal to the port of the host having the lower process priority(S408,S418). In case that the host having the high process priority completes data processing, the host having the lower priority processes the data stored in the public bank by transferring the process grant signal to the port of the host having the lower process priority(S414,S424).

Description

How to control shared bank access of dual port memory {METHOD FOR CONTROLLING ACCESS TO PUBLIC BANK OF DUAL PORT MEMORY}

1 is an exemplary diagram for schematically illustrating a dual port memory to which the present invention is applied;

2 is a flowchart of a first embodiment for explaining a shared bank access control method of a dual port memory according to the present invention;

3 is a flowchart illustrating an example of a control signal received by a port in FIG. 2;

4 is a flowchart of a second embodiment for explaining a shared bank access control method of a dual port memory according to the present invention;

<Explanation of symbols on main parts of the drawings>

110, 111, 120: bank 130: shared bank

140: control unit

The present invention relates to a shared bank access control method of dual port memory, and more particularly, to sharing dual port memory for use in dual port dynamic random access memory (hereinafter, simply referred to as 'DRAM'). A bank access control method.

In general, DRAM is a large scale integrated circuit (LSI) memory which is most widely used as a main memory device of computers today, with a binary number ('0') depending on the presence or absence of charge of capacitors on the integrated circuit. And '1') to store the data.

Among such DRAMs, a single port DRAM having one input / output port can be used only by one host. Therefore, when two hosts access, the other host may access after all requests from one host are terminated. Such a structure has been a factor in degrading the performance of a system on a chip (SoC) chip having high performance and an integrated processor.

For this reason, the demand for development of dual port DRAM having two input / output ports is increasing, and Korean Patent Publication No. 2003-10984 (Dual Port Memory Controller for adjusting data access timing) has been disclosed. have.

The above-mentioned Patent Publication No. 2003-10984 is characterized by adjusting the data access timing of the processor by delaying a signal for not being able to accept a data access request for a stable read / write of data.

However, the Patent Publication No. 2003-10984 has a problem in that when one host is accessing and using the dual port memory controller, the other host may not only read / write but also access.

The present invention has been proposed to solve the above problems, and allocates a shared bank, which is a bank that two hosts can access at the same time, and accesses the other process even if one process accesses and uses the shared bank. Its purpose is to provide a shared bank access control method of dual port memory to enable this.

In order to achieve the above object, according to a preferred embodiment of the present invention, in the shared bank access control method of the dual port memory, when the access request from the host connected to any one of the dual port to the shared bank (A) when the host connected to the other port is accessing the shared bank and performing data processing, by transmitting an access signal to the port requesting the access, allowing the host to access the shared bank; And (b) when the host of the port performing the data processing has completed this, transmitting the processable signal to the port that delivered the accessible signal so that the host performs the processing of the data stored in the shared bank. A shared bank access control method of a dual port memory is provided.

In this case, accessing the shared bank of step (a) is preferably such that the host is in a standby state for processing data stored in the shared bank.

In addition, according to another embodiment of the present invention, in the shared bank access control method of the dual port memory, when the access request is received from the host connected to the two ports at the same time, the priority of the process of both hosts is determined Step (a); (B) transmitting a processable signal to a port of a host having a process having a substantially higher priority, so that the host having a process having a higher priority performs processing of data stored in a shared bank; And (c) forwarding an accessible signal to a port of a host having a process having a substantially lower priority, thereby allowing a host having a process having a substantially lower priority to access a shared bank. A control method is provided.

In this case, when a host having a process having a substantially higher priority has completed processing of data, the host transmits a processable signal to a port of the host having a process having a substantially lower priority, thereby processing the data stored in the shared bank. The method may further include the step (d), and in the case of (a), if the priority of the processes of both hosts is substantially the same, arbitrarily selecting one host to select a process having a high priority. The branch may further comprise the step (d) of designating a host.

In this case, the access to the shared bank of step (b) may be such that the host is in a standby state for processing data stored in the shared bank.

The above objects, features and advantages will become more apparent from the following detailed description taken in conjunction with the accompanying drawings. First of all, in adding reference numerals to the components of each drawing, it should be noted that the same components have the same number as much as possible even if displayed on different drawings. Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings.

1 is an exemplary diagram schematically illustrating a dual port memory to which the present invention is applied.

As shown in the figure, the dual port memory to which the present invention is applied will have a specified number of banks for each port. In the example of FIG. 1, there are four banks in total, of which two banks (BANKA_0 and BANKA_1) 110 and 111 are assigned to port A, and one bank (BANKB_0) 120 is connected to port B. You can see that it is assigned. In addition, it can be seen that the other bank, the shared bank 130, is simultaneously assigned to the A port and the B port.

In general, assuming that the dual port memory has S banks, S satisfies the following equation.

In this case, M is the number of banks 110 assigned to port A, N is the number of banks 120 assigned to port B, and K is the number of shared banks 130. In FIG. 1, the case where the number of the shared banks 130 is one is described, but is not limited thereto.

M banks and N banks can be accessed by two different hosts at the same time through the A port and the B port, respectively, and there is no fear that the two processes will collide, but each of the K shared banks 130 Appropriate arbitration may be necessary if a host of the station wants to access the shared bank 130 at the same time, or if another port wants to access when one port is already in use.

Therefore, the controller 140 of FIG. 1 controls each of the access request signals from different hosts according to the present invention. The controller 140 added two output signals READY [0] and READY [1] according to the present invention, and the host receiving the signal accesses the shared bank if the output signal is '0'. This is possible, but data processing is not possible, and the operation must be waited until the value becomes '1'. That is, the output signal '0' may be referred to as an 'accessible signal' and the output signal '1' may be referred to as a 'processable signal'.

In this case, the READY [0] and the READY [1] signal will be defined as a signal applied to the A port and the B port, respectively.

Meanwhile, for convenience of description of the present invention, a host connected to the A port is referred to as a 'A host', and a host connected to the B port is referred to as a 'B host'. In addition, the process going on host A will be referred to as 'Process A', and the process going on host B will be referred to as 'B Process'. However, this is only to be described for the convenience of description of the present invention, the present invention is not limited thereto.

FIG. 2 is a flowchart illustrating a method for controlling access to a shared bank of a dual port memory according to the present invention. In the case where one host accesses and uses the shared bank 130, another host accesses it. The case is shown.

As shown in the figure, the access control method of the present invention, when any host attempts to access the shared bank (S200), if another host accesses the shared bank 130 (ACCESS) the shared bank In the case of being used by reading / writing the data stored in the 130 (S202), the controller 140 transmits 'READY = 0' to the corresponding port (S204). Thus, the host can access the shared bank 130 (S206), but it can be said that a standby state in which processing such as reading / writing of data stored therein is not yet possible.

After that, when the data processing of the first accessed host is terminated (S208), the controller 140 transmits 'READY = 1' to the corresponding port (S210), and accesses and stores the shared bank 130. It may be possible to read and / or write with respect to (S212).

As such, when one host accesses and uses a shared bank, the present invention sets a READY signal allocated to another port to '0', where the host of the corresponding port is accessible and processing is performed by the control unit. This is possible when the READY signal transmitted by 140 is '1'.

FIG. 3 is a flowchart illustrating an example of a control signal received by a port in FIG. 2. When one host accesses and uses the shared bank 130, each port approaches a port. This is for explaining the state of the READY signal of the control unit 140 according to the command of the main controller (not shown) of the dual port memory transmitted to.

In this case, as described above, the READY [0] and READY [1] signals are applied to the A port and the B port, respectively.

As shown in the figure, if an ACTIVE command is transmitted from the main controller of the dual port memory to any port of the present invention (S300), in this case READY [0] = 1 and READY [1] = 1 and Equals (300).

At this time, in the case of the activation command to the A port (S302), it is checked whether the activation command to the shared bank 130 again (S304). In this case, READY [0] = 1 and READY [1] = 1 are continued (302 and 304). In case of an activation command for the shared bank 130 (S304), READY [0] = 1 and READY [1] = 0 (306). That is, in this case, the host A may process data with respect to the shared bank 130, and the host B may access only the shared bank 130.

Thereafter, when the host A of the port A completes the processing of the shared bank 130 and receives a PRECHARGE command from the main controller (S306), the controller 140 again reads READY [0]. ] = 1 and READY [1] = 1 may be sent to each port (308). If the command is not an activation command for the shared bank 130 in step S304, data processing may be performed on the bank allocated to the A port, where READY [0] = 1 and READY [1. ] = 1 will be (308).

On the other hand, in step S302, if it is not the activation command to the port A, that is, the activation command to the port B, it is checked whether the activation command to the shared bank 130 again (S310). In this case, READY [0] = 1 and READY [1] = 1 are continued (302 and 310). In the case of the activation command for the shared bank 130 (S310), READY [0] = 0 and READY [1] = 1 (312). That is, in this case, the host A can only access the shared bank 130, and the host B can process data with respect to the shared bank 130.

Thereafter, when the host B of the B port completes the data processing for the shared bank 130 and receives the preparation charge command from the main controller (S314), the controller 140 again reads READY [0] =. 1 and READY [1] = 1 may be sent to each port (314). If the command is not an activation command for the shared bank 130 in step S310, data processing may be performed on the bank allocated to the B port, where READY [0] = 1 and READY [1. ] = 1 will be 314.

FIG. 4 is a flowchart illustrating a method for controlling access to a shared bank of a dual port memory according to an embodiment of the present invention, and illustrates a case where two hosts access the shared bank 130 at the same time.

According to the present invention, when two hosts try to access the shared bank 130 (S400), the controller 140 preferably determines the priority of both processes (S402).

In general, in the case of DRAM, priority is assigned to a host that performs a faster termination, and in general, the priority for port A is high, but the detailed description thereof will be omitted in the present invention, and the determination of priority is performed. do.

That is, the controller 140 selects a process having a high priority (S404), and if the priority of the A process is high, delivers READY [0] = 1 and READY [1] = 0 to each port (S406). ). As a result, host A may access the shared bank 130 to read / write the stored data, and host B may access the shared bank 130 to wait for data processing (see FIG. S408).

Thereafter, when host A completes the process of reading / writing the data stored in the shared bank 130 (S410), READY [0] = 0 and READY [1] = 1 are transmitted to each port (S410). S412). As a result, the host B can perform processing such as reading / writing of data (S414).

If the priority of the B process is high in step S404, host A and host B may perform steps 2406 to S414 in a reverse order (steps S416 to S424).

If the priority of both processes is the same in step S404, a process is arbitrarily selected (S426), and if the selected process is an A process (S428), steps S406 through S414 are performed, and step S426 is performed. If the process selected in step B is a process (S428), it is preferable to perform the steps S416 to S424.

The present invention described above is not limited to the above-described embodiments and the accompanying drawings, and various substitutions, modifications, and changes can be made in the art without departing from the technical spirit of the present invention. It will be clear to those of ordinary knowledge.

In the present invention as described above, if two output signals READY [0] and READY [1] are added and this output signal outputs a value of '0', access to the shared bank is possible, but the signal is' By enabling data processing at 1 ', arbitration can be achieved when two hosts want to access a shared bank at the same time, or when another host wants to access one port already in use. There is an effect that can be performed efficiently.

Claims (6)

In the shared bank access control method of the dual port memory, When a shared bank receives an access request from a host connected to one of the dual ports, when a host connected to another port accesses and performs data processing, the access bank sends an access signal to the port that requested the access. (A) allowing the host to access the shared bank; And When the host of the port performing the data processing has completed this, transmitting the processable signal to the port which delivered the accessible signal so that the host performs the processing of the data stored in the shared bank (b). Shared bank access control method of the dual port memory including a. The method of claim 1, To access the shared bank of step (a), A method of controlling access to a shared bank of dual port memory, wherein the host is in a standby state for processing data stored in the shared bank. In the shared bank access control method of the dual port memory, (A) determining a priority of a process of both hosts when receiving access requests from hosts connected to two ports at substantially the same time; (B) transmitting a processable signal to a port of a host having a process having a substantially higher priority, so that the host having a process having a higher priority performs processing of data stored in a shared bank; And (C) transmitting an accessible signal to a port of a host having a process having a substantially lower priority so that a host having a process having a substantially lower priority has access to a shared bank; Shared bank access control method of the dual port memory including a. The method of claim 3, When a host having a process having a substantially higher priority has completed processing of data, the host transmits a processable signal to a port of the host having a process having a substantially lower priority, and the host performs processing of data stored in a shared bank. The shared bank access control method of the dual port memory further comprising the step (d). The method of claim 3, In the case of (a), if the priority of the processes of both hosts is substantially the same, the dual port further includes the step of selecting one host arbitrarily and designating it as a host having a process having a high priority. How to control shared bank access of memory. The method of claim 3, To access the shared bank of step (b), A method of controlling access to a shared bank of dual port memory, wherein the host is in a standby state for processing data stored in the shared bank.

Images