KR100210404B1 - An apparatus for controlling access of memory in dual bus system - Google Patents

Abstract

The shared memory access control apparatus according to the present invention comprises a bus master 210 having its own address bus AB1 and a data bus DB1, a bus master 210 and another address bus AB2 and a data bus DB2. If a bus request signal is input from the processor 240 having the CPU 240 and the bus master 210, a bus grant signal is output. If a grant ack signal is input, the bus master 210 is output. A specific memory module from the prelook logic 220, the prelook logic 220, or the processor 240, which interprets the upper address AB1 outputted by the controller and outputs the corresponding memory module request signals MEM1 to MEMn. If a request signal is input, it detects whether there is a collision, and if it does not collide, it outputs a signal allowing memory access to the bus master and processor, and outputs a memory control signal accordingly. A memory access controller 230 for outputting a control signal to negate any request according to an algorithm, and generating a control signal for accessing the memory by a device to which the access is allowed, and a plurality of individually accessible memory modules When the processor or bus master is accessed, the shared memory 250 stores or outputs data according to a control signal of the memory access controller.

Description

Shared Memory Access Control

The present invention relates to a shared memory access control apparatus for enabling a bus master and a processor to efficiently access shared memory in a system in which a processor and a bus master share memory.

In general, in order to use the bus in a computer system in which system resources are connected through a common bus, as shown in FIG. 1, when the bus arbiter permits the bus arbiter 16 to use the bus, The bus can be used.

That is, referring to FIG. 1, at least one processor board 11 and 12 is connected to the system bus 14, and the input / output board 15, the memory board 13, and the bus intermediator 16 are connected to the system bus 11. The bus master device capable of actively using the system bus in a system commonly connected to the ()) is a first processor board, a second processor board, an input / output board, and the like.

Therefore, since a collision occurs when the processor board or the input / output board approaches the system bus at the same time to use the system bus, the bus arbiter 16 arbitrates the bus use to prevent this. That is, when the processor boards 11 and 12 or the input / output board 15 request the bus arbiter 16 to use the bus in order to use the system bus 14, the bus intermediator sends a bus arbitrator to one bus master according to a predetermined algorithm. Allow bus use. The bus master is then allowed to transfer data using the system bus.

For example, when the input / output board 15 needs to store data in the memory due to an urgent situation while the first processor 11 reads data from the memory board 13 using the system, the input / output board 15 After requesting the bus arbiter to use the bus arbiter, the controller writes data to the memory board 13 through the system bus 14 when the use is permitted. In this case, the processor board 11 cannot use the system bus and thus cannot access the memory board.

As described above, in a system in which a shared bus is used to access memory by arbitration, since only one bus master can access the memory through the system bus, the use of memory is inefficient.

Accordingly, the present invention has been made to solve the above problems, and after dividing the memory into a plurality of modules that can be accessed separately, the processor and other busters to access the memory module at the same time, the shared memory access control device The purpose is to provide.

In order to achieve the above object, the apparatus of the present invention is a system having a bus master and a processor capable of inputting and outputting data to and from a shared memory independently having an address bus and a data bus independent from each other, wherein the bus master is a bus. PreLux Logic outputs a bus permission signal when a request signal is input, and outputs a corresponding memory module request signal by analyzing a higher address output by the bus master when a bus response signal is input; When a signal for requesting a specific memory module is input from the prelux logic or from the processor, a collision is detected. If there is no collision, a signal for allowing memory access to the bus master and the processor is output and a memory control signal corresponding thereto is output. A memory access controller which outputs a control signal to negotiate any one request according to a predetermined algorithm when collided, and generates a control signal for accessing the memory by a device to which the access is permitted; And a shared memory configured to store or output data according to a control signal of a memory access controller when any one of a processor or a bus master is accessed by a plurality of individually accessible memory modules.

1 is a view illustrating a bus arbitration function in a general computer system;

2 is a diagram illustrating a shared memory access control apparatus according to the present invention;

3 is an operation timing diagram of an apparatus according to the present invention.

* Explanation of symbols for main parts of the drawings

210: bus master 220: prelook logic

230: memory access controller 240: processor (CPU)

250: shared memory M1, M2, Mn: memory module

Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings.

2 is a block diagram illustrating a memory access control apparatus according to the present invention, and FIG. 3 is an operation timing diagram of the apparatus according to the present invention.

The apparatus according to the present invention has a bus master 210 having its own address bus AB1 and data bus DB1, a bus master 210 and a different address bus AB2 and data bus, as shown in FIG. When a bus request signal is input from the processor 240 (CPU) having a DB2 and the bus master 210, a bus grant signal is output, and when a grant ack signal is input, the bus is output. From the pre-look logic 220, the pre-look logic 220, or from the processor 240, which interprets the upper address AB1 output by the master 210 and outputs the corresponding memory module request (MEM1 to MEMn) signals. If a signal for requesting a specific memory module (MEM1 REQ to MEMn REQ or PCS1 to PCSn) is input, if there is a collision, if there is no collision, a signal for allowing memory access to the bus master and the processor is output and the memory control accordingly God Outputs (SELn, CSn, WEn, OEn, DIRn), outputs a control signal to negate any request according to a predetermined algorithm when a collision occurs, and a control signal for accessing the memory by a device to which the access is allowed A shared memory configured to store and output data according to a control signal of the memory access controller when any one of the processor or the bus master accesses the memory access controller 230 generating a memory and a plurality of individually accessible memory modules. 250).

In addition, the shared memory 250 is composed of n memory modules M1 to Mn, and each memory module has an address bus AB1 of a bus master or an address bus AB2 of a processor according to the selection signals SEL1 to SELn. Is activated according to the multiplexers 251, 252 and 253 connecting the memory module to the memory module and the chip select signals CS1 to CSn to store data in accordance with the write signals WE1 to WEn or to the enable signals OE1 to OEn. The data bus DB1 of the bus master or the data bus DB2 of the processor is connected to the memory devices in accordance with the memory devices 254, 255, and 256 for outputting data, and the select (SEL1 to SELn) signals and the direction (DIR1 to DIRn) signals. Is composed of mux / demux logic (257, 258, 259).

Next, the operation of the apparatus of the present invention configured as described above will be described with reference to the timing diagram of FIG. 3.

Since the bus master 210 has a direct memory access (DMA) function, the bus master 210 undergoes an arbitration process to access a memory using a bus. In general, the arbitration process requires the use of a bus as a bus req signal to a device with a bus arbitration function (typically, a bus arbitrator), and a bus grant signal from the bus arbitrator. When received, it outputs a grant acknowledgment signal and simultaneously inputs and outputs an address and data using a bus.

In the present invention, since the bus master and the processor use independent buses (dual bus systems), no bus arbitration process is required, but the memory request signal is made using the bus arbitration signal provided by the bus master.

In other words, when the bus req signal is input from the bus master 210, the prelux logic 220 outputs a bus grant signal immediately. Then, when the grant ack signal is input, the bus master The upper address of the address bus AB1 output from the 210 is latched and decoded to output a memory request (MEM1 REQ to MEMn REQ) signal to the memory access controller 230. In this case, the memory request signal is a signal for requesting a memory module appropriately divided in the memory space by an upper address. For example, when the shared memory is composed of n memory modules M1 to Mn, the memory module 1 (M1) to the memory module are used. This signal is required to access any one of the n (Mn) memory modules.

The memory access controller 230 receives a memory request signal (MEM1 REQ to MEMn REQ or PCS1 to PCSn) from the lookup logic 220 or the processor 240 to request that the two memory signals collide (ie, request the same memory module). If there is no conflict, the processor or bus master can access the memory at the same time, and if there is a conflict, select either of them according to a predetermined procedure.

In this case, when the bus master is selected, the req ack signal is activated by the prelogic 220, and when the processor 240 is selected, the READY signal of the processor is activated. Meanwhile, if the req ack signal is not activated from the memory access controller 230, the pre-look logic 220 outputs a wait signal to the bus master.

In addition, if the memory module requested by the bus master 210 and the memory module requested by the processor do not collide with each other, the memory access controller 230 enables the corresponding memory modules and controls signals from the bus master 210 or the processor 240. The control signal is outputted so that the read or write operation is performed.

For example, when the bus master 210 accesses the memory module 1 M1 to store data, and the processor 240 accesses the memory module n Mn to read data, the operation is performed as follows. .

1. The bus master writes data to memory module 1.

The bus master 210 outputs a bus req signal and outputs a grant ack signal when a bus grant signal is input from the free look logic 220. Output the address for access. The pre-logic logic 220 interprets the upper bits of this address and outputs a first memory module request (MEM1 REQ) signal to the memory access controller 230.

Since the memory access controller 230 does not conflict with the request of the bus master 210 and the request of the processor, the multiplexer 251 sets the select (SEL1) signal of the first memory module M1 high (or low). The address bus AB1 of the bus master is connected to the memory device 254, the memory write control signal is input from the bus master 210 to generate the write signal WE1, and the direction DIR signal is generated. The high (or low) signal is selected and the select (SEL1) signal is set high to connect the bus master's data bus DB1 to the memory 254, with the direction from the data bus to the memory side.

Therefore, data output from the bus master through the data bus is stored (written) in the corresponding address area of the first memory module M1.

2. The processor reads data from memory module n

The processor 240 outputs a signal PCSn requesting the memory module n to the memory access controller 230, and then outputs an address for accessing the memory module Mn.

Since the memory access controller 230 does not collide with the request of the processor and the request of the bus master, the multiplexer 253 sets the address of the processor by setting the select (SELn) signal of the memory module n (Mn) low (or high). The bus AB2 is connected to the memory device 256, the memory read control signal is input from the processor to generate an out enable signal, the DIR signal is set low (or high), and the selection is made. With the signal low, the data bus DB2 of the processor is coupled to the memory element 256, with the direction from the memory side to the data bus side. Therefore, data stored in the address area output by the processor can be read.

On the other hand, when the memory module to be accessed by the processor 240 and the bus master 210 collide with each other, a control signal is generated so that the processor or bus master selected by the memory access controller 230 can access the corresponding memory module, The unselected busmaster or processor outputs a control signal for standby.

Referring to FIG. 3, (a) shows a system clock (SYS CLK), (b) shows a bus request signal (BUS REQ) of a bus master, and (c) shows a bus master signal of a bus master. (D) represents a GRANT ACK signal. In addition, (e) shows an upper address and (f) shows a lower offset (OFFSET) address.

(G) of FIG. 3 shows a select (SELi) signal, (h) shows a direction (DIRi) signal, (i) shows a weight (WAIT) signal, and (j) shows a memory request (PCSi) of the processor. Signal, and (k) represents a ready signal.

3 (a) to (k), when the bus request (BUS REQ) signal is activated high from the bus master 210 as shown in (b), the prelux logic 220 accordingly causes the bus permission (BUS). GRANT) signal from low to high. When the bus grant signal becomes high, the bus master 210 recognizes that the bus is permitted to use the bus, and switches the grant acknowledge signal from low to high and the upper address and offset. Drive the address.

Then, the lookup logic 220 interprets the upper address and requests the memory access controller 230 for the memory module to be accessed.

On the other hand, when the processor requests the memory access controller 230 to access the memory module required by the memory request signal PCSi, or the free look logic 220 requests access to the memory module, the memory access controller 230 may collide with each other. After checking, generate the select (SELi) signal and the direction (DIRi) signal of the memory module and output them to the corresponding memory module.If a collision occurs, limit the memory access of the processor with the READY signal or request request (req). an ack) signal, and the prelux logic 220 generates a WAIT signal according to the request ack signal to limit the memory access of the bus master 210.

As described above, when the shared memory access control apparatus according to the present invention attempts to access a common memory by a bus master or a processor having a DMA function, the shared memory access control apparatus divides the memory into a plurality of memory modules so that they can be accessed individually, and then crashes. Without this, the shared memory can be accessed at the same time, making the shared memory more efficient.

Claims (2)

In a system having a bus master and a processor having independent address buses and data buses, which can input and output data to and from a shared memory independently, A prelux logic 210 for outputting a bus permission signal when a bus request signal is input from the bus master, and interpreting an upper address output by the bus master when a bus response signal is input; When a signal for requesting a specific memory module is input from the prelux logic or from the processor, a collision is detected. If there is no collision, a signal for allowing memory access to the bus master and the processor is output and a memory control signal corresponding thereto is output. A memory access controller 220 which outputs a control signal to negotiate any one request according to a predetermined algorithm when a collision occurs, and generates a control signal for accessing the memory by a device to which the access is permitted; And Shared memory access control device consisting of a shared memory (230) configured to store or output data according to the control signal of the memory access controller when any one of the processor or the bus master is accessed by a plurality of individually accessible memory modules. The memory module of claim 1, wherein the memory module of the shared memory is configured to connect the address bus AB1 of the bus master or the address bus AB2 of the processor to the memory modules according to selection signals SEL1 to SELn. And memory elements 254, 255, and 256 which are activated according to the chip select signals CS1 to CSn and store data according to the write signals WE1 to WEn or output data according to the out enable signals OE1 to OEn. And a mux / demux logic (257, 258, 259) for connecting a bus master data bus or a processor data bus to the memory device according to a signal and a direction signal.