JPH05151142A - Interface circuit - Google Patents

Abstract

PURPOSE:To execute the asynchronous reading and writing operations of a synchronizing dual port RAM by a CPU. CONSTITUTION:An interface circuit 10 of a synchronizing dual port RAM 30 and a CPU 20 consists of an address latch circuit for the RAM 30, a write data latch circuit, a read data buffer circuit, a data writing mode flag generating circuit, a flag generating circuit which shows a fact that the data to be read are valid, a flag reading buffer circuit, the generating circuits which produce the chip selection signal, the write enable signal, and the output enable signal to the RAM 30, and a program which secures the flag read/read-out/write timing through the buffer circuits.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION The present invention relates to a synchronous 2-port RAM.
And CPU interface circuit. In particular, LS
The present invention relates to an interface circuit between the internal synchronous 2-port RAM and the CPU.

[0002]

2. Description of the Related Art A conventional asynchronous 2-port RAM is shown in FIG.
As shown in (2), it has two ports for the same address and can read and write from both ports, and is usually used for data transfer between CPUs.
The read and write sequences are asynchronously performed by the access from the CPU, as shown in FIG.

[0003]

With the progress of circuitization of LSIs, LSIs having a synchronous 2-port RAM inside have been created. The synchronous 2-port RAM performs reading and writing in synchronization with a synchronization clock, and the timing is shown in FIG. When the CPU accesses the synchronous 2-port RAM, the read and write signals of the CPU are connected to the output enable signal terminal and the write enable signal terminal of the synchronous 2-port RAM at the timing shown in FIG. Even if writing or writing is performed, unless the reading or writing signal rises while the synchronizing clock rises while the reading or writing signal is at the low level and the data of the synchronous 2-port RAM is held.
Since the data read or written by the CPU is not valid, there is a drawback that the correct reading and writing cannot be performed.

The present invention eliminates such drawbacks, and an object of the present invention is to provide an interface circuit for realizing asynchronous reading and writing of a synchronous two-port RAM by a CPU.

[0005]

According to the present invention, in an interface circuit interposed between a CPU and a synchronous two-port RAM, a circuit for latching addresses read and written by the CPU and data for writing are latched. Circuit, a first buffer circuit for reading data from the synchronous 2-port RAM, and the synchronous 2-port R
A circuit for generating a write busy flag signal indicating that data is being written to the AM, a circuit for generating a read enable flag signal indicating that the data to be read is valid, the write busy flag signal and the read enable flag signal A second buffer circuit for reading out, a circuit for generating a chip select signal, an output enable signal and a write enable signal for the synchronous 2-port RAM, and a write busy flag signal for reading via the second buffer circuit. And a program for determining the timing of reading, reading and writing of the enable flag signal.

[0006]

In the synchronous 2-port RAM, when both the chip select signal and the write enable signal are low level, data is written in synchronization with the rising edge of the synchronous clock. To satisfy this condition, the program writes the address value of the synchronous 2-port RAM to be written to the address latch circuit and the data to be written to the data latch circuit. By this data writing, the write busy flag signal is set to the high level, and the control signal generation circuit sets the write enable signal and the chip select signal to the low level. When the synchronous clock falls twice, the write busy flag signal is set to low level,
The control signal generation circuit sets the write enable signal and the chip select signal to high level. On the other hand, the program
The write busy flag signal is polled by writing data to the data latch circuit, and the next data is not written while the write busy flag signal is at a high level. As a result, the data is written correctly. Further, in the synchronous 2-port RAM, when both the chip select signal and the write enable signal are low level, data is read in synchronization with the rising edge of the synchronous clock. In order to satisfy this condition, the program is a synchronous 2-port RAM to be read by the address latch circuit.
Write the address value of and request read from the data latch circuit. By this request, the read enable flag signal is set to the high level, and the control signal generation circuit sets the write enable signal and the chip select signal to the low level. When the synchronous clock rises, the read enable flag signal goes low. On the other hand, the program polls the read enable flag signal after the request, and does not read the data of the synchronous 2-port RAM while the read enable flag signal is at the high level. When the read enable flag signal becomes low level, the program executes the synchronous 2-port RA.
The data of M is read, and the control signal generation circuit sets the output enable signal and the chip select signal to the high level. As a result, the data is written correctly.

[0007]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention will be described below with reference to the drawings. 1 to 7 show an interface circuit between a synchronous 2-port RAM having an address of 8 bits and data of 8 bits and a CPU as the embodiment.

FIG. 1 is a block diagram showing the overall configuration of this embodiment, FIG. 2 is a connection diagram showing the configuration of the interface circuit 10 included in FIG. 1, and FIG.
2 is a connection diagram showing a configuration of an address latch circuit 11 included in FIG. 4, and FIG. 4 is a flag signal generation circuit 1 included in FIG.
3 is a connection diagram showing the configuration of FIG. 3, FIG. 5 is a connection diagram showing the configuration of the flag signal generation circuit 14 included in FIG. 2, and FIG. 6 is a configuration diagram of the control signal generation circuit 16 included in FIG. FIG. 7 is a connection diagram shown, and FIG. 7 is a connection diagram showing a configuration of the buffer circuit 18 included in FIG.

In this embodiment, as shown in FIGS. 1 to 7, there is an address latch circuit 11 interposed between a CPU 20 and a synchronous two-port RAM 30 for latching an address read and written by the CPU 20, and a write. Data latch circuit 12 for latching data to be processed, buffer circuit 18 for reading data from synchronous 2-port RAM 30, and flag signal generating circuit 13 for generating a write busy flag signal indicating that data is being written to synchronous 2-port RAM 30. A flag signal generation circuit 14 for generating a read enable flag signal indicating that the data to be read is valid, and a buffer circuit 1 for reading the write busy flag signal and the read enable flag signal.
5, a control signal generating circuit 16 for generating a chip select signal, an output enable signal and a write enable signal for the synchronous 2-port RAM 30, and a write busy flag signal and a read enable flag signal via a buffer circuit 15. And a program storage circuit 17 that stores a program that determines the timing of reading, reading, and writing.

Next, the operation of this embodiment will be described. Figure 1
The interface circuit performs writing at the timing of 1 and reading at the timing of FIG. here,
The portion a in FIG. 11 is from the CPU 20 to the synchronous 2-port RAM 3
12 shows data writing to 0, and part b of FIG.
Access to a request address for reading from the port RAM 30 is shown, and part c shows reading of data. At the time of writing, as shown in FIG. 4, the data to be written in the synchronous 2-port RAM 30 is synchronized with the rising edge of the synchronous clock when the chip select signal is at the low level and the write enable signal is at the low level. Is captured. In this interface circuit 10 for satisfying this condition, the falling edge of the synchronous clock is set to 2
The write enable signal and the chip select signal are kept at a low level until the detection is performed. Further, the CPU 20 does not write the next data until the write busy flag signal becomes low level. Further, at the time of reading, as shown in FIG. 10, when the chip select signal is at the low level and the output enable signal is at the low level, data is output in synchronization with the rising edge of the synchronous clock. To meet this condition, this circuit detects the rising edge of the synchronous clock and resets the read enable flag signal,
At the same time, the chip select signal and the output enable signal are kept at the low level until the CPU 20 reads the data. Further, the CPU 20 does not read data until the read enable flag signal becomes low level.

That is, the synchronous 2-port RAM 30 is
When both the chip select signal and the write enable signal are low level, data is written in synchronization with the rising edge of the synchronous clock. To meet this condition,
The program of the program storage circuit 17 is a synchronous 2-port RAM to be written in the address latch circuit 11.
The address value of 30 is written into the data latch circuit 12 as data to be written. By this data writing, the flag signal generation circuit 13 sets the write busy flag signal to the high level, and the control signal generation circuit 16 sets the write enable signal and the chip select signal to the low level.
When the synchronous clock falls twice, the flag signal generation circuit 13 sets the write busy flag signal to the low level, and the control signal generation circuit 16 sets the write enable signal and the chip select signal to the high level. On the other hand, the program of the program storage circuit 17 is the data latch circuit 1
By writing data to the buffer circuit 2,
Polls the write busy flag signal by
The next data is not written while the write busy flag signal is at the high level. As a result, the data is written correctly. Further, in the synchronous 2-port RAM 30, when both the chip select signal and the write enable signal are low level, data is read in synchronization with the rising edge of the synchronous clock. In order to satisfy this condition, the program in the program storage circuit 17 has the address latch circuit 11
The address value of the synchronous 2-port RAM 30 to be read is written to, and the data latch circuit 12 is requested to read. In response to this request, the flag signal generation circuit 14 sets the read enable flag signal to the high level, and the control signal generation circuit 16 sets the write enable signal and the chip select signal to the low level. When the synchronous clock rises, the flag signal generation circuit 1
4 sets the read enable flag signal to a low level. On the other hand, the program of the program storage circuit 17 polls the read enable flag signal by the buffer circuit 15 after the request, and does not read the data of the synchronous 2-port RAM 30 while the read enable flag signal is at the high level. When the read enable flag signal becomes low level, the buffer circuit 18 causes the buffer circuit 18 to load the program stored in the program storage circuit 17.
Data is read out, and the control signal generation circuit 16 sets the output enable signal and the chip select signal to the high level. As a result, the data is written correctly.

[0012]

As described above, the present invention makes it possible to read and write the synchronous two-port RAM even from an asynchronous CPU, and an interface circuit between CPUs or other peripherals corresponding thereto. There is an effect that an LSI including a synchronous 2-port RAM can be used when forming an interface circuit with the circuit.

[Brief description of drawings]

FIG. 1 is a block configuration diagram showing an overall configuration of an embodiment of the present invention.

FIG. 2 is a block configuration diagram showing a partial configuration of an embodiment of the present invention.

FIG. 3 is a block configuration diagram showing a partial configuration of an embodiment of the present invention.

FIG. 4 is a block configuration diagram showing a partial configuration of an embodiment of the present invention.

FIG. 5 is a block diagram showing a partial configuration of an embodiment of the present invention.

FIG. 6 is a block configuration diagram showing a partial configuration of an embodiment of the present invention.

FIG. 7 is a block configuration diagram showing a partial configuration of an embodiment of the present invention.

FIG. 8 is a block configuration diagram showing a configuration of a conventional example.

FIG. 9 is a timing chart showing the timing of writing and reading of the asynchronous 2-port RAM.

FIG. 10 is a timing chart showing the timing of writing and reading of the synchronous 2-port RAM.

FIG. 11 is a timing chart showing the timing of synchronous writing in the embodiment of the present invention.

FIG. 12 is a timing chart showing the timing of synchronous reading in the embodiment of the present invention.

[Explanation of symbols]

 10 interface circuit 11 address latch circuit 12 data latch circuit 13 and 14 flag signal generation circuit 15 buffer circuit 16 control signal generation circuit 17 program storage circuit 18 buffer circuit 20 CPU 30 synchronous 2-port RAM

Claims (1)

[Claims] 1. An interface circuit interposed between a CPU and a synchronous 2-port RAM, a circuit for latching an address read and written by the CPU, a circuit for latching data to be written, and the synchronous 2-port. A first buffer circuit for reading data from the RAM, a circuit for generating a write busy flag signal indicating that data is being written to the synchronous 2-port RAM, and a read enable flag signal for indicating that the data to be read are valid. A generating circuit, a second buffer circuit for reading the write busy flag signal and the read enable flag signal, and a chip select signal, an output enable signal and a write enable signal for the synchronous 2-port RAM. Circuit and above second buffer times Loading the write busy flag signal and the read error Neiburu flag signal through the interface circuit, characterized in that a program for determining the timing of the read and write.