JP2944280B2 - Interface circuit - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a synchronous two-port RAM.
And an interface circuit of the CPU. In particular, LS
I relates to an interface circuit between a synchronous two-port RAM inside the I and a CPU.

[0002]

2. Description of the Related Art Conventionally, an asynchronous two-port RAM is shown in FIG.
As shown in (1), there are two ports for the same address, reading and writing are possible from both ports, and it is usually used for data transfer between CPUs.
Read and write sequence, as shown in FIG. 9 is performed asynchronously by the access from CPU.

[0003]

With the progress of circuit integration, LSIs having a synchronous 2-port RAM inside have been produced. The synchronous two-port RAM performs reading and writing in synchronization with a synchronization clock, and the timing is shown in FIG. When the synchronous 2-port RAM is accessed by the CPU, the read and write signals of the CPU are connected to the output enable signal terminal and the write enable signal terminal of the synchronous 2-port RAM at the timing shown in FIG. Or, even if writing is performed, as long as the synchronization clock rises while the read or write signal is low and the read or write signal does not rise while the data of the synchronous 2-port RAM is held,
Since the data read or written by the CPU is not valid, there is a drawback that reading and writing cannot be performed correctly.

An object of the present invention is to eliminate such a drawback, and an object of the present invention is to provide an interface circuit which realizes asynchronous reading and writing of a synchronous two-port RAM by a CPU.

[0005]

SUMMARY OF THE INVENTION The present invention operates asynchronously.
An interface circuit interposed between the CPU and a synchronous two-port RAM in which reading and writing from the CPU are performed, a circuit for latching an address to be read and written by the CPU, and a latch for data to be written. A circuit, a first buffer circuit for reading data from the synchronous two-port RAM, a circuit for generating a write busy flag signal indicating that data is being written to the synchronous two-port RAM, and that the data to be read is valid. A second buffer circuit for reading the write busy flag signal and the read enable flag signal; a chip select signal for the synchronous 2-port RAM;
A circuit for generating an output error enable signal and a write error enable signal, the reading of the second write busy through the buffer circuit flag signal and the read error Neiburu flag signal, and a program storage circuit for determining the timing of the read and write are input Based on the clock
Read at the timing determined by the program storage circuit.
When writing, the above chip
Rect signal and the above write enable signal
The chip select signal when reading
And output enable signal at specified timing
And means for maintaining the interval .

[0006]

In the synchronous two-port RAM, data is written in synchronization with the rising edge of the synchronous clock when both the chip select signal and the write enable signal are at a low level. To satisfy this condition, the program writes an address value of the synchronous 2-port RAM to be written to the address latch circuit and data to be written to the data latch circuit. By this data writing, the write busy flag signal is set to the high level, and the control signal generation circuit sets the write enable signal and the chip select signal to the low level. When the synchronous clock falls twice, the write busy flag signal is set to low level,
The control signal generating circuit sets the write enable signal and the chip select signal to high level. On the other hand, the program
The write busy flag signal is polled by writing data to the data latch circuit, and the next data is not written while the write busy flag signal is at a high level. As a result, data is correctly written. The synchronous-type two-port RAM, when the chip select signal and output enable signal are both low level, data is read in synchronization with the rising edge of the synchronous clock. To satisfy this condition, the program writes an address value of the synchronous 2-port RAM to be read to the address latch circuit, and requests the flag generation circuit to read. With this request,
And a read error Neiburu flag signal to the high level, the control signal generating circuit to an output enable signal and the chip select signal to a low level. When the synchronous clock rises, the read enable flag signal goes low. On the other hand, the program polls the read enable flag signal after the request, and does not read data from the synchronous 2-port RAM while the read enable flag signal is at a high level. When the read enable flag signal goes low, the program
The data in the port RAM is read, and the control signal generation circuit sets the output enable signal and the chip select signal to high level. This allows data to be read correctly.
Ru is Desa see.

[0007]

An embodiment of the present invention will be described below with reference to the drawings. FIGS. 1 to 7 show an interface circuit between a CPU and a synchronous 2-port RAM having an address of 8 bits and data of 8 bits.

FIG. 1 is a block diagram showing the overall configuration of this embodiment, FIG. 2 is a connection diagram showing the configuration of an interface circuit 10 included in FIG. 1, and FIG.
FIG. 4 is a connection diagram showing a configuration of an address latch circuit 11 included in FIG.
3 is a connection diagram showing a configuration of FIG. 5, FIG. 5 is a connection diagram showing a configuration of a flag signal generation circuit 14 included in FIG. 2, and FIG. 6 is a connection diagram of a control signal generation circuit 16 included in FIG. FIG. 7 is a connection diagram showing a configuration of the buffer circuit 18 included in FIG.

In this embodiment, as shown in FIGS. 1 to 7, an address latch circuit 11 interposed between a CPU 20 and a synchronous two-port RAM 30 for latching an address to be read and written by the CPU 20, and a write operation. A data latch circuit 12 for latching data to be output, a buffer circuit 18 for reading data from the synchronous two-port RAM 30, a flag signal generating circuit 13 for generating a write busy flag signal indicating that data is being written to the synchronous two-port RAM 30, A flag signal generating circuit 14 for generating a read enable flag signal indicating that data to be read is valid, and a buffer circuit 1 for reading a write busy flag signal and a read enable flag signal.
5, a control signal generating circuit 16 for generating a chip select signal, an output enable signal, and a write enable signal for the synchronous 2-port RAM 30, and a write busy flag signal and a read enable flag signal via a buffer circuit 15. And a program storage circuit 17 for storing a program for determining read and write timings.

Next, the operation of this embodiment will be described. FIG.
Writing at the timing of 1 and reading at the timing of FIG. 12 are performed by the interface circuit. here,
11a is a synchronous 2-port RAM 3 from the CPU 20.
0 indicates that data is written in the synchronous system 2 in FIG.
An access to a request address for reading from the port RAM 30 is shown, and a part c indicates data reading. At the time of writing, as shown in FIG. 11 , the data to be written into the synchronous 2-port RAM 30 is synchronized with the rising edge of the synchronous clock when the chip select signal is at a low level and the write enable signal is at a low level. Is taken in. In this interface circuit 10 for satisfying this condition, the write enable signal and the chip select signal are kept at a low level until the falling of the synchronous clock is detected twice. In the CPU 20,
The next data is not written until the write busy flag signal goes low. At the time of reading, as shown in FIG. 12 , when the chip select signal is at a low level and the output enable signal is at a low level, data is output in synchronization with the rising edge of the synchronous clock. To satisfy this condition, the present circuit detects the rising edge of the synchronous clock, resets the read enable flag signal, and keeps the chip select signal and the output enable signal at low level until the CPU 20 reads data. The CPU 20 does not read data until the read enable flag signal goes low.

That is, the synchronous two-port RAM 30 comprises:
When the chip select signal and output enable signal are both low level, the data is written in synchronization with the rising edge of the synchronous clock. To satisfy this condition, the program of the program storage circuit 17 writes the address value of the synchronous two-port RAM 30 to be written to the address latch circuit 11 and the data to be written to the flag signal generation circuit 14 . By this data writing, the flag signal generating circuit 13 sets the write busy flag signal to a high level, and the control signal generating circuit 16 sets the write enable signal and the chip select signal to a low level. When the synchronous clock falls twice, the flag signal generation circuit 13 sets the write busy flag signal to low level, and the control signal generation circuit 16 sets the write enable signal and the chip select signal to high level. on the other hand,
The program in the program storage circuit 17 polls the write busy flag signal by the buffer circuit 15 by writing data to the data latch circuit 12, and does not write the next data while the write busy flag signal is at a high level. . As a result, data is correctly written. The synchronous-type two-port RAM30, when the chip select signal and output enable signal are both low level, data is read in synchronization with the rising edge of the synchronous clock. In order to satisfy this condition, the program in the program storage circuit 17 must be synchronized with the synchronous 2-port R to be read out to the address latch circuit 11.
Write address value of AM30 and generate flag signal
14 is requested to read. This request flag signal generating circuit 14 sets a read error Neiburu flag signal to the high level, the control signal generating circuit 16 A
The output enable signal and the chip select signal are set to low level. When the synchronous clock rises, the flag signal generation circuit 14 sets the read enable flag signal to a low level. On the other hand, the program storage circuit 17
Is polling the read enable flag signal by the buffer circuit 15 after the request, and does not read the data of the synchronous 2-port RAM 30 while the read enable flag signal is at a high level. When the read enable flag signal goes low, the program in the program storage circuit 17 reads the data in the synchronous 2-port RAM 30 by the buffer circuit 18, and the control signal generation circuit 16 sets the output enable signal and the chip select signal to high. To level. This allows
Data is correctly Ru read.

[0012]

As described above, the present invention enables a synchronous 2-port RAM to be read and written by an asynchronous CPU, and provides an interface circuit between the CPUs and other peripheral circuits equivalent thereto. When configuring an interface circuit with a circuit, there is an effect that an LSI including a synchronous 2-port RAM can be used.

[Brief description of the drawings]

FIG. 1 is a block diagram showing the overall configuration of an embodiment of the present invention.

FIG. 2 is a block diagram showing a partial configuration of the embodiment of the present invention.

FIG. 3 is a block diagram showing a partial configuration of the embodiment of the present invention.

FIG. 4 is a block diagram showing a partial configuration of the embodiment of the present invention.

FIG. 5 is a block diagram showing a partial configuration of the embodiment of the present invention.

FIG. 6 is a block diagram showing a partial configuration of the embodiment of the present invention.

FIG. 7 is a block diagram showing a partial configuration of the embodiment of the present invention.

FIG. 8 is a block diagram showing a configuration of a conventional example.

FIG. 9 is a timing chart showing write and read timings of the asynchronous two-port RAM.

FIG. 10 is a timing chart showing write and read timings of a synchronous two-port RAM.

FIG. 11 is a timing chart showing the timing of synchronous writing in the embodiment of the present invention.

FIG. 12 is a timing chart showing the timing of synchronous reading in the embodiment of the present invention.

[Explanation of symbols]

 Reference Signs List 10 interface circuit 11 address latch circuit 12 data latch circuit 13, 14 flag signal generation circuit 15 buffer circuit 16 control signal generation circuit 17 program storage circuit 18 buffer circuit 20 CPU 30 synchronous 2-port RAM

──────────────────────────────────────────────────続 き Continuation of front page (56) References JP-A-3-129452 (JP, A) JP-A-63-29854 (JP, A) JP-A-62-125446 (JP, A) JP-A-61-125 183770 (JP, A) JP-A-61-138358 (JP, A) JP-A-59-72552 (JP, A) JP-A-60-15763 (JP, A) (58) Fields investigated (Int. ^6, DB name) G06F 13/18 510 G06F 12/00 570 G06F 15/16 350 G11C 11/41

Claims (1)

(57) [Claims] 1. Reading from a CPU that operates asynchronously
An interface circuit interposed between the CPU and a synchronous two-port RAM in which writing is performed; a circuit for latching an address to be read and written by the CPU; a circuit for latching data to be written; A first buffer circuit for reading out the data, a circuit for generating a write busy flag signal indicating that data is being written to the synchronous 2-port RAM, and a read enable flag signal indicating that the data to be read is valid. A second buffer circuit for reading the write busy flag signal and the read enable flag signal; and a circuit for generating a chip select signal, an output enable signal, and a write enable signal for the synchronous 2-port RAM. The second buff above Loading the write busy flag signal and the read error Neiburu flag signal through a circuit, and a program storage circuit <br/> determining the timing of the read and write, in said program storage circuit based on the clock input
Read and write at specified timing
When writing, the chip select signal and the
Keep the enable signal for a predetermined time and read it out.
In this case, the chip select signal and output energy
An interface circuit for holding an Ibble signal for a predetermined timing time .