JPH0756860A - Multi-cpu system - Google Patents

Abstract

PURPOSE:To provide the multi-CPU system which can accelerate inter-CPU data transfer speed. CONSTITUTION:This multi-CPU system is provided with an address coupling buffer 6 connected between a main CPU address bus 2 and a sub CPU address bus 15, data coupling buffer 7 connected between a main CPU data bus 3 and a sub CPU data bus 16, control signal generating buffer 8 connected between a main CPU control bus 4 and a sub CPU control bus 17, and memory device 18 to which the sub CPU address bus 15, data bus 16 and control bus 17 are connected, and when performing access from a main CPU 1 to the memory device, the access is performed while conducting the respective buffers.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a multi-CPU system for transferring data between a plurality of CPUs.

[0002]

2. Description of the Related Art Conventionally, a memory device for a sub CPU is closed in a sub CPU system and cannot be directly accessed by a main CPU. Therefore, the sub-CP
When the main CPU accesses the data in the U memory device, a common memory device is provided for the main CPU and the sub CPU, and data transfer is performed via this common memory device. For example, the sub CPU transfers data from its own memory to a common memory, and the main CPU accesses the transferred data to transfer the data.

[0003]

Conventionally, there have been the following problems. <A> There are many steps for transferring data between CPUs, and much time is required for data transfer. <B> When the processing capacities of the CPUs are different from each other, the data transfer rate is influenced by the performance of the CPU having a low processing capacity, and thus the overall performance is deteriorated. <C> As the number of data items that need to be transferred increases, software needs to be added and modified, and the software creation time increases.

[0004]

SUMMARY OF THE INVENTION It is an object of the present invention to provide a multi-CPU system capable of increasing the data transfer rate between CPUs. Another object of the present invention is to provide a system in which the first CPU can freely transfer required data to the second CPU side when needed.

[0005]

The present invention provides a plurality of CPs.
First CPU in a multi-CPU system including U
Gate circuit connected between the address bus of the second CPU and the address bus of the second CPU, a second gate circuit connected between the data bus of the first CPU and the data bus of the second CPU, and a control signal bus of the first CPU A third gate circuit connected between the control signal bus of the second CPU and the control signal bus of the second CPU, and a memory device for the second CPU to which an address bus, a data bus for the second CPU, and a control signal bus are connected. When accessing the memory device for 2 CPUs, the second CP
U is a multi-CPU system characterized by opening the address bus, data bus and control signal bus of the second CPU to the first CPU, and opening the first to third gate circuits, or the first CPU is the main CPU, In the multi-CPU system, the second CPU is a sub CPU.

[0006]

Embodiments Embodiments will be described below with reference to the drawings. <B> Outline of multi-CPU system The main CPU 1 is, as shown in FIG.
It is connected to the PU buses 2 to 4, and the sub CPU 11 is connected to the sub CPU buses 15 to 17. Sub CPU
A memory device 18 is connected to the buses 15 to 17.
The main CPU buses 2 to 4 and the sub CPU buses 15 to 17 are connected via buffers 6 to 8.

The main CPU 1 has a high processing capacity and can take a large memory area. 2 to 3 sub-CP
An outline of transferring data from the memory area (map) of U11 to the memory area (map) of the main CPU 1 will be shown. By mapping a part (see FIG. 2) or the whole (see FIG. 3) of the memory map on the sub CPU side on the memory map on the main CPU side, the main CPU 1 can transfer data to the sub CPU 11 like a DMA controller. And
It is completed as an individual system except during the period when data is transferred. When the whole is mapped, sub C
Required data can be transferred to all functions controlled by the PU. For example, the main CPU is the sub-CP
The external input / output data of U can be transferred when necessary, and the communication protocol with the sub CPU is unnecessary.

<B> Main CPU The main CPU 1 is connected to a main CPU address bus 2, a main CPU data bus 3, and a main CPU control bus 4. Although not shown, peripheral devices such as an input / output device and a memory device are connected to the main CPU 1 via the buses 2 to 4 and are controlled under the main CPU.

<C> Sub CPU The sub CPU 11 includes a sub CPU address bus 15, a sub CPU data bus 16, and a sub CPU control bus 1.
Connected to 7. The memory device 18 has buses 15 to 1
It is connected to the sub CPU 11 via 7. Other than that, peripheral devices such as an input / output device (not shown) are connected to the sub CPU 11 via the buses 15 to 17 and controlled under the sub CPU. Sub CPU 11
Is the internal address buffer 12 and the internal data buffer 1
3. It has an internal control signal generation buffer 14. The sub CPU 11 has a terminal for receiving a transfer start request signal and a terminal for outputting a permission signal.

<D> Buffers Between Buses In order to transfer data between the main CPU 1 and the sub CPU 11, the buses 2 to 4 for the main CPU and the buses 15 to 17 for the sub CPU via the buffers 6 to 8. It is connected. Both address buses are through the address combination buffer 6,
Both data buses are connected via a data combining buffer 7, and both control buses are connected via a control signal generating buffer 8.

When the addresses of the main CPU 1 and the sub CPU 11 are different from each other, for example, the lower addresses are made common, or the addresses are converted to obtain consistency. The data bus width is converted according to the memory device on the sub CPU side. Further, the control bus is configured so that the control signal generation buffer 8 operates in the same manner as the sub CPU.

A permission signal line 10 is connected to each of the buffers 6 to 8, and a high impedance cutoff state or a normal buffer state is obtained by a signal on the permission signal line 10.
The wait signal line 19 is connected to the main CPU 1 from the control signal generation buffer 8 and sends a transfer wait signal to the main CPU.

<E> Decoder The decoder 5 is connected to the main CPU address bus 2 and the decoding result is output to the sub CPU 11 via the request signal line 9. The main CPU 1 of the decoder 5 is a sub CP
Used when U11 is requested to access or when it is stopped, it decodes the address signal from the main CPU 1 and, in the case of the corresponding address, requests access to the sub CPU 11.

An example of the procedure of data transfer between CPUs will be described below. <A> Data read from the sub CPU side In order to make a data transfer request to the sub CPU 11, as shown in FIG. 4, the main CPU 1 outputs a predetermined address signal to the address bus 2 at the time t1. , The data bus 3 and the control bus 4 are opened for reading data.

After time t1, the decoder 5 decodes the address signal and outputs a transfer start request signal to the request signal line 9. At time t2, the sub CPU 11 receives the transfer start request signal, and if the request can be accepted, outputs the transfer start permission signal to the permission signal line 10 and reads the data from the sub CPU buses 15 to 17 for data reading. Open to. The permission signal line 10 is connected to the address combination buffer 6, the data combination buffer 7, and the control signal generation buffer 8 to which a transfer start permission signal is applied.

When the transfer start permission signal is given to each of the buffers 6 to 8, at time t2, each buffer changes from the high impedance state to the normal buffer state, and the buses 2 to 4 for the main CPU and the bus for the sub CPU are provided. 15 to 17 are connected, the main CPU side accesses the memory device 18 on the sub CPU side, and the data in the memory device is transferred to the main C
It is read to the PU side.

When the reading is completed, at the time t4, the end signal is output from the sub CPU to the permission signal line 10 by the signal of the request signal line 9, and the address combination buffer 6, the data combination buffer 7 and the control signal generation buffer 8 are supplied. Is entered.

When a signal for termination is given to each of the buffers 6 to 8, at time t5, each buffer becomes high impedance, and the buses 2 to 4 for the main CPU and the buses 15 to 17 for the sub CPU are cut off. , Each bus is main C
Open to PU and sub CPU. Then, at time t6, the main CPU starts the next operation.

When the access speed of the sub CPU 11 is lower than that of the main CPU 1, the control signal generation buffer 8 outputs the transfer wait signal 19 to the main CPU via the wait signal line 19.

<B> Data Writing to Sub CPU Side In order to transfer data to the sub CPU 11, as shown in FIG. 5, the main CPU 1 outputs a predetermined address signal to the address bus 2 at time t1. Data bus 3
Write data is output to and the control bus 4 is opened for writing data.

After time t1, the decoder 5 decodes the address signal and outputs a transfer start request signal to the request signal line 9.

At time t2, the sub CPU 1 receives the transfer start request signal, and if the request can be accepted, it outputs the transfer start enable signal to the enable signal line 10 and the buses 15 to 17 for the sub CPU. Open for writing data. The permission signal line 10 is connected to the address combination buffer 6, the data combination buffer 7, and the control signal generation buffer 8 to which a transfer start permission signal is applied. When the transfer start permission signal is given to each of the buffers 6 to 8, the main CPU buses 2 to 4 are transferred at time t2.
And the sub CPU buses 15 to 17 are connected.

At time t3, the memory device 18 on the sub CPU side is accessed by the write control command of the main CPU control bus 4, and data is written to the memory device 18 from the main CPU side.

At time t4, the write control command of the main CPU control bus 4 is inverted and the writing is completed. A signal on the request signal line 9 causes a signal to be output from the sub CPU to the permission signal line 10 and input to the address combination buffer 6, the data combination buffer 7, and the control signal generation buffer 8.

When a signal for termination is given to each of the buffers 6 to 8, the buses 2 to 4 for the main CPU and the buses 15 to 17 for the sub CPU are cut off at time t5, and each bus is
Each is open to the main CPU and sub CPU.

When a signal for termination is given to each of the buffers 6 to 8, at time t6, each buffer becomes high impedance, and the buses 2 to 4 for the main CPU and the buses 15 to 17 for the sub CPU are cut off. , Each bus is main C
Open to PU and sub CPU. Then, at time t7, the main CPU starts the next operation.

The grid-like waveforms in FIGS. 4 to 5 indicate that it is unknown whether the waveform is high (high) or low (low). Also, the waveforms of the address combination buffer, the data combination buffer, the control signal generation buffer, the internal address buffer, the internal data buffer, and the internal control signal generation buffer in FIGS. 4 to 5 indicate the signals output from these buffers. There is.

[0028]

According to the present invention, the following effects can be obtained. <B> Regardless of the difference in CPU power, it is possible to transfer data according to the power of the CPU capable of high-speed processing, and it is possible to improve the processing speed of the entire system. <B> Special communication means (protocol) because data can be transferred from the main CPU to the sub CPU at any time
Is unnecessary.

[Brief description of drawings]

[Figure 1] Connection diagram of multiple CPUs

FIG. 2 is a diagram for transferring partial data from the sub CPU side to the main CPU side.

FIG. 3 is a diagram for transferring all data from the sub CPU side to the main CPU side.

FIG. 4 is a time chart diagram of reading from a sub CPU.

FIG. 5 is a time chart diagram of writing to a sub CPU.

Claims (2)

[Claims] 1. In a multi-CPU system including a plurality of CPUs, a first gate circuit connected between an address bus of a first CPU and an address bus of a second CPU, a data bus of the first CPU and a data bus of the second CPU. A second gate circuit connected between the second CPU, a third gate circuit connected between the control signal bus of the first CPU and the control signal bus of the second CPU, an address bus for the second CPU, a data bus, and a control signal A second CPU memory device to which a bus is connected, and when the first CPU accesses the second CPU memory device, the second CPU opens the address bus, data bus and control signal bus of the second CPU to the first CPU, A multi-CPU system characterized by opening first to third gate circuits. 2. A multi-CPU system according to claim 1, wherein the first CPU is a main CPU and the second CPU is a sub-C.
A multi-CPU system characterized by being a PU.