JP2610971B2 - Direct memory access method between central processing units - Google Patents

Description

The present invention relates to a communication system between central processing units (CPUs).
In particular, it relates to a method for directly accessing the memory space of the partner CPU.

[Conventional technology]

Conventionally, when data is sent and received between two CPUs, serial or parallel communication ports are prepared for each CPU.
Is a method of performing a data communication after executing a protocol with a partner CPU using this communication port.

[Problems to be solved by the invention]

The conventional port-based communication method described above is communication through the input / output devices of each CPU, and requires the intervention of each CPU, which takes time for communication. Especially when the data amount is small, the own protocol is used for communication. Efficiency is extremely poor because it occupies most of the time.

Further, there is a problem that not only the cost is increased because the input / output device is required, but also software for operating the input / output device and determining a protocol is required.

[Means for solving the problem]

In the direct memory access method between central processing units of the present invention, two central processing units connect memories corresponding to the respective central processing units via respective system buses, and the respective central processing units mutually communicate with each other's central processing unit. A memory access method in a distributed processing device having a configuration capable of accessing a memory of a processing device, characterized by having the following configuration.

(1) Connected to the system bus of the own central processing unit and the other central processing unit via a gate circuit, and sends out a hold request output from the own central processing unit and requesting release of the system bus of the other central processing unit. , The other central processing unit
At the same time, the hold request is received through the gate circuit that is opened when the hold request is not made, and the other central processing unit releases the corresponding system bus and sends a hold acknowledgment to the own central processing unit. (2) an address buffer interconnected to the own system bus and the partner system bus and enabled based on the hold approval; (3) the central processing of the own central processing unit based on the hold approval Stop access to the memory corresponding to the device,
Gate circuit means for opening an enable signal input circuit of the data buffer mutually connected to the own system bus and the other system bus; (4) the data buffer recognizes the hold approval via the system port; (5) The address and data output from the own central processing unit are sent to the partner system bus via the address buffer and the data buffer, respectively, and the address is stored in the memory of the own central processing unit. Access the corresponding memory space of the central processing unit.

〔Example〕

 Next, the present invention will be described with reference to the drawings.

 FIG. 1 is a block diagram showing an embodiment of the present invention.

CPU1 and CPU2 have system buses 3 and 4, respectively. CPU2 holds CPU1 from system port (SYSTEM PORT) 5 connected to system bus 4 (HOLD)
Upon receiving the HOLD request, the CPU 1 issues a HOLD acknowledgment 7 to the system port 5 and releases the system bus 3. The HOLD acknowledgment signal 7 enables the address buffer 8, thereby allowing the system bus 4 to enter the system bus 3.

Further, the HOLD approval signal 7 opens the gate of the gate circuit 9 and closes the gate of the gate circuit 10. The CPU 2 recognizes the HOLD approval signal 7 by scanning the system port 5 and outputs the corresponding address to the system bus 4 to access the memory 11 in the memory space of the CPU 2. As a result, the address decoder (ADD DEC) 12 decodes the address and outputs the decoding result to the gate circuits 9 and 10. This time,
The gate circuit 9 forms a logical product between the decoded result and the HOLD acknowledgment signal 7, and enables the data buffer 13. The corresponding address issued by the CPU 2 is transmitted to the system bus 3 through the address buffer 8, and the address decoder 14 of the CPU 1 selects the memory (MEM) 15, and the CPU 2
Can access the memory 15 on the CPU 1 side.

The access end is completed when the CPU 2 releases the HOLD request 6 and the HOLD approval signal from the CPU 1 becomes inactive.

After completion, system buses 3 and 4 are connected to CPU 1 and 2 respectively.
And the memory 15 is arranged in the memory space of the CPU 1 and the memory 11 is arranged in the memory space of the CPU 2.

FIG. 2 shows the memory space state at this time. That is, FIG. 2A is a memory space of the CPU 1, and FIG.
6 is a memory space map of CPU2.

When the system bus of CPU1 is occupied by CPU2
FIG. 3 shows a memory space map of the CPU2. That is, from CPU2
This shows a state where the memory of the CPU 1 (the memory 15 in FIG. 1) is accessible.

In FIG. 1, the HOLD acknowledgment signal is
However, after the CPU 2 recognizes this signal, it is also possible to output it from another port.

 Next, a second embodiment of the present invention is shown in FIG.

This is an example of enabling access from both CPUs. In FIG. 4, the circuits existing on the CPU 2 side in FIG. 1 are provided symmetrically on the CPU 1 side and are accessible from both CPUs.

The first symmetrical circuit is system port 16,
Next, there are the gate circuits 17, 18 and the address decoder 19.
The added circuits are gate circuits 20 and 2 for enabling the address buffer and the data buffer from both.
1 and has the function of OR.

Further, in this embodiment, gate circuits 22 and 23 are provided for simultaneously issuing HOLD requests to each other to prevent deadlock. The gate circuits 22 and 23 gate a HOLD request from the other party and are controlled from the system ports 5 and 16. That is, each CPU can prevent collision by activating this signal when a HOLD request from the other party can be accepted.

〔The invention's effect〕

As described above, according to the present invention, by temporarily occupying the other system bus between the two CPUs,
Fetch a part of the other party's memory into their own memory space,
It allows direct access. This results in CPU
This has the effect that data transfer between them can be realized at high speed and without software for processing complicated protocols.

[Brief description of the drawings]

FIG. 1 is a diagram showing a first embodiment of the present invention, FIGS. 2 and 3 are diagrams showing a memory space map of each CPU in FIG. 1, and FIG. 4 is a second embodiment of the present invention. FIG. 1,2 CPU, 3, 4 System bus, 5, 16 System port (SYSTEM PORT), 6 HOLD request signal, 7 HOLD acknowledgment signal, 8 Address buffer, 9, 10 , 17,18 …… Gate circuit (control circuit), 11,15 …… Memory (MEM), 12,14,19
... Address decoder (ADD DEC), 13 Data buffer, 20 OR circuit, 21 OR circuit, 22, 23 HOLD request gate circuit.

Claims (1)

(57) [Claims] 1. Central processing units (1, 2) connect memories (15, 11) corresponding to respective central processing units via respective system buses (3, 4), and each central processing unit (1, 2) The device is a memory access method in a distributed processing device configured to be able to mutually access the memory of the other central processing unit.
Is connected to the other central processing unit via the CPU, and sends a hold request output from the own central processing unit requesting release of the system bus of the other central processing unit, and the other central processing unit simultaneously issues a hold request. A system port (5 or 16) for receiving the hold request via the gate circuit which is opened when not open, and relaying a hold acknowledgment for releasing and sending the system bus of the partner central processing unit to the own central processing unit; An address buffer (8) interconnected to the system bus of the own central processing unit and the system bus of the partner central processing unit and enabled based on the hold approval; Stop access to the memory corresponding to the own central processing unit,
A data buffer (13) interconnected to the system bus of its own central processing unit and the system bus of the partner central processing unit
Gate circuit means (9, 10) for opening the enable signal input circuit of
Or the data buffer is enabled based on an address output from the own central processing unit that has recognized the hold approval via the system port, and an address output from the own central processing unit. The data is sent to the system bus of the partner central processing unit via the address buffer and the data buffer, respectively, and the corresponding memory space of the partner central processing unit is accessed with the address of the memory of the partner central processing unit. Characteristic direct memory access method between central processing units.