JPH02146667A - Inter-cpu direct memory access system - Google Patents

Abstract

PURPOSE:To partly fetch a memory of the remote side into its own memory space and to realize a direct access by occupying temporarily the system bus of the remote side between two CPUs. CONSTITUTION:A system port 5 gives a HOLD request 6 to a CPU 1 of the remote side and receives the HOLD approval 7 from the CPU 1. An address buffer 8 and a data buffer 13 function to connect its own system bus to the system bus of the remote side based on the approval 7 received from the CPU 1. Then the control circuits 9 and 10 secure the accesses to a memory 15 of the remote side while the CPU 1 is delivering the approval 7 for a partial address space of a memory of its own CPU 2. Thus the data can be transferred at a high speed between both CPU 1 and 2 with no complicated protocol needed.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a communication system between central processing units (CPUs), and particularly to a system for directly accessing the memory space of the other CPU.

[Conventional technology]

Conventionally, when sending and receiving data between two CPUs, serial or parallel communication ports were prepared for each CPU, and each CPU
After the PU uses this communication port to implement a protocol with the other CPU.

It is a method for data communication.

[Problem that the invention seeks to solve]

The conventional port-based communication method described above communicates through the input/output devices of each CPU, and requires intervention from each CPU, so communication takes time. Especially when the amount of data is small, communication using a proprietary protocol is better. It is extremely inefficient as it takes up most of the time.

Furthermore, since it requires an input/output device, it not only increases costs, but also requires software to operate the input/output device and determine the protocol.

[Means for solving problems]

The CPU-to-CPU direct memory access method of the present invention sends a HOLD request to the other CPU and receives a HOL request from the other CPU.
It has a system port that receives D-acknowledgment, by the HOLD acknowledgment signal from the other CPU.

There is a bias between address buffers and data buffers that connect the own system bus to the other system bus.

The other CPU uses a part of the memory address space of its own CPU
It is characterized by having a control circuit that allows access to the other party's memory while the OLD approval is issued.

〔Example〕

Next, the present invention will be explained with reference to the drawings.

FIG. 1 is a block diagram showing an embodiment of the present invention.

CPUI and CPU2 are connected to system buses 3 and 4, respectively.
It is equipped with The CPU 2 is connected to the CPU from the system port (SYSTEM PORT) 5 connected to the system bus 4.
A hold (HOLD) request is sent to the UI, and the CPU UI accepts this HOLD request.

The HOLD approval 7 is sent out toward the system port 1-5, and the 7 stem bus 3 is released. The HOLD acknowledge signal 7 enables the address buffer 8, thereby
The system bus 4 can be connected to the system bus 3.

Furthermore, the HOLD approval signal 7 is sent to the CPU 2 of the gate circuit 9.
recognizes the HOLD acknowledge signal 7 by scanning the system port 5 and stores the memory 11 in the memory space of the CPU 2.
The corresponding address is output to the system bus 4 in order to access the address. This allows the address decoder (ADD DE
C) 1.2 decodes the address and outputs the decoded result to gate circuits 9 and 10. At this time, the gate circuit 9 performs an AND between the decoding result and the HOLD approval signal 7, and enables the data buffer 13.

The corresponding address issued by the CPU 2 is transmitted to the system bus 3 through the address buffer 8.

Address decoder 14 on the CPUI side is memory (MEM)
]5 is selected, and the memory 15 on the CPUI side can be accessed from the CPU 2.

To end the access, CPU2 releases HOLD request 6,
This is completed when the HOLD acknowledge signal from the CPUI becomes inactive.

After completion, the system buses 3 and 4 are returned to the CPUI and 2, respectively, and the memory 15 is placed in the memory space of the CPUI K and the memory 1]uCPU2.

FIG. 2 shows the state of the memory space at this time. That is, FIG. 2(a) shows the memory space of CPUJ.

FIG. 2(b) is a memory space map of the CPU 2.

FIG. 3 shows a memory space map of the CPU 2 in a state where the CPU 2 system bus is occupied by the CPU 2. That is, the memory from CPU2 to CPUUI (memory 15 in FIG.
) indicates that it is accessible.

In FIG. 1, the HOLD acknowledge signal is directly input to the address buffer 8 and gate circuits 9 and 10, but the CP
After U2 recognizes this signal, it is also possible to output it from another port.

Next, a second embodiment of the present invention is shown in FIG.

This is an example in which access is enabled from both CPUs. In Figure 2, the circuit existing on the CPU2 side in Figure 1 is installed symmetrically in the CPU1111tl, and both CPU2
It is accessible from PU.

First, the circuit placed symmetrically is system port 16 and 2
Next are gate circuits 17 and 18 and address decoder 19. The added circuits are gate circuits 20 and 21 for enabling the address buffer and data buffer from both, and have a logical OR function.

Further, in this embodiment, gate circuits 22 and 23 are provided for simultaneously issuing HOLD requests to each other to prevent deadlock. This gate circuit 22° B is used to gate HOLD requests from the other party, and is controlled from each system port 5, 16. That is, each CPU can prevent collision by activating this signal when it can accept a HOLD request from the other CPU.

〔Effect of the invention〕

As explained above, in the present invention, by temporarily occupying the system bus of the other party between two CPUs, it is possible to import a part of the other party's memory into its own memory space and directly access it. This result C
This has the advantage that data transfer between PUs can be achieved at high speed without the need for software that processes complex protocols.

Address buffer, 9, 10, 1.7.18... Gate circuit (control circuit), 11.15... Memory (ME
M), 12,14゜19...address decoder (A
DDDEC), 13... data buffer, 20...
・OR circuit, 21...OR circuit.

22.23...HOLD request gate circuit.

[Brief explanation of the drawing]

FIG. 1 is a diagram showing a first embodiment of the present invention, FIGS. 2 and 3 are diagrams showing a memory space map of each CPU in FIG. 1, and FIG. 4 is a diagram showing a second embodiment of the present invention. FIG.

Claims (1)

[Claims] 1. Used in a distributed processing device using two central processing units, where one central processing unit sends a hold request to the other central processing unit and the other central processing unit issues a hold approval to the one central processing unit. a second means for connecting a system bus of said one central processing unit to a system bus of said other central processing unit based on said hold approval; and third means for making a predetermined address space of the memory accessible to the memory of the other central processing unit.