JPH0232432A - Control system for dual port memory - Google Patents

Abstract

PURPOSE:To improve the processing speed without stopping the action of one side CPU by providing a bank control means, switching alternately the bank which can be accessed by respective CPUs and permitting a memory access to respective CPUs. CONSTITUTION:A CPU 101, when initialization is completed, outputs a bank switching permitting signal (b) to a bank control part 600. On the other hand, a CPU 102, when the access for refreshing is completed, outputs an access completing signal to the control part 600. Thus, the control part 600 inverts an address upper-most order bit signal (a) on a signal line 701. By the code of the signal a0, the processing is executed in a dual port memory 200 as the upper-most order bit on an address bus 301 or 302. Consequently, the coincidence of the address on the memory 200 can be avoided, the generation of the waiting time due to the stoppage of one side CPU can be prevented and the processing speed can be improved.

Description

DETAILED DESCRIPTION OF THE INVENTION (Field of Industrial Application) The present invention relates to a control method for a dual port memory for exchanging data between two CPUs.

(Prior Art) Conventionally, the system shown in FIG. 3 is known as a system that exchanges data between two CPUs using a dual port memory. In the same figure, 101.102 is C
PU, 200 is a dual port memory (dual port RAM; hereinafter simply referred to as memory), 301, 302 are address buses, 401.402 are data buses, 501, 5
02 is a signal line, CP UIOI, 102 is an address bus 301, 302 and a data bus 401, respectively.
402 is used to access the memory 200 and write and read data.

In such a configuration, the address bus 301,
If the addresses indicated by 302 are different, CPULot,
102 and the memory 200 are performed in parallel, but when these addresses match, the memory 200 sends a BUS signal to the CPU 101 or 102 accessed later via the signal line 501 or 502.
It is known to arbitrate access rights by sending a Y signal to temporarily stop the operation of the destination CPU.

(Problem M to be solved by the invention) However, according to this method, the operation of one CPU stops every time the addresses match, and the
There was a problem in that the processing speed of the PU decreased. Furthermore, since the CPUs 10I and 102 access any address on the memory 200 asynchronously and independently,
There were also drawbacks such as the inability to synchronize data between CPU10I and CPU102.

The present invention was proposed in order to solve the above problems, and its purpose is to avoid stopping the operation of one CPU even when the addresses on the address bus from each CPU match. An object of the present invention is to provide a control method for a dual port memory that improves processing speed and also makes it possible to ensure data synchronization between CPUs.

(Means for Solving the Problems) In order to achieve the above object, the present invention provides a bank control unit for switching between two banks of a dual port memory between CPUs that exchange data, and this bank control unit: Banks that can be accessed by each CPU are alternately switched on the condition that a dual-port memory bank switching permission signal output from one CPU and a memory access end signal output from the other CPU are input. It is characterized in that in addition to switching, access to the memory by each CPU is permitted.

(Function) According to the present invention, the banks that can be accessed by each CPU are alternately switched, so even if the addresses on the address bus of each CPU match, the addresses on the dual port memory will be different, and each Access from the CPU becomes valid.

In addition, since the bank control unit switches memory banks by handshaking that confirms the puncture switching permission signal accompanying the end of access by one CPU and the end signal of access by the other CPU, each CPU
It is possible to synchronize data exchanged between the two via memory.

(Example) An embodiment of the present invention will be described below with reference to the drawings.

In FIG. 1, similarly to the above, 101 and 102 have CPUs for exchanging data, and 200 has two banks. Dual port memory (dual port RAM), 301
, 302 are address buses, and 401, 402 are data buses, and the CPU IO I, 102 can access the memory 200 through the address buses 301, 302, and data buses 401, 402, respectively. Further, 600 is a bank control unit, which transmits an address most significant bit signal a0 from a signal line 701 to the memory 20 as described later.
This is for switching the bank of the memory 200 by sending the data to 0. A sign inverter 80 is connected to the signal line 701.
0 is provided, and in addition to the signal a0, its inverted signal is added to the most significant bit of the address of the memory 200.

In addition, a puncture switching permission signal is sent to the bank control unit 600 from one CPU l0I via a signal @702, and a blowout switching permission signal is sent from the other CPU 102 via a signal line 703.
The access end signal C from 102 is inputted, and furthermore, an interrupt signal d to the CPU 101 is outputted via a signal line 704.

Next, the operation of this embodiment will be explained with reference to the second timing chart. First of all, CPU10I.

When initialization such as IPL (initial program load) is completed, a puncture switching permission signal S is output to the bank control section 600 from time t1 in FIG.

On the other hand, the CPU 102 has been accessing one bank A of the memory 200 for data refresh since time t2, and this access is at time t.

At the same time, the access end signal C is output to the bank control section 600. At this point, the bank control unit 60
0 confirms the presence of the puncture switching permission signal from the CPU 101 and inverts the address most significant bit signal a on the signal line 7. This signal a0 is the address bus 301
Since it is processed in the memory 200 as the most significant bit of the above address, in the memory 200, the C
Access from PUl0I becomes possible.

At the same time, signal a0 is sign inverted by sign inverter 800 and processed in memory 200 as the most significant bit of the address on address bus 302. Therefore, memory 20
0, the CPU 102 can access bank B which has an inverted signal (for example, 11111) of the signal a0 in the most significant bit. That is, time t.

The sign inversion of the signal a0 at is CP Ulol, 1
It functions to switch the bank accessible from 02 to the previous bank.

The bank control unit 600 clears the bank switching permission signal at time t4 after time t3, and at the same time
It outputs an interrupt signal d to. This signal is CPUIQ
The CPU 10I receives this signal d and accesses the bank A of the memory 200 (the bank that had been accessed by the CPU 102 up to that point) at time t.

If an access from the CPU 102 is made at time t6 during this access period, if the address bus 3
Even if the addresses on 01.302 are the same, the signal a. And the inverted signal causes the CPU 102 to access a bank B different from CPUl0I, and the access becomes valid.

Then, when the access by the CPU 101 ends at time t7, the CPU 10I outputs the bank switching permission signal S again, and the bank control unit 600 outputs the bank switching permission signal S and the access completion signal C from the CPU 102 at the time t0. By confirming this and inverting the sign of the signal a0 again, each CPU10I, 102
The banks that can be accessed are alternately switched. Thereafter, banks are alternately switched in the same manner every time access to a different bank by the CPUs 10I and 102 is completed.

In this way, according to this embodiment, the signal a0 is used to
By avoiding an address match on memory 200 by Ul0I, 102, CPUl0I.

102 can perform memory access in parallel,
There is no inconvenience that the operation of the CPU 101 or 102 is stopped due to a match between the addresses on the address buses 301 and 302. In addition, the bank control unit 600
Since the handshake between the CPU 102 and the CPU 102 is performed by inputting and outputting the bank switching permission signal b, the access end signal C, and the interrupt signal d with the CPU 102, there is no communication between the CPU 102 and the memory 200. The continuity of data is maintained, and it becomes possible to synchronize data between the CPU IOI and 102 during data refresh.

(Effects of the Invention) As described above, according to the present invention, it is possible to avoid matching of addresses on the dual port memory from each CPU by the action of the bank control unit. This can prevent the occurrence of
The processing speed can be significantly improved. Furthermore, since the timing of bank switching is determined by handshaking between each CPU, it is possible to ensure synchronization for one digital refresh.

[Brief explanation of the drawing]

1 and 2 show one embodiment of the present invention. FIG. 1 is a block diagram showing a control circuit of a dual port memory to which this embodiment is applied, together with a CPU, and FIG. 2 is a block diagram showing the operation. FIG. 3 is a block diagram showing the connection state of the CPU and dual port memory to explain the drawbacks of the conventional example. 101.102...CPU 200...Dual port memory 301.302...Address bus 40
1,402...Data bus 600...Bank control section 701,702,703,704...Signal line 800
...Sign inverter

Claims (1)

[Claims] In a control method for a dual port memory that is used for data exchange between two CPUs and has two banks that can be accessed by these CPUs, a bank control section is provided between the CPUs, and the bank control section is provided between the CPUs. The control unit is configured to control the memory bank switching permission signal outputted from one CPU and the memory access end signal outputted from the other CPU on the condition that the memory bank switching permission signal outputted from one CPU and the memory access end signal outputted from the other CPU are input. A control method for a dual port memory, characterized in that banks are alternately switched and each CPU is allowed to access the memory.