JPH0215094B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention provides a control system for a multiprocessor device,
In particular, the present invention relates to a control method for a multiprocessor device in distributed processing of a data processing device.

Conventionally, in a multiprocessor device using a plurality of processors, as shown in FIG.
There is a method in which a slave processor 4 equipped with a common memory 3 and its control circuit 2 is coupled to a bus line 5 of the processor, and a method in which a plurality of processors are coupled by using a bus line in common by time sharing. It has been adopted.

However, the former method has the advantage that there is no restriction on the operation because it does not interfere with each other's operations, but it requires a common memory and its control circuit to be provided as hardware, and input/output Linking is done by instructions, which has the disadvantage of making the software complex.

On the other hand, the latter time sharing method requires a complicated control circuit and has drawbacks such as difficulty in combining a plurality of processors with different speeds.

That is, both are designed for systems in which multiple microprocessors have the same rights to shared memory and buses, making it difficult to develop the hardware and software to handle this.

The present invention has been made to solve the above-mentioned drawbacks, and it is an object of the present invention to more efficiently transfer data between one main microprocessor and a plurality of subordinate microprocessors connected thereto. This paper relates to a control method for a multiprocessor device.

Examples will be described below with reference to the drawings. Second
The figure is a block diagram of an embodiment for explaining the control method of a multiprocessor device according to the present invention.
The figure is a configuration diagram of one embodiment of the control circuit.

In FIG. 2, a control circuit 6 is connected to the main processor 1, memory and I/0 via a main bus line 15, and further connected to the slave processor 4 via a slave bus line 16. Inside the slave processor 4, there is a microprocessor (MPU) 4-1,
There is a memory 4-2, which is connected to an internal bus 16-2.
1, respectively.

Here, the slave processor 4 is configured to start processing when activated by the main processor 1 via the control circuit 6, and to stop after the processing is completed.
Therefore, the main processor 1 is similar to the slave processor 4.
During the stop period, the memory of the slave processor 4 can be accessed via the control circuit 6, and data can be exchanged between the main processor 1 and the slave processor 4. A control circuit is provided corresponding to each slave processor.

The control circuit will be explained with reference to FIG. FF is a flip-flop circuit consisting of logic elements 7 and 8. 9 is a NOT circuit, 10 is a bus switching circuit, 11 is a startup request signal from the main processor 1, 12 is a startup signal for the slave processor, 13
is a stop signal of the slave processor, 14 is a stop signal of the slave processor which is received by the main processor,
15 is a main bus line, and 16 is a sub bus line.

Now, when starting the slave processor 4, the signal 14 indicating that the slave processor 4 is stopped is used.
The main processor 1 confirms that the main bus line 15 is stopped, and if it is stopped, the stop signal 13 activates the bus switch 10 to connect the main bus line 15 to the slave bus line 16. In this case, the stopped slave processor 4 has a high impedance with respect to the slave bus line 16, so that the memory of the slave processor 4 can be accessed by the main processor 1, and necessary processing data can be transferred to the slave processor 4. The activation request signal 11 is output from the main processor 1 to the slave processor 4. This allows the flip
Flop circuit FF is set and slave processor 4
The activation signal 12 is generated, the slave processor 4 is activated, and the stop signal 13 is invalidated.

Therefore, the bus switch 10 disconnects the main bus line 15 and the slave bus line 16, the flip-flop circuit FF is reset, and the activation signal of the slave processor is invalidated.

When the slave processor 4 is activated, processing is performed according to the data from the main processor 1.
When the process is completed, it will stop by itself and stop signal 1
Generates 3. Therefore, the main processor 1 can perform other processing until it recognizes the stop signal 14 from the slave processor 4, and when the slave processor 4 stops, it retrieves the processing result from the memory of the slave processor 4 and starts the next process. I can make you do it.

Therefore, it can be seen that the present invention is particularly effective in systems where the slave processor does not need to constantly execute processing. This is because after the slave processor completes processing, it automatically stops and releases the internal bus to the main processor, making the memory in the slave processor accessible from the main processor, which is not necessary in the conventional common memory method. This is because a common memory control circuit and a common memory are not required, which simplifies the hardware configuration.Furthermore, since the main processor directly accesses the memory in the slave processor, this data is This is also because there is no need to add special software for sending and receiving.

As explained above, according to the present invention, in a multiprocessor control system using one main processor and a plurality of slave processors, a control circuit is provided that allows the main processor to access the memory of the slave processor while the slave processor is stopped. Because of this structure, the number of slave processors can be increased according to the processing capacity by simply adding a control circuit, which is advantageous when the processors have different processing speeds. Moreover, if the interrupt function of the processor is used, it is not only more effective, but also the control time for data exchange between processors can be shortened, and the distributed processing capacity can be further improved.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing a conventional multiprocessor device, FIG. 2 is a block diagram showing an embodiment of a control method for a multiprocessor device according to the present invention, and FIG. 3 is a block diagram of an embodiment of a control circuit. be. 1...Main processor (CPU), 2...Common memory control circuit (CNT), 3...Common memory (CM), 4...
Slave processor (CPU), 5...Main bus line, 6...
Control circuit (IF), 7, 8...NAND circuit, 9...
NOT circuit, 10...Bus switch, 11...Slave processor start request signal, 12...Slave processor start signal, 13...Slave processor stop signal, 14...Slave processor stop signal, 15...Main bus line, 16...
Slave bus line, FF...flip-flop circuit.

Claims (1)

[Claims] 1. In a control method for a multiprocessor device in which data is mutually transferred between a main processor and a plurality of slave processors via a data bus, each slave processor is provided with a control device, and during a period when the slave processors are stopped, A control system for a multiprocessor device, characterized in that data is exchanged between processors via the memory of the slave processor by making the memory of the slave processor accessible from the main processor.