JP2705955B2 - Parallel information processing device - Google Patents

Description

Description: BACKGROUND OF THE INVENTION The present invention relates to a parallel information processing apparatus in which a plurality of arithmetic units are connected by an interconnection path, and more particularly, to a parallel information processing device provided with a DMA controller provided in the arithmetic unit. The present invention relates to a parallel information processing device that realizes high-speed data transfer between memories between arithmetic units.

[Conventional technology]

2. Description of the Related Art In recent years, two or more arithmetic units
A parallel information processing apparatus has been widely used, which is connected by a bus), transfers data between arithmetic units as needed, and executes processing in parallel by sharing the processing among the arithmetic units. In this type of parallel information processing apparatus, when the contents of a memory (local memory) in a certain arithmetic unit are transferred to a memory (local memory) in another arithmetic unit, data is conventionally stored on a bus connecting the arithmetic units. In general, a method is provided in which a shared memory for relaying is provided and the process is performed via the shared memory.

FIG. 5 shows a configuration example of a data transfer method between memories in a conventional parallel information processing apparatus. In FIG. 5, a plurality of operation units 1, 2,... 9 are interconnected by a bus 104. The arithmetic unit 1 includes a central processing unit (CPU) 11, a local memory (MEM) 12, a bus interface circuit (BIF) 15
And are interconnected by a local bus 14. The same applies to the configurations of the other arithmetic units 2 to 9. The bus 104 is further connected to a shared memory (MEM) 10 used by each of the arithmetic units 1 to 9 for data relay. For example, when transferring data from the memory 12 in the arithmetic unit 1 to the memory 22 in the arithmetic unit 2, the CPU 11 in the arithmetic unit 1
Temporarily transfers the data in the memory 12 to the shared memory 10 via the bus interface circuit 15 and the bus 104, and instructs the arithmetic unit 2 to access the shared memory 10.
According to the instruction from the arithmetic unit 1, the CP of the arithmetic unit 2
U21 reads data from the shared memory 10 and stores it in the memory 22 via the bus 104 and the bus interface circuit 25.
Note that a buffer in the bus interface circuit in the arithmetic unit may be used instead of the shared memory 10.

On the other hand, in an information processing apparatus including a single arithmetic unit, a so-called direct memory access controller (DMA controller) for directly accessing a memory independently of a CPU operation has been conventionally used. FIG. 6 shows an example of the configuration, in which a CPU 11, a memory 12, and a DMA controller (DMAC) 13 are connected to a local bus 14.

A typical concept of the DMA controller is established in, for example, an LSI (product number 8237A) manufactured by Intel Corporation in the United States, and performs the following series of processing operations. That is, when the DMAC 13 acquires the right to use the bus from the CPU 11, the DMAC 13 successively generates memory addresses for both transmission and reception in accordance with a previously programmed sequence, and transfers data from a specific address of the memory 12 to another specific address of the memory 12. Are continuously performed, and when a series of data transfer ends, the bus use right is relinquished.

[Problems to be solved by the invention]

In the prior art, in the method using a shared memory for relaying, a CPU in a certain arithmetic unit temporarily transfers the contents of the memory to the shared memory, and a CPU in another arithmetic unit that knows this transfers the content from the shared memory to the shared memory. A two-stage process of transferring data to the memory again was necessary. Of course, such a method has the obvious disadvantage that the transfer requires a long time and the provision of a shared memory for relaying is also obvious. Disadvantages such as the necessity of arbitrating the right to use the bus, the complexity of the control circuit therefor, and the reduction in bus use efficiency, so that the arithmetic unit is not erroneously used by unrelated arithmetic units. Is recognized.

On the other hand, a method using a DMA controller is an effective method for performing high-speed data transfer between memories without going through a CPU, but conventionally, data transfer is limited to one bus (local bus). Was. For this reason, a parallel information processing apparatus having a plurality of arithmetic units cannot be used as it is.

An object of the present invention is to provide a method that is effective in a single arithmetic unit.
It is an object of the present invention to provide a parallel information processing apparatus which expands the function of a DMA controller and speeds up data transfer between memories across a plurality of arithmetic units.

[Means for solving the problem]

In order to achieve the above object, the present invention provides a parallel information processing device in which at least a processor, a memory, and a plurality of arithmetic units connected to a DMA controller for directly accessing the memory by a local bus are connected by an interconnect path. The DMA controller in each arithmetic unit
A function of acquiring or abandoning the right to use the local bus in the self-processing unit in response to a transfer request; a function of reading and writing a memory in the self-processing unit using the local bus;
A function to acquire or abandon the right to use the interconnecting path;
A function of sending an instruction to the DMA controller of another arithmetic unit via the interconnect path, and a function of acquiring or relinquishing the right to use the local bus in the own arithmetic unit in response to an instruction from the DMA controller of the other arithmetic unit And a function for reading and writing a memory in another arithmetic unit, and these functions can be operated independently.

(Operation)

The most important feature of the present invention is to obtain a bus use right from the CPU included in the function of the DMA controller in order to realize inter-memory data transfer across a plurality of arithmetic units that the conventional DMA controller could not support. The handshake function and the data transfer function between memories have been separated from each other, the function of sending and receiving instructions to and from other DMA controllers has been added, and these functions can be used alone or in combination. . With this, conventionally, if a certain CPU is held, then C
What had to perform a series of inter-memory data transfer within the PU's local bus can be extended to DMA transfer of the entire parallel information processing device by using an appropriate combination of separate and independent unit functions .

〔Example〕

Hereinafter, an embodiment of the present invention will be described with reference to the drawings.

FIG. 1 shows a configuration diagram of an embodiment of the present invention. In FIG. 1, a plurality of arithmetic units 1, 2,... 9 are interconnected by an interconnection path (bus) 104. The arithmetic unit 1 includes a CPU 11, a local memory (MEM) 12, a DMA controller (DMAC) 13, and a bus interface circuit (BIF) 1.
5, which are interconnected by a local bus 14. The same applies to the configurations of the other arithmetic units 2 to 9.
Although FIG. 1 shows a parallel information processing apparatus including nine arithmetic units, any number of arithmetic units may be generally used as long as the number is two or more.

FIG. 2 shows an embodiment of the internal configuration of the DMA controller which forms the center of the present invention. For convenience, FIG. 2 shows the DMA controller 13 in the arithmetic unit 1, but FIG.
The same applies to DMA controllers in other arithmetic units. Here, the DMA controller 13 includes an internal control register group 130, a CPU hold control circuit 131, a data transfer control circuit 132 between memories, and a control signal transmission / reception circuit 13 between other CPUs.
3.System bus right acquisition control circuit 134, DMA reception circuit 13
5. Consists of an instruction execution control circuit 136.

Hereinafter, the side on which the DMA controller 13 of the operation unit 1 issues a DMA transfer request (hereinafter, referred to as a requester), and the side on which the DMA controller 23 of the operation unit 2 receives the request (hereinafter, referred to as a requester).
The operation of FIG. 1 and FIG. 2 will be described together.

It is assumed that the DMA controller 13 of the arithmetic unit 1 receives a DMA request from the CPU 11 in a form of being written to the internal control register group 130 by software (the following description is based on I
The same applies to a case where a DMA request is received from a / O device or the like via the DMA receiving circuit 135). When receiving the DMA request, first, the CPU hold control circuit 131 issues a hold request signal to the CPU 11. In response, the CPU 11 relinquishes the right to use the local bus 14, and at the same time returns a hold permission signal. Next, the system bus right acquisition control circuit 134 transmits a system bus to the system bus arbitration circuit (so-called arbiter; ARB) omitted in FIG.
A bus use request signal 104 is issued, and a bus use permission signal is received from the system bus arbitration circuit. At this stage,
The DMA controller 13 of the arithmetic unit 1 has acquired the right to use the local bus 14 and the system bus 104.

Next, the DMA controller 13 of the arithmetic unit 1 sends a control signal to the arithmetic unit 2 from the control signal transmission / reception circuit 133 between other CPUs. It is assumed that there are one or more types of control signals, which are given by the CPU 11 setting in the internal control register group 130. Here, the control signal is transmitted to the DMA controller 23 of the arithmetic unit 2.
Is a control instruction meaning that the right to use the local bus 24 of the arithmetic unit 2 is obtained.

The control signal transmission / reception circuit 233 between the other CPUs in the DMA controller 23 of the target side of the arithmetic unit 2 receives the control signal, and subsequently, the instruction execution control circuit
23 interprets the control signal and DMA controller 23
Activate the related circuit inside. Now, the control signal is CP
Since this is a U21 hold request, the CPU hold control circuit 23
1 issues a hold request signal to the CPU 21. In response, the CPU 21 relinquishes the right to use the local bus 23 and returns a hold permission signal at the same time. The inter-CPU control signal transmission / reception circuit 233 notifies the requester-side DMA controller 13 of the inter-CPU control signal transmission / reception circuit 133 that the execution of the control command by the control signal is completed.
In the process up to this point, the local bus 14, the system bus 104, and the local bus 24 are all connected to the DMA controller 13 of the arithmetic unit 1.
Can be used.

Next, the memory-to-memory data transfer control circuit 132 in the DMA controller 13 of the arithmetic unit 1 performs a requester-side memory address, a target-side memory address, an address increment method, and a transfer total byte in the preset internal control register group 130. Memory addresses for both transmission and reception are generated one after another according to data such as the number and the transfer direction, and data transfer is continuously performed from a specific address of the memory 12 to another specific address of the memory 22, for example.

After a series of data transfer is completed, the DMA controller 23 connects the local bus 24 from the requester-side DMA controller 13 to the other CPU-to-CPU control signal transmitting / receiving circuit 133 from the other-to-CPU control signal transmitting / receiving circuit 133 to the target-side DMA controller 23. Sends a control signal instructing to abandon. As a result, in the same procedure as when acquiring the right to use the bus,
Instruction execution control circuit 2 which is an internal circuit of DMA controller 23
36, the CPU hold control circuit 231 and the like operate, the DMA controller 23 abandons the local bus 24, and the CPU 21 enters a state in which the processing that was being executed before being held can be resumed.
Completion of abandonment is also indicated by DMA controller 23
The MA controller 13 is notified. DMA controller 13
Further causes the system bus acquisition control circuit 134 to relinquish the right to use the system bus 104, and subsequently relinquishes the right to use the local bus 14, and completes the operation.

The above operation sequence is summarized as shown in FIG.

The operation in the case where the DMA controller 13 becomes the target receiving the DMA transfer request, that is, the target, may be considered by replacing the relationship between the DMA controllers 13 and 23 in the above description, and will not be particularly described. .

In the above description of the operation, the DM of the arithmetic unit 1
A The control signal sent from the controller 13 is
Although the description has been given such that only the DMA controller 23 of the arithmetic unit 2 receives the signal, this implies that the DMA controller 13 simultaneously transmits a signal for selecting the arithmetic unit 2. is there. If the signal selects all the processing units, the CPU control signal transmitting / receiving circuit operates in addition to all the processing units except the processing unit 1, and the right to use the local bus of all the processing units is assigned to each of the processing units. The DMA controller of each arithmetic unit acquires the right to use the local bus, and the same data can be simultaneously written from the memory 12 of the arithmetic unit 1 to the memories of all other arithmetic units (called broadcasting). Becomes For example, when an operation unit number is used as an operation unit selection signal, such data can be broadcast by setting one of the unused operation unit numbers as the all operation unit selection signal.

FIG. 4 shows a system configuration of another embodiment of the present invention. That is, this is a configuration example in which the arithmetic units 1 to 5 are connected to a network. The configuration of each of the arithmetic units 1 to 5 is basically the same as that of FIG. 2, except that the system bus interface circuit is replaced with a network interface circuit. Even in such a network connection between the operation units, it is possible to perform inter-memory transfer across the operation units in the same manner as the bus connection in FIG.

In the above description, the present invention has been described as relating to data transfer in the memory address space.
The present invention is similarly effective in the case where the I / O address space or the memory address space and the I / O address space which the controller often handles coexist. That is, when the I / O address space is considered, I / O devices are connected to the local bus 14 and
It may be assumed that the DMA request from the / O device is issued to the DMA receiving circuit 135.

〔The invention's effect〕

As described above, according to the present invention, a CPU, a memory, and a DMA controller are connected by an interconnecting path to a plurality of arithmetic units connected by a local bus, and the DMA controller of each arithmetic unit uses a bus from the CPU. The function of acquiring or revoking the right and the function of transferring data between memories are separated and independent, and the function of controlling another DMA controller is added, so that the data transfer between memories between arithmetic units can be executed at high speed. Further, by appropriately combining various unit functions such as bus request and transfer, data transfer between the inside and outside of the arithmetic unit can be flexibly realized. In addition, by adding control signal types between arithmetic units, more complex DMA
It is also possible to execute transfer control.

[Brief description of the drawings]

FIG. 1 is an overall configuration diagram of one embodiment of the present invention, and FIG.
FIG. 3 is a diagram showing a detailed configuration example of a DMA controller in FIG. 3, FIG. 3 is a diagram showing an example of an operation sequence according to FIGS. 1 and 2, FIG. 4 is a schematic configuration diagram of another embodiment of the present invention, FIG. 5 is a diagram illustrating a configuration example of an information processing apparatus according to a conventional inter-memory transfer method, and FIG. 6 is a diagram illustrating a configuration example of an information processing apparatus including a conventional DMA controller. 1,2,9 arithmetic unit 11,21,91 CPU (central processing unit) 12,22,92 memory 13,23,93 DMA controller 14,24,94 Local bus, 15, 25, 95 …… System bus interface circuit, 104…
… System bus, 130… Internal control register group, 131… CPU hold control circuit, 132… Data transfer control circuit between memories, 133… Controller signal transmission / reception circuit between other CPUs, 134… System bus right acquisition control circuit , 135 ... DMA reception circuit, 136 ... Instruction execution control circuit.

Claims (2)

(57) [Claims] 1. A parallel information processing apparatus in which at least a processor, a memory, and a plurality of operation units connected by a local bus to a DMA controller for directly accessing the memory are connected by an interconnecting path. Has a function of acquiring or relinquishing the right to use the local bus in the self-processing unit in response to a DMA transfer request, a function of reading and writing a memory in the self-processing unit using the local bus, and A function of acquiring or abandoning the right to use, a function of sending an instruction to the DMA controller of another arithmetic unit via the above-mentioned interconnection path, and a function of transmitting a local instruction in the own arithmetic unit in response to an instruction from the DMA controller of the other arithmetic unit. A function of acquiring or relinquishing the right to use the bus, and a function of reading and writing a memory in another arithmetic unit; and These functions can operate independently and independently, and the DMA controller in one arithmetic unit separates the processor in its own arithmetic unit and the processor in the other arithmetic unit from the respective local buses, and the A parallel information processing apparatus characterized in that data can be read and written between a memory in its own processing unit and a memory in another processing unit via the CPU. 2. A DMA controller in each arithmetic unit,
The parallel information processing apparatus according to claim 1, further comprising a broadcast function of writing the same data from a memory in the arithmetic unit to a memory in a plurality of other arithmetic units.