JPS61166670A - Bus switching system for service processor - Google Patents

Abstract

PURPOSE:To attain the individual control and call-out of the internal state of an optional main body device through plural service processors SVP, by using a circuit which switches the bus of each SVP and a circuit which controls the priority of operations. CONSTITUTION:A busy flag is turned on to start an access to a main body device 1 in case no operation is executed by an access strobe signal sent from an SVP-A. An affirmative answer is sent back to the SVP-A after the end of the access. The SVP-A lost the access strobe signal and the busy flag is reset. Then an operation is kept waiting even if an SVP-B starts an access during an access of the SVP-A. Thus the priority is decided for operations between both SVP-A and B and therefore the access is possible regardless of the action mode of a system. In case the access strobe signals are transmitted at a time, a priority control circuit 32 performs the selection control so that the access is carried out in the prescribed priority.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a service processor using an interface control device (SCI) provided between a main unit and a plurality of service processors (SVP) in an information processing system. (SVP) This relates to a bus switching method.

With the recent increase in size and sophistication of information processing systems, the number of main body devices constituting the system is increasing, and a plurality of sets are now being configured.

In addition, in response to the above-mentioned trend toward larger and more sophisticated systems, a dedicated service processor (hereinafter referred to as SvP) is provided to perform operation/maintenance operations of the system.

The above-mentioned SvP takes a form in which an interface control device (hereinafter referred to as SCI) is interposed between the main unit and the main unit to control the plurality of sets of main units.
A configuration control register (CFR) is provided in the SCI, and bus selection within the SCI is performed according to the contents of the register.
A connection is established between the svp and the main device.

In this case, in order to reduce the number of connection lines between the SCI and the main unit, for each set of main units, one SCI should be connected to multiple SVPs either directly or through SCIs of other systems. Take.

In such an information processing system, for example, when operating in a multiprocessor configuration, the SvP on the slave side is in standby mode and cannot directly access the main unit, and in a partition configuration, each main unit is connected to another system. Currently, it is not possible to access the device.

Therefore, in a multiprocessor configuration, Sv on the slave side
This means that the svp is not being used effectively, and even with a partition configuration, there is a problem that it is not possible to access the main unit of another system.
SvP allows for efficient connection control between
A bus switching system has been awaited.

[Conventional technology]

FIG. 4 is a block diagram showing a conventional svp bus switching system. For example, two sets of main body W1,
In an information processing system consisting of two SVPs (M-3VP, S-5VP) 2 and an inter-sono SCI 3,
In the partition configuration, under each SVP 2, the svp Each SvP bus is selected by controlling the selection circuit (SEL) 31, and similarly in a multiprocessor configuration, the mask SVP (M-S
VP) Under 2, mask SCI 3. or SC of each group
The SvP bus was selected according to the configuration control information in the configuration control register (CFR) so that each main unit 1 was connected to the main unit 1 (indicated by a solid line).

[Problem that the invention seeks to solve]

Therefore, in the conventional system, for example, in a multi-processor configuration, the mask SVP (M-5VP) 2 has the following configuration control. control
1... Since the information is fixed unless changed, the slave SVP 2 (S-
The slave SVP (S-5VP) 2 functions exclusively as a standby, and each SCI
There was a problem in that the main unit 1 connected to the main unit 3 could not be accessed. Also, in the partition configuration,
Each 5vP2 and the SCI 3 connected below it,
Since the main unit 1 is completely logically separated from the main unit 1 at the point indicated by the dashed line, there is a problem in that each 5VP 2 cannot access the main unit of another system.

In view of the above conventional drawbacks, the present invention provides control of the SvP bus selection circuit (SEL) 31 provided in the SCI 3.
The priority order is controlled each time by the operation from each SVP without being fixed by configuration control information, and the main unit of any system can be accessed from multiple SVPs 2 to control the main unit. The purpose of the present invention is to provide a method for reading out internal states.

[Means for solving problems]

This purpose is to provide a plurality of sets of information processing main units, a plurality of service processors (SVPs) corresponding to the main units,
Consisting of multiple interface control devices ('5CI), one interface control device (SCI) for each set of main units can control multiple interface control devices (SCI) directly or through other system interface control devices (SCI). In an information processing system connected to a service processor (SVP), the interface control device (SCI) includes:
A priority control circuit that switches the bus from each service processor (SVP) while controlling the priority for each operation is provided, and the main unit of an information processing system with a multiprocessor configuration or partition configuration is This is achieved by the SvP bus switching method of the present invention, which can be controlled from a service processor (SVP).

[Effect]

That is, according to the present invention, each SC1 is provided with a selection circuit (SELI) that switches the bus from each SvP, and a priority control circuit that controls the priority of the operation when there is an operation from each SvP. , regardless of multiprocessor configuration, partition configuration, etc., each main unit can be controlled from multiple svp, so any main unit can be controlled and its internal state can be read from multiple svp individually. This allows for diversification of SvP processing, as well as efficient use of standby SVPs, especially in multiprocessor configurations.
This has the effect of decentralizing the processing to be executed by the information processing system.

〔Example〕

Embodiments of the present invention will be described in detail below with reference to the drawings.

FIG. 1 is a block diagram showing one embodiment of the present invention, FIG. 2 is a diagram explaining details of the operation of the priority control circuit explained in FIG. 1, and FIG. FIG. 3 is a time chart showing the operation of the ranking control circuit. In Figures 1 and 2, the same symbols as in Figure 4 indicate the same objects,
The priority control circuit 32 is a necessary functional block to implement the present invention.

As is clear from FIG.
SvP bus selection circuit (SEL) 31 switches the bus from each SVP (M-SVP, S-5VP) 2 and controls the priority of operations from each 5VP (1'l-5VP, S-5VP) 2. Priority control circuit 32
The main unit can be controlled from a plurality of SVPs 2 by switching the SvP bus selection circuit (SEL) 31 with the output of the priority control circuit 32 for each operation, regardless of the multiprocessor configuration or partition configuration. It is distinctive in that it is made like this.

Next, the operation of dynamically switching the svp bus for each of the above-mentioned operations will be explained with reference to FIG. 3 for the second time.

Generally, in an information processing system consisting of two systems, a partition configuration or a multiprocessor configuration can be constructed, but in FIG.

The two SVPs 2 are noted and shown.

2 (7) Lotuses from SVP 2 are located in SCI 3 (7
)SVP Lotus selection circuit (SEL) connected to 31,
The bus selected by this SvP bus selection circuit (SEL) 31 is further connected to the bus distributed from the SCI 3 to each main unit 1, and is distributed to the host unit 1.

The two SVPs 2 further send out access strobe signals, and in response to the signals, the SCI 3 sends out the two SVPs 2.
An acknowledgment of the access is sent back to the SvP.

Then, in the priority control circuit 32 in SCI a, the access strobe signal from the SVP 2,
The access order is determined based on the response signal from the SCI 3, and the bus selection signal is sent to the svp bus selection circuit (SEL) 31.

FIG. 3 shows the operation at this time as a time chart, and the svp bus switching operation according to the present invention will be explained using the time chart.

Assuming that the above two SVPs 2 are 5VP-A, 5VP-
8.

First, the access strobe signal (■) sent from the 5VP-A 2 causes a busy flag (not shown in FIG. 2) if there is no operation in progress.
Turn on ■ and start accessing the main device 1.

Then, after or before the end of the access, an acknowledgment (^CK) ■ is sent back to 5VP-A 2, and 5VP
-A2 drops the access strobe signal (2), thereby completing the operation and resetting the busy flag (3).

If 5VP-A 2 (7) During 7 accesses, 5VP-
When the 5VP-82 sends out the access strobe signal (2) and starts accessing, since the busy flag (2) is already on, the operation from the 5VP-82 functions as if it were to wait.

The operation of 8.5VP-82 is 5VP-A 2.
When the operation B is completed and the busy flag ■ is reset, access B ■ is started.

In this way, the priority order of operations between the 5VP-A and 5VP-8 is determined, and the main unit can be accessed from the two 5VP-A and 5VP-8 regardless of the operating mode of the system.

When the access strobe signals are sent from multiple SVPs 2 at the same time, for example, a priority control circuit is set so that the main device 1 can be accessed sequentially according to a predetermined priority order. Selection control is performed at 32.

〔Effect of the invention〕

As explained above in detail, the SVP path switching method of the present invention includes a selection circuit (SEL) in each SCI that switches the bus from each SvP, and when there is an operation from each SvP, priority is given to the operation. A multiprocessor configuration with a priority control circuit that controls the order,
Each main unit can be controlled from multiple SVPs regardless of the partition configuration, etc., so any main unit can be controlled and its internal state can be read individually from multiple SVPs. , while diversifying SvP processing, especially in a multiprocessor configuration,
Efficient use of standby SVPs has the effect of distributing processing.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing an embodiment of the present invention. FIG. 2 is a diagram illustrating details of the operation of the priority control circuit explained in FIG. 1. FIG. 3 is a time chart showing the operation of the priority control circuit. FIG. 4 is a block diagram showing a conventional svp bus switching method. It is. In the drawings, 1 is the main unit. 2 is a service processor (M-5VP, S-5VP,
5VP-A, 5VP-8). 3 is an interface control device (SCI). 31 is an svp bus selection circuit (SEL). 32 is a priority control circuit. ■～■ are control signals or access operations. are shown respectively.弗 1 Figure circle 2 Figure vine 3 Figure 4 m

Claims (1)

[Claims] Consists of multiple sets of information processing main units, multiple service processors (SVP) corresponding to the main units, and multiple interface control units (SCI), with one interface for each set of main units. Control device (SCI)
directly or other system interface controller (SC)
I) through multiple service processors (SVPs)
In the information processing system connected to the above interface control device (SCI), there is a priority control circuit that switches the bus from each service processor (SVP) while controlling the priority for each operation. 1. A service processor bus switching method, wherein a main unit of an information processing system having a multiprocessor configuration or a partition configuration can be controlled from the plurality of service processors (SVPs).