JPS61118847A - Simultaneous access control system of memory - Google Patents

Abstract

PURPOSE:To avoid the throughput deterioration of a CPU even in case a large quantity of data are transferred to a memory from a peripheral device, by attaining the simultaneous accesses to different memory areas from plural devices. CONSTITUTION:The part of a memory 305 is divided into memory areas (banks 0-N) where the accesses are possible independently of each other from a CPU301 and the peripheral device 302 and addresses are continuous. A selection circuit 304 is provided to each memory bank to perform switching between the signal line led from the device 302 and that led from the CPU301. A memory access control circuit 303 monitors the accesses given to the same memory bank from the CPU301 and the device 302 and set one of them under a waiting state according to the priority when an access conflict is produced.

Description

[Detailed Description of the Invention] [Field of Industrial Application] The present invention relates to an access control method for a memory (storage device), and in particular, the present invention relates to a method for controlling access to a memory (storage device), and in particular, to a system for controlling access to a memory (storage device), in which a large amount of data is transferred to the memory from a peripheral device other than a CPU (central processing unit). It can be applied to medium-sized and small-scale communication control equipment, etc.

Concerning simultaneous memory access control methods.

[Conventional technology]

Conventionally, memory multiple access systems have been used in large-scale computers and the like. There is multi-bank control using address interleaving. Figure 6 shows 2. An example of a two-puncture configuration using the way interleap method is shown. In this scheme, addresses are assigned to two punctures 101, 102 of memory in sequence. That is.

Addresses 0, 2, 4, . . . are assigned to punk 1()1, and addresses 1*3 p 5 v . . . are assigned to punk 1O2. Furthermore, in the two-line system, an address buster 201 and a data register 202 are installed for each puncture, so that each puncture 101 and 102 can be accessed independently, and each register is switched by a switching circuit and connected to the CPU. This allows for simultaneous access to each puncture when referring to addresses continuously, such as in normal programs or data, so the data transfer time to and from the CPU is sufficient compared to the memory read/write time. If you're fast.

Memory throughput can be improved in proportion to the number of punctures. In the configuration shown in FIG. 6, the memory read/write time seen from the CPU is approximately A of the actual time.

[Problem that the invention seeks to solve]

However, in the two-prong system, multiple devices (CPU, . . .

Since the memory cannot be accessed simultaneously from multiple devices (channels, etc.) and is accessed sequentially from each device, throughput is significantly reduced when the memory is simultaneously accessed from multiple devices.

In addition, data transfer with one peripheral device such as a small to medium-sized communication control device is performed using a DMA transfer control circuit (il) CPU
In a method that is performed independently of memory access.

When accessing memory from the DMA transfer control circuit, the CPU
Since memory accesses from the

[Failure to solve the problem]

An object of the present invention is to divide a memory into a plurality of memory areas with consecutive addresses, and to selectively switch the address bus, data bus, and memory access signals from the CPU and peripheral control device for each memory area. Install the circuit,
If the memory areas accessed by multiple devices do not overlap, it is possible to enable each device to access the corresponding memory area independently and simultaneously, and to prevent memory access from multiple devices to the same memory area. A memory access control circuit that takes into consideration conflicts and determines the priority order of memory accesses when there is a memory access conflict is installed for the peripheral control device.
An object of the present invention is to provide a memory control method that allows a device with a high priority to access the memory.
In a device having at least one peripheral control device (such as a channel) other than a CPU, at least a part of the memory is divided into a plurality of memory areas with consecutive addresses.
A selection circuit is provided for each divided memory area to select an address/data/memory access signal line from the CPU and an address/data/memory access signal line from the peripheral control device and connect the selected address/data/memory access signal line to the memory. moreover,
For each peripheral control device, there is a register in which information indicating a memory area to be accessed by the peripheral control device is set, and information in the register includes information on a memory area to be accessed by the CPU when memory is accessed from the CPU. If they match, the priority of the memory access is determined, and the memory access with a lower priority is queued, and at the same time, the memory bus is connected to the device that generated the memory access with a higher priority. and a memory access control circuit that sends a selection signal to the selection circuit.

In this way, the CPU and the peripheral control device can access the memory completely independently and at the same time if the areas of memory to be accessed are different.

〔Example〕

Next, embodiments of the present invention will be described with reference to the drawings.

FIG. 1 is a conceptual diagram of a memory simultaneous access control system according to an embodiment of the present invention. In FIG. 1, memory 305
A part of the CPU 301 and peripheral control unit (IOC)
The memory area is divided into a plurality of memory areas with consecutive addresses (Punk 0 to Punk N) that can be accessed independently from the CPU 302 .For each memory bank, a signal line from the CPU 301 and a signal line from the peripheral control device 302 A selection circuit 304 is installed that switches the signal line and connects it to the memory puncture. In addition, in correspondence with the second peripheral control device 302, the CPU
A memory access control circuit 303 is installed to monitor conflicts in access to the same memory area (memory bank) between the peripheral control device 301 and the peripheral control device 302 and switch between the two selection circuits 304. A memory puncture selection circuit 304 accessed by the peripheral control device 302 normally connects the signal line of the peripheral control device 302 to the corresponding memory bank, and connects the signal line of the peripheral control device 302 to the corresponding memory bank.
Unless U 301 accesses this memory puncture, system 2
The peripheral control device 302 can access the corresponding memory puncture independently of the CPU 301.

Figure 2 shows the CPU 301 and peripheral control device 302 in Figure 1.
FIG. 3 shows a detailed configuration of a memory control unit including a memory access control circuit 303 and a memory access control circuit 303, and FIG.
The details of the memory unit including the memory 305 and the memory 305 are shown.

Figures 1 and 2 are shown below.

The operation of this embodiment will be explained with reference to FIG. Here, a case is shown in which the memory puncture 3050 is accessed from the CPU 301 and the peripheral control circuit 302.

First, the CPU 301 sets in the bank designation register 406 the position information (number) of a memory puncture to which the peripheral control circuit 302 accesses and transfers data.

Next, the CPU 301 sets data transfer control information (data transfer start address, number of data transfer bytes/words) in the peripheral control circuit 30'2, and instructs the peripheral control circuit 302 to start the transfer. According to the bank specification register 406, the memory section 03050 is accessed by the peripheral control circuit 302 as a memory puncture.
Consider the case where .

The contents of the bank specification register 406 are stored in the address decoder 4.
07, and the corresponding memory puncture (bank 0
) bus selection circuit 502. The bus switching circuit 504 is switched to the peripheral control circuit 402 side. That is, a portion including the bus selection circuit 502 and the bus switching circuit 504 constitutes the selection circuit 304 in FIG.

When the CPU 301 accesses the memory, the upper pit of the address signal and the contents of the bank designation register 406 are compared by the comparator 405, and if the bank accessed by the CPU 301 is not in the bar state (
MB MATCH=0), the memory access control circuit 303 does not generate a WAIT signal to the CPU 301.

The CPU 301 accesses the corresponding memory.

If the peripheral control circuit 302 accesses the data transfer memory bank 0 at the same time, the peripheral control circuit 302 first accesses the data transfer memory bank 0.
02 sends a bus occupancy request signal (HREQ) to the memory access control circuit 303. On the other hand, since there is no access conflict for the same memory bank (MB MATCH=O), the memory access control circuit 303 sends a bus occupancy request acceptance signal (HLDA) to the second peripheral control circuit 302.
to be sent back. As a result, the second peripheral control circuit 302 is
301 can access the corresponding memory puncture (bank O) at the same time as accessing other memory punctures.

FIG. 4 shows a time chart when there is no memory access conflict as described above.

Furthermore, when the CPU 301 accesses the memory, the bank (bank 0) 503 designated as the data transfer area of the peripheral control circuit 302 is stored in the bank designation register 406.
When CPU 301 accesses 0 (MB MAT
CH=1).

(1) When the CPU 301 accesses memory puncture 0 (MREQ=1) while the peripheral control circuit 302 is accessing memory puncture 0 (HREQ=1),
The memory access control circuit 303 sends a WAIT signal to the CPU 301 to wait for a memory access from the CPU 301. When the memory access from the peripheral control circuit 302 is completed (HREQ = 0) 1°, the memory access control circuit 303 sets HLDA = 0, and C
A PU selection signal is sent (CPU 5EL=1) and the bus selection circuit 502. At the same time as switching the bus switching circuit 504 to the CPU side, WAIT for the CPU is canceled to enable the CPU 301 to access the memory puncture O.

(2) If the peripheral control circuit 302 does not access memory puncture 0 (HREQ=0), the memory access control circuit 303 does not send out the WAIT signal.

Bus selection circuit 502. CPU SEL=1. Switch the bus switching circuit 504 to the CPU 301 side and
U 301 accesses memory puncture O.

CPU 301 is accessing memory puncture O.

When an access to memory puncture O occurs from the peripheral control circuit 302 (HREQ=1), the memory access control circuit 303 controls the peripheral control circuit 3 until the memory access from the CPU 301 ends (MREQ=O).
By not returning HLDA to 02.

Memory access from the peripheral control circuit 302 is made to wait. Next, when the memory access from the CPU 301 is completed, the memory access control circuit 303
Bus selection circuit 502 with L=0. The bus switching circuit 504 is switched to the peripheral control circuit 302 side, and the HLDA
= 1 to enable memory access from the peripheral control circuit 302. Completion of data transfer by peripheral control circuit 302 is notified to CPU 301 by an interrupt signal (INT).

FIG. 5 shows a time chart when memory access conflict occurs in the same memory bank (bank 0).

With this configuration, the 9 CPUs 301 can change the memory bank to which data is transferred independently from the 9 CPUs 301 by changing the contents of the bank designation register 406 using software, and by using the peripheral control circuit 302. can.

The present invention is particularly useful in systems that require data transfer from peripheral devices, etc., independent of CPU processing, such as small to medium-sized communication control devices.
When the amount of data transferred between memories is large and the area where the program is stored and the area used for data transfer are separated in the memory space, the through knot of the CPU can be greatly improved.

〔Effect of the invention〕

As described above, the present invention enables simultaneous access to different memory areas from multiple devices, thereby reducing CPU throughput even when transferring large amounts of data from peripheral devices to memory. Data can be transferred without any interruption.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing an outline of a simultaneous memory access system according to an embodiment of the present invention, and FIG. 2 is a schematic diagram showing the configuration of the memory control section of FIG. 1. Figure 3 is a program showing the configuration of the memory section in Figure 1. FIG. 4 is a time chart in the case where there is no memory access conflict in the above embodiment, FIG. 5 is a time chart in the case where there is memory access conflict in the above embodiment, and FIG. 6 is a conventional two-way process. This is a diagram for explaining an example of a bank configuration using an interleaving method.0 301...CPU, 302...Peripheral control device,
303...Memory access control device, 304...Selection circuit. 305...Memory, 403...Address decoder. 405...Comparator, 406...Puncture designation register. 407--address decoder, 501m and 501b
... Dirt switching circuit, 502... Bus selection circuit. 504...Bus switching circuit. Figure 1

Claims (1)

[Claims] 1. In a device having a CPU and at least one peripheral control device as an access source to memory, at least a part of the memory is divided into a plurality of memory areas with consecutive addresses, and for each memory area, the CPU
A selection circuit is provided for selecting an address bus, data bus, and memory access signal from the peripheral control device and an address bus, data bus, and memory access signal from the peripheral control device to connect the selected memory area to the corresponding memory area; If the register in which information indicating the memory area to be accessed by the device is set and the information indicating the memory area to be accessed by the CPU at the time of memory access from the CPU match the information in the register, the priority of memory access is determined. The selection circuit selects the bus connected to the corresponding memory area, and at the same time makes the memory access with a low priority wait for the memory access. 1. A simultaneous memory access control system, characterized in that a memory access control circuit for sending out a selection signal for connection to a memory is installed corresponding to the peripheral control device.