JP2005332372A - Image processing apparatus and image forming apparatus - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To prevent that the band of memory bus becomes insufficient, and to enable to distribute the load of data transfer. <P>SOLUTION: This apparatus is a digital copy machine 1 provided with an image input unit 2 which reads in image of a manuscript, and a printer engine 3 which forms image on a medium based on the read-in image data. The apparatus uses bus of PCI (Peripheral Component Interconnect) Express standard for data transfer. Same switches by PCI Express standard are connected to a storage domain and hardware resources performing transmitting and receiving of image data to the storage domain as the end points of same standard; that is, the input and output domain 21, the image input unit 2, and the printer engine 3 are connected to a switch 11, and a preservation domain 22, a compressor 5, and hard disk 6 are connected to a switch 12. <P>COPYRIGHT: (C)2006,JPO&NCIPI

Description

  The present invention relates to an image processing apparatus that performs predetermined processing relating to image data, and an image forming apparatus that reads an image of a document and forms an image on a medium such as paper.

  As a high-speed serial interface, an interface called PCI Express (registered trademark) corresponding to a successor standard of the PCI bus method has been proposed (for example, see Non-Patent Document 1).

"Outline of the PCI Express standard" Interface magazine, July '2003 Naoshi Satomi

  FIG. 22 is an explanatory diagram for explaining the flow of image data in a conventional digital copying machine equipped with a dedicated and general-purpose bus. The flow of image data is indicated by arrows.

  In the digital copying machine 201 of FIG. 22, the image data read by the image input device 202 is temporarily stored in the memory 203, and the image data is output to the printer engine 204 to form an image. Further, the digital copying machine 201 has a function of compressing and encoding image data stored in the memory 203 by the compressor 208 and storing it again in the memory 203 or storing it in the hard disk (HDD) 205. An input / output area 206 of the memory 203 is a storage area for temporarily storing image data read by the image input device 202, and a storage area 207 is a storage area for storing image data compressed and encoded by the compressor 208. Data input / output to / from the memory 203 is arbitrated by the arbiter 209 and performed by the memory bus 210.

However, such a conventional system has a problem that the bandwidth of the memory bus 210 may be insufficient because the image data always passes through the memory bus 210 when processing the image data as described above. For example,
The data transfer rate from the image input device 202 to the memory 203 is 15 MBytes / sec.
Data transfer rate from memory 203 to printer engine 204 is 20 MBytes / sec
Data transfer rate from memory 203 to compressor 208 is 25 MBytes / sec
Data transfer rate from the compressor 208 to the memory 203 is 25 MBytes / sec
Data transfer rate from memory 203 to HDD 205 is 50MBytes / sec
And FIG. 23 shows the sum of the start time and end time of each data transfer and the transfer rate of the memory bus 210 in this case. In FIG.
Start time of data transfer from image input device 202 to memory 0 seconds
End time 0.60 seconds Start time to transfer the image data in the memory to the printer engine 0.36 seconds
End time 0.81 seconds Start time to transfer the image data on the memory to the printer compressor 0.48 seconds
End time 0.66 seconds Start time of data transfer from printer compressor to memory 0.48 seconds
End time 0.66 seconds Start time to transfer data on compression-encoded memory to HDD 0.57 seconds
If the end time is 0.75 seconds, data transfer of 135 MB / sec occurs between 0.57 seconds and 0.60 seconds when the respective data transfers overlap.

  An object of the present invention is to prevent a memory bus from running out of bandwidth and to distribute a data transfer load.

  The present invention provides an image processing apparatus that performs predetermined processing relating to image data, and includes a bus and a switch for transferring data, a storage area for storing image data, and a hardware resource for transmitting and receiving image data. The image processing apparatus is characterized in that the storage area and the hardware resource are connected to the same switch.

  Another aspect of the present invention relates to an image forming apparatus that includes an image input device that reads an image of a document, and a printer engine that forms an image on a medium based on the read image data. A PCI Express standard bus is used for transfer, and the same switch according to the standard is connected to a storage area as an end point of the standard, and a hardware resource that transmits and receives image data to and from the storage area. An image forming apparatus characterized by the above.

  According to the present invention, by connecting the storage area and the hardware resource to the same switch, it is possible to avoid the fact that one memory bus is always used for the transfer of image data as in the prior art. It is possible to prevent the bus bandwidth from becoming insufficient and to distribute the data transfer load.

  The best mode for carrying out the present invention will be described with reference to the drawings.

  In the following, details of PCI Express will be described in the columns [Outline of PCI Express Standard] to [Details of Architecture of PCI Express], and then the digital copier of this embodiment will be described in the [Digital Copier] column. explain.

[Outline of PCI Express standard]
First, this embodiment uses PCI Express (registered trademark), which is one of high-speed serial buses. As an assumption of this embodiment, an outline of the PCI Express standard is a part of Non-Patent Document 1. Explain by excerpt. Here, the high-speed serial bus means an interface capable of exchanging data at high speed (about 100 Mbps or more) by serial (serial) transmission using a single transmission line.

  PCI Express is a standardized expansion bus that can be used for all computers as a successor to PCI. In general, low-voltage differential signal transmission, point-to-point independent communication channels, and packetization Split transactions and high scalability due to differences in link configuration.

  FIG. 1 shows a configuration example of an existing PCI system, and FIG. 2 shows a configuration example of a PCI Express system. In the existing PCI system, PCI-X (PCI upward compatible standard) devices 104a and 104b connect the PCI-X bridge 105a to the host bridge 103 to which the CPU 100, the AGP graphics 101, and the memory 102 are connected. Or a tree structure (tree structure) in which the PCI bridge 105b to which the PCI devices 104c and 104d are connected or the PCI bridge 107 to which the PCI bus slot 106 is connected is connected via the PCI-X bridge 105c. Has been.

  On the other hand, in the PCI Express system, the PCI Express graphics 113 is connected by the PCI Express 114a to the root complex 112 to which the CPU 110 and the memory 111 are connected, and the endpoint 115a and the legacy endpoint 116a. PCI Express 114b connects the switch 117a to which the PCI Express 114b is connected, and the PCI bridge 119 to which the switch 117b to which the endpoint 115b and the legacy endpoint 116b are connected by the PCI Express 114d and the PCI bus slot 118 are connected. The switch 117c connected by the Express 114e has a tree structure (tree structure) connected by the PCI Express 114f.

  An example of an actually assumed PCI Express platform is shown in FIG. The illustrated example shows an application example to desktop / mobile. For example, the graphics 125 is x16 with respect to the memory hub 124 (corresponding to the root complex) to which the CPU 121 is connected by the CPU host bus 122 and the memory 123 is connected. PCI Express 126a and an I / O hub 127 having a conversion function are connected by PCI Express 126b. For example, an HDD or a storage 129 is connected to the I / O hub 127 by a Serial ATA 128, a local I / O 131 is connected by an LPC 130, and a USB 2.0 132 and a PCI bus slot 133 are connected. Furthermore, a switch 134 is connected to the I / O hub 127 by a PCI Express 126c. The switch 134 is connected to the mobile dock 135, Gigabit Ethernet (Ethernet is a registered trademark) 136, and an add-in by PCI Express 126d, 126e, and 126f, respectively. A card 137 is connected.

  That is, in the PCI Express system, the conventional PCI, PCI-X, AGP bus is replaced with PCI Express, and a bridge is used to connect an existing PCI / PCI-X device. Connection between chipsets is also PCI Express connection, and existing buses such as IEEE1394, Serial ATA, and USB 2.0 are connected to PCI Express by an I / O hub.

[Components of PCI Express]
A. Port / Lane / Link
FIG. 4 shows the structure of the physical layer. A port is a set of transmitters / receivers that are physically in the same semiconductor and form a link, and logically means an interface that connects components one-to-one (point-to-point). The transfer rate is, for example, one-way 2.5 Gbps (in the future, 5 Gbps or 10 Gbps is assumed). The lane is, for example, a set of 0.8 V differential signal pairs, and includes a transmission-side signal pair (two) and a reception-side signal pair (two). A link is a collection of lanes connecting two ports and the two ports, and is a dual simplex communication bus between components. The “xN link” is composed of N lanes, and N = 1, 2, 4, 8, 16, 32 are defined in the current standard. The illustrated example is an x4 link example. For example, as shown in FIG. 5, by changing the lane width N connecting the devices A and B, a scalable bandwidth can be configured.

B. Root Complex
The root complex 112 is located at the highest level of the I / O structure, and connects the CPU and the memory subsystem to the I / O. In a block diagram or the like, as shown in FIG. 3, it is often described as “memory hub”. The root complex 112 (or 124) has one or more PCI Express ports (root ports) (indicated by squares in the root complex 112 in FIG. 2), and each port is an independent I / O hierarchical domain. Form. The I / O hierarchical domain is a simple endpoint (for example, the example of the endpoint 115a side in FIG. 2), or is formed from a large number of switches and endpoints (for example, the endpoint in FIG. 2). 115b and switches 117b and 115c side).

C. End point
The endpoint 115 is a device having a configuration space header of type 00h (specifically, a device other than a bridge), and is divided into a legacy endpoint and a PCI Express endpoint. The major difference between the two is that the PCI Express endpoint basically does not request I / O port resources in the BAR (base address register), and therefore does not request an I / O request. PCI Express endpoints also do not support lock requests.

D. Switch
The switch 117 (or 134) couples two or more ports and performs packet routing between the ports. From the configuration software, the switch is recognized as a collection of virtual PCI-PCI bridges 141 as shown in FIG. In the figure, double-headed arrows indicate PCI Express links 114 (or 126), and 142a to 142d indicate ports. Of these, the port 142a is an upstream port closer to the root complex, and the ports 142b to 142d are downstream ports farther from the root complex.

E. PCI Express 114e-PCI bridge 119
Provides connection from PCI Express to PCI / PCI-X. Thereby, an existing PCI / PCI-X device can be used on the PCI Express system.

[Hierarchical architecture]
As shown in FIG. 7A, the conventional PCI architecture has a structure in which protocols and signaling are closely related and there is no concept of hierarchy. However, in PCI Express, as shown in FIG. Like independent communication protocols and InfiniBand, it has an independent hierarchical structure, and specifications are defined for each layer. In other words, a transaction layer 153, a data link layer 154, and a physical layer 155 are provided between the uppermost software 151 and the lowermost mechanism (mechanical) unit 152. Thereby, the modularity of each layer is ensured, and it becomes possible to provide scalability and reuse the module. For example, when adopting a new signal coding method or transmission medium, it is possible to cope with only changing the physical layer without changing the data link layer or the transaction layer.

  The core of the PCI Express architecture is a transaction layer 153, a data link layer 154, and a physical layer 155, each having the following roles described with reference to FIG.

A. Transaction layer 153
The transaction layer 153 is located at the highest level and has a function of assembling and disassembling a transaction layer packet (TLP). The transaction layer packet (TLP) is used for transmission of transactions such as read / write and various events. The transaction layer 153 performs flow control using credits for transaction layer packets (TLP). An outline of a transaction layer packet (TLP) in each of the layers 153 to 155 is shown in FIG. 9 (details will be described later).

B. Data link layer 154
The main role of the data link layer 154 is to guarantee data integrity of the transaction layer packet (TLP) by error detection / correction (retransmission) and link management. Packets for link management and flow control are exchanged between the data link layers 154. This packet is called a data link layer packet (DLLP) to distinguish it from a transaction layer packet (TLP).

C. Physical layer 155
The physical layer 155 includes circuits necessary for interface operations such as a driver, an input buffer, a parallel-serial / serial-parallel converter, a PLL, and an impedance matching circuit. It also has interface initialization / maintenance functions as logical functions. The physical layer 155 also serves to make the data link layer 154 / transaction layer 153 independent of the signaling technology used in the actual link.

  The PCI Express hardware configuration uses a technology called embedded clock, there is no clock signal, the clock timing is embedded in the data signal, and the receiving side is based on the crosspoint of the data signal. The clock is extracted.

[Configuration space]
PCI Express has a configuration space like conventional PCI, but its size is expanded to 4096 bytes as shown in FIG. 10, whereas conventional PCI has 256 bytes. As a result, sufficient space is secured in the future even for devices (such as host bridges) that require a large number of device-specific register sets. In PCI Express, the configuration space is accessed by accessing a flat memory space (configuration read / write), and the bus / device / function / register number is mapped to a memory address.

  The first 256 bytes of the space can be accessed as a PCI configuration space by a method using an I / O port from a BIOS or a conventional OS. The function of converting conventional access to PCI Express access is implemented on the host bridge. From 00h to 3Fh, it is a PCI2.3 compatible configuration header. As a result, a conventional OS and software can be used as they are except for functions extended by PCI Express. That is, the software layer in PCI Express inherits a load / store architecture (a method in which a processor directly accesses an I / O register) that is compatible with the existing PCI. However, in order to use functions expanded by PCI Express (for example, functions such as synchronous transfer and RAS (Reliability, Availability and Serviceability)), it is necessary to make it possible to access a 4 Kbyte PCI Express expansion space.

  Various form factors (shapes) are conceivable as PCI Express. Examples of specific examples include add-in cards, plug-in cards (NEWCARD), and Mini PCI Express.

[PCI Express architecture details]
The transaction layer 153, data link layer 154, and physical layer 155, which are the core of the PCI Express architecture, will be described in detail.

A. Transaction layer 153
The main role of the transaction layer 153 is to assemble and disassemble transaction layer packets (TLP) between the upper software layer 151 and the lower data link layer 154 as described above.

a. Address space and transaction type
In PCI Express, memory space (for data transfer with memory space), I / O space (for data transfer with I / O space), and configuration space (device configuration and setup) supported by conventional PCI In addition to message space (in-band event notification between PCI Express devices and general message transmission (exchange) ... Interrupt requests and confirmations are communicated by using the message as a "virtual wire" And four address spaces are defined. Transaction types are defined for each space (memory space, I / O space, configuration space is read / write, and message space is basic (including vendor definition)).

b. Transaction layer packet (TLP)
PCI Express performs communication in units of packets. In the transaction layer packet (TLP) format shown in FIG. 9, the header length of the header is 3DW (DW is an abbreviation of double word; total 12 bytes) or 4DW (16 bytes), and the transaction layer packet (TLP) format ( Information such as header length and presence / absence of payload), transaction type, traffic class (TC), attribute, and payload length are included. The maximum payload length in the packet is 1024 DW (4096 bytes).

  ECRC is an end-to-end data integrity guarantee and is a 32-bit CRC of the transaction layer packet (TLP) portion. This is because when an error occurs in the transaction layer packet (TLP) inside the switch or the like, the LCRC (link CRC) cannot detect the error (because the LCRC is recalculated with the TLP in error).

  Some requests do not require a completion packet, and some requests.

c. Traffic class (TC) and virtual channel (VC)
Upper software can differentiate (prioritize) traffic by using a traffic class (TC). For example, video data can be transferred with priority over network data. There are eight traffic classes (TC) from TC0 to TC7.

  A virtual channel (VC) is an independent virtual communication bus (a mechanism that uses a plurality of independent data flow buffers sharing the same link), each having resources (buffers and queues) As shown in FIG. 11, independent flow control is performed. Thereby, even if the buffer of one virtual channel becomes full (full), the transfer of another virtual channel can be performed. In other words, it can be used effectively by physically dividing one link into a plurality of virtual channels. For example, as shown in FIG. 11, when a route link is divided into a plurality of devices via a switch, the priority of traffic of each device can be controlled. VC0 is indispensable, and other virtual channels (VC1 to VC7) are mounted in accordance with the cost performance trade-off. The solid line arrow in FIG. 11 indicates the default virtual channel (VC0), and the broken line arrow indicates the other virtual channels (VC1 to VC7).

  Within the transaction layer, a traffic class (TC) is mapped to a virtual channel (VC). One or more traffic classes (TC) can be mapped to one virtual channel (VC) (when the number of virtual channels (VC) is small). In a simple example, it can be considered that each traffic class (TC) is mapped to each virtual channel (VC) on a one-to-one basis, and all traffic classes (TC) are mapped to the virtual channel VC0. The mapping of TC0-VC0 is essential / fixed, and the other mappings are controlled from the upper software. The software can control the priority of the transaction by using the traffic class (TC).

d. Flow control Flow control (FC) is performed in order to avoid overflow of the reception buffer and establish the transmission order. Flow control is done point-to-point between links, not end-to-end. Therefore, it cannot be confirmed that the packet has reached the final partner (completer) by flow control.

  PCI Express flow control is performed on a credit basis (mechanism to check the buffer availability on the receiving side before starting data transfer and prevent overflow and underflow). That is, the receiving side notifies the transmitting side of the buffer capacity (credit value) at the time of link initialization, and the transmitting side compares the credit value with the length of the packet to be transmitted, and transmits the packet only when there is a certain remaining. There are six types of credits.

  Flow control information exchange is performed using data link layer packets (DLLP) in the data link layer. The flow control is applied only to the transaction layer packet (TLP) and not to the data link layer packet (DLLP) (DLLP can always be transmitted / received).

B. Data link layer 154
The main role of the data link layer 154 is to provide a reliable transaction layer packet (TLP) exchange function between two components on the link, as described above.

a. Handling of transaction layer packet (TLP) For the transaction layer packet (TLP) received from the transaction layer 153, a 2-byte sequence number at the beginning and a 4-byte link CRC (LCRC) at the end are added to the physical layer. To 155 (see FIG. 9). The transaction layer packet (TLP) is stored in the retry buffer and retransmitted until a reception confirmation (ACK) is received from the partner. When the transmission of the transaction layer packet (TLP) continues to fail, it is determined that the link is abnormal, and the physical layer 155 is requested to retrain the link. If link training fails, the state of the data link layer 154 transitions to inactive.

  The transaction layer packet (TLP) received from the physical layer 155 is inspected for the sequence number and the link CRC (LCRC). If normal, the transaction layer packet (TLP) is passed to the transaction layer 153. If there is an error, a retransmission is requested.

b. Data link layer packet (DLLP)
A packet generated by the data link layer 154 is called a data link layer packet (DLLP), and is exchanged between the data link layers 154. Data link layer packet (DLLP)
-Ack / Nak: TLP reception confirmation, retry (retransmission)
-InitFC1 / InitFC2 / UpdateFC: Flow control initialization and update-DLLLP for power management
There are different types.

  As shown in FIG. 12, the length of the data link layer packet (DLLP) is 6 bytes. From the DLLP type (1 byte) indicating the type, the information specific to the type of DLLP (3 bytes), and CRC (2 bytes) Composed.

C. Physical layer-logical sub-block 156
The main role of the physical layer 155 in the logical sub-block 156 shown in FIG. 8 is to convert the packet received from the data link layer 154 into a format that can be transmitted by the electrical sub-block 157. It also has a function of controlling / managing the physical layer 155.

a. Data encoding and parallel-serial conversion
PCI Express uses 8B / 10B conversion for data encoding so that continuous "0" and "1" do not continue (in order not to continue a state where a crosspoint does not exist for a long period of time). The converted data is serial-converted and transmitted from the LSB onto the lane as shown in FIG. Here, when there are a plurality of lanes (FIG. 13 illustrates the case of x4 link), data is allocated to each lane in units of bytes before encoding. In this case, it looks like a parallel bus at first glance, but since the transfer is performed independently for each lane, the skew which is a problem with the parallel bus is greatly reduced.

b. Power Management and Link State In order to keep the power consumption of the link low, a link state of L0 / L0s / L1 / L2 is defined as shown in FIG.

  L0 is a normal mode, and power consumption is reduced from L0s to L2, but it takes time to return to L0. As shown in FIG. 15, by actively performing active state power management in addition to software power management, it is possible to reduce power consumption as much as possible.

D. Physical layer—Electric sub-block 157
The main role of the physical layer 155 in the electrical sub-block 157 is to transmit the data serialized in the logical sub-block 156 onto the lane, and to receive the data on the lane and pass it to the logical sub-block 156. is there.

a. AC coupling On the transmission side of the link, a capacitor for AC coupling is mounted. This eliminates the need for the DC common mode voltage on the transmission side and the reception side to be the same. For this reason, it is possible to use different designs, semiconductor processes, and power supply voltages on the transmission side and the reception side.

b. De-emphasis
In PCI Express, as described above, processing is performed so that continuous “0” and “1” do not continue as much as possible by 8B / 10B encoding, but continuous “0” and “1” may continue (maximum). 5 times). In this case, it is specified that the transmission side must perform de-emphasis transfer. When bits of the same polarity are consecutive, it is necessary to increase the noise margin of the signal received on the receiving side by dropping the differential voltage level (amplitude) from the second bit by 3.5 ± 0.5 dB. . This is called de-emphasis. Due to the frequency-dependent attenuation of the transmission line, there are many high-frequency components in the case of changing bits, and the waveform on the receiving side becomes small due to attenuation. Becomes larger. For this reason, de-emphasis is performed in order to make the waveform on the receiving side constant.

[Digital copier]
FIG. 16 is a block diagram illustrating an overview of the digital copying machine 1 according to the first embodiment of this invention. The flow of image data is indicated by arrows.

  The digital copying machine 1 implements the image processing apparatus of the present invention and performs predetermined processing relating to image data. In this example, since the digital copying machine 1 also implements the image forming apparatus of the present invention, an image input device 2 that reads an image of a document and a medium such as paper based on the read image data of the document. The printer engine 3 is an output device that performs image formation. As predetermined processing relating to image data, the image input device 2 reads an image of a document and the printer engine 3 prints out the read image. In addition to the electrophotographic method, various methods such as an inkjet method, a sublimation type thermal transfer method, a silver salt photography method, a direct thermal recording method, and a melt type thermal transfer method can be used as the printing method of the printer engine 3.

  The digital copying machine 1 of the present embodiment uses a PCI Express standard bus for transferring image data and the like. The image input device 2, the printer engine 3, the memory 4, the compressor 5, and the hard disk (HDD) 6 are hardware resources serving as PCI Express standard end points. The switches 11 and 12 are PCI Express standard switches, and the arbiter 13 is a PCI Express standard root complex.

  The document image data read by the image input device 2 is temporarily stored in the memory 4 as a storage device, and the image data is output to the printer engine 3 to form an image. Further, the image data stored in the memory 4 can be compression-encoded by the compressor 5 and stored again in the memory 4 or stored in the HDD 6. The input / output area 21 of the memory 4 is a storage area for temporarily storing image data read by the image input device 2, and the storage area 22 is a storage area for storing image data compression-encoded by the compressor 5. That is, the storage areas 21 and 22 are a part of the memory 4 that is a single storage device divided into a plurality of uses. Data input / output to / from the memory 4 is arbitrated by the arbiter 13.

  Each of the switches 11 and 12 is connected with a storage area and hardware resources for transmitting and receiving image data to and from the storage area as end points.

  Specifically, the input / output area 21 and the image input apparatus 2 that transmits image data to the input / output area 21 are connected to the same switch 11. A printer engine 3 that outputs an image based on image data stored in the input / output area 21 is connected to the switch 11.

  A compressor 5 for compressing image data and a storage area 22 are connected to the switch 12.

  Thus, by connecting the storage area and the hardware resource for transmitting and receiving the image data to the same switch, one memory bus is always used for transferring the image data as in the prior art. Therefore, it is possible to prevent the memory bus bandwidth from becoming insufficient and to distribute the data transfer load.

  In addition, since a PCI Express standard bus is used, there is no need to worry about the bandwidth of the memory bus when connecting hardware resources and memory later. That is, in the example shown in FIG. 17, the input / output memory 31 and the storage memory 32 which are independent memory devices are used as storage areas corresponding to the input / output area 21 and the storage area 22, respectively. When retrofitting an image processing circuit 41 that performs predetermined image processing and an image processing memory 42 that is an independent memory device that stores the image data after the image processing, these are connected to the same switch 14. Even if hardware resources and memory are increased, the memory bus bandwidth does not become insufficient, and the data transfer load can be distributed.

  In the above description, the example in which the image processing apparatus of the present invention is applied to a digital copying machine has been described. However, the image processing apparatus of the present invention is not limited to this, and a printer, a scanner, a facsimile machine, etc. The present invention can be applied to various image processing apparatuses that perform predetermined processing relating to image data.

[Second Embodiment]
Next, a second embodiment of the present invention will be described with reference to FIGS. The same parts as those in the first embodiment described above are denoted by the same reference numerals, and description thereof is also omitted.

  FIG. 18 is a block diagram illustrating an outline of the digital copying machine 1 according to the second embodiment of this invention. The flow of image data is indicated by arrows.

  The digital copying machine 1 of the present embodiment uses a PCI Express standard bus for transferring image data and the like. The image input device 2, the printer engine 3, the memory 4, the compressor 5, and the hard disk (HDD) 6 are hardware resources serving as PCI Express standard end points. The switch 11 is a PCI Express standard switch, and the arbiter 13 is a PCI Express standard root complex.

  The document image data read by the image input device 2 is temporarily stored in the memory 4 as a storage device, and the image data is output to the printer engine 3 to form an image. The image data stored in the memory 4 can be compression-encoded by the compressor 5 and stored again in the memory 4 or stored in the HDD 6. The input / output area 21 of the memory 4 is a storage area for temporarily storing image data read by the image input device 2, and the storage area 22 is a storage area for storing image data compression-encoded by the compressor 5. That is, the storage areas 21 and 22 are a part of the memory 4 that is a single storage device divided into a plurality of uses. Data input / output to / from the memory 4 is arbitrated by the arbiter 13.

Here, data transfer between individual hardware resources
Input / output area 21 from image input device 2
Input / output area 21 to compressor 5
From the input / output area 21 to the printer engine 3
Storage area 22 from compressor 5
From storage area 22 to HDD 6
It is. For example,
The data transfer rate from the image input device 2 to the input / output area 21 is 15 MBytes / sec.
The data transfer rate from the input / output area 21 to the printer engine 3 is 20 MBytes / sec.
The data transfer rate from the input / output area 21 to the compressor 5 is 25 MBytes / sec.
Data transfer rate from the compressor 5 to the storage area 22 is 25 MBytes / sec
Data transfer rate from storage area 22 to HDD 6 is 50MBytes / sec
Then, the transfer rate is as shown in FIG. FIG. 19 is an explanatory diagram showing the sum of the time at which each data transfer occurs and the data transfer rate at the port of each area (input / output area, storage area) of the memory. According to this, since hardware resources are connected under the switch 11 of the PCI Express standard, the transfer rate in the input / output area is a bus transfer rate of 75 MB / sec in the port of the storage area, and the load is distributed. Can be made.

  A storage area and hardware resources for transmitting / receiving image data to / from the storage area are connected to the switch 11 as an end point.

  Specifically, the input / output area 21 and the image input apparatus 2 that transmits image data to the input / output area 21 are connected to the same switch 11. A printer engine 3 that outputs an image based on image data stored in the input / output area 21, a compressor 5 that compresses image data, and a storage area 22 are connected to the switch 11.

  Thus, by connecting the storage area and the hardware resource for transmitting and receiving the image data to the same switch, one memory bus is always used for image data transfer as in the prior art. Therefore, it is possible to prevent the bandwidth of the memory bus from being insufficient, and to distribute the load of the data transfer rate.

  Generally, the bus is competing between the data transfer from the input / output area 21 to the compressor 5 and the data transfer from the input / output area 21 to the printer engine 3, and the traffic is reduced. Here, FIG. 20 is a graph showing a characteristic in which four traffics start simultaneously at the output port of the switch 11 and data transfer ends in order according to the speed. As shown in FIG. 20, according to the present embodiment, as the number of competing traffic decreases, the slope of the graph becomes steeper and the data transfer rate is improved.

[Third Embodiment]
Next, a third embodiment of the present invention will be described with reference to FIG. The same parts as those in the first embodiment described above are denoted by the same reference numerals, and description thereof is also omitted.

  FIG. 21 is a block diagram illustrating an outline of the digital copying machine 1 according to the third embodiment of this invention. The flow of image data is indicated by arrows.

  In the digital copying machine 1 of the present embodiment, an input / output memory 31 and a storage memory which are independent memory devices as storage areas corresponding to the input / output area 21 and the storage area 22 described in the first embodiment. 32 is used. If these are connected to the same switch 11, even if hardware resources and memory are increased, the memory bus bandwidth will not be insufficient, and the load of the data transfer rate can be distributed.

It is a block diagram which shows the structural example of the existing PCI system. FIG. 2 is a block diagram illustrating a configuration example of a PCI Express system. It is a block diagram which shows the structural example of the PCI Express platform in desktop / mobile. It is a schematic diagram which shows the structural example of the physical layer in the case of x4. It is a schematic diagram which shows the example of lane connection between devices. It is a block diagram which shows the logical structural example of a switch. It is a block diagram which shows the architecture of the existing PCI. It is a block diagram which shows the architecture of PCI Express. It is a block diagram which shows the hierarchical structure of PCI Express. It is explanatory drawing which shows the format example of a transaction layer packet. It is explanatory drawing which shows the configuration space of PCI Express. It is a schematic diagram for demonstrating the concept of a virtual channel. It is explanatory drawing which shows the format example of a data link layer packet. It is a schematic diagram which shows the byte striping example in x4 link. It is explanatory drawing explaining the definition of the link state of L0 / L0s / L1 / L2. It is a time chart which shows the example of control of active state power management. 1 is a block diagram illustrating an overview of a digital copying machine according to a first embodiment of this invention. FIG. 3 is an explanatory diagram when an image processing circuit and a memory are added to a digital copying machine. It is a block diagram explaining the outline | summary of the digital copying machine of the 2nd Embodiment of this invention. It is explanatory drawing which shows the sum of the time which each data transfer occurs, and the data transfer rate in the port of each area | region (input / output area | region, storage area | region) of memory. It is the graph which showed the characteristic that four traffics start simultaneously in the output port of a switch, and data transfer is completed in order according to speed. It is a block diagram explaining the outline | summary of the digital copying machine of the 3rd Embodiment of this invention. It is explanatory drawing explaining the subject of this invention. It is explanatory drawing which shows the sum of the time which each data transfer generate | occur | produces, and the transfer rate of a memory bus.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 Image processing apparatus, image forming apparatus 2 Hardware resource, image input device 3 Hardware resource, output device, printer engine 4 Storage device 5 Hardware resource, Compressor 6 Hardware resource, Hard disk 11, 12, 14 Switch 21, 22, 31, 32, 42 Storage area 41 Hardware resource

Claims (11)

In an image processing apparatus that performs predetermined processing relating to image data,
A bus and a switch for transferring data;
A storage area for storing image data; and
Hardware resources for sending and receiving image data;
With
The storage area and the hardware resource are connected to the same switch;
An image processing apparatus.   The image processing apparatus according to claim 1, wherein the bus and the switch conform to a PCI Express standard.   The image processing apparatus according to claim 1, wherein the storage area is a part of a single storage device divided into a plurality of uses.   The image processing apparatus according to claim 1, wherein an image input apparatus that transmits image data to the storage area as the hardware resource is connected to the switch.   The output device that outputs an image based on the image data stored in the storage area as the hardware resource is connected to the switch. The image processing apparatus described. As the hardware resource, an image processor for processing image data is connected to the switch,
The storage area stores image data compressed by the compressor.
The image processing apparatus according to claim 1, wherein the image processing apparatus is an image processing apparatus. In an image forming apparatus comprising: an image input device that reads an image of a document; and a printer engine that forms an image on a medium based on the read image data.
PCI Express standard bus is used for data transfer,
The same switch according to the standard is connected to a storage area as an end point of the standard, and a hardware resource that transmits and receives image data to and from the storage area.
An image forming apparatus.   The image forming apparatus according to claim 7, wherein the storage area is a part of a single storage device divided into a plurality of uses.   The image forming apparatus according to claim 7, wherein the image input apparatus that transmits image data to the storage area as the hardware resource is connected to the switch.   The printer engine that performs the image formation based on image data stored in the storage area as the hardware resource is connected to the switch. The image forming apparatus described in 1. As the hardware resource, a compressor for compressing image data is connected to the switch,
The storage area stores image data compressed by the compressor.
The image forming apparatus according to claim 7, wherein the image forming apparatus is an image forming apparatus.

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