JP4928715B2 - Serial data transfer device, image output device, image input device, and image forming device - Google Patents

Description

  The present invention relates to an image output device, an image input device, a serial data transfer device for an image device such as an image forming device, and the like, and these image devices.

  Generally, a PCI bus is used as an interface between devices in an image apparatus such as a printer that handles image data and other data, a scanner, a digital copying machine including these, and an image forming apparatus such as an MFP. However, the parallel PCI bus has problems such as racing and skew, and the transfer rate has been low for use in high-speed and high-quality image equipment. The use of a high-speed serial interface as an alternative to the system interface is being studied.

  In particular, an interface called PCI Express (registered trademark) corresponding to a successor standard of the PCI bus system has been proposed and is now in a practical stage (see, for example, Non-Patent Document 1).

JP 2002-82793 A “Outline of PCI Express Standard” Interface, July’2003 Naoshi Satomi

  However, in the case of the PCI Express standard described in Non-Patent Document 1, etc., the physical layer (port / lane / link) configuration is premised on the same configuration (pair configuration) in both directions. If the data flow is only in one direction, the performance of the interface is too high, and the signal line (physical layer electrical sub-block) is wasted. There are disadvantages in this respect.

  Incidentally, Patent Document 1 discloses a technique in which an interface connecting a controller and a printer engine is divided into a control line and a data line, the control line is bidirectional, and the data line is exchanged in one direction. . However, only the number of signal lines according to the direction of data transfer is specified, and in the case of high-speed serial data communication, especially high-speed serial data communication according to the PCI Express standard, how is the physical layer configuration, etc. There is no mention of whether to apply it, and it is insufficient.

  An object of the present invention is to provide an interface function that is advantageous in terms of cost, power consumption, and the like when a high-speed serial data communication, in particular, a high-speed serial data communication conforming to the PCI Express standard is applied to an imaging device. That is.

The serial data transfer device for an image device according to the first aspect is a lane provided across the first port and the second port, and is a set of signal lines capable of bidirectionally communicating a control signal and data . PCI Express standard has a 1 lane and a second lane is a communicable signal lines in one direction as the data lines for transferring lane a is data that is provided over said first port and said second port When the data is transferred from the first port to the second port, the data is transferred via the first lane and the second lane, and the second port When data is transferred from the first port to the first port, the data is transferred through the first lane .

According to a second aspect of the present invention, in the serial data transfer device according to the first aspect, the physical layer controls the number of lanes in a digital transmission / reception unit of a logical sub-block of the physical layer.

  According to a third aspect of the present invention, in the serial data transfer device according to the second aspect, the transaction layer and data link layer above the physical layer conform to the PCI Express specification.

4. The image output apparatus according to claim 4, wherein at least the image output engine, a controller for controlling and driving the image output engine, and the controller and the image output engine are connected. An interface by the serial data transfer device according to claim 1, wherein the first lane can bidirectionally communicate the control signal between the controller and the image output engine, and The controller can transfer data from the controller to the image output engine, and the second lane can transfer image data from the controller to the image output engine.

According to a fifth aspect of the present invention, in the image output device according to the fourth aspect, the image output engine has a plurality of output mechanisms corresponding to the color components for color, and the first lane includes the color components for color. The image data of any one of the color components is transferred from the controller to the image output engine, and the second lane is the color component transferred by the first lane among the color components for the color. Image data of color components other than the image data is transferred from the controller to the image output engine.

6. The image input device according to claim 6, wherein at least the image input engine, a controller for controlling and driving the image input engine, and the controller and the image input engine are connected. An interface by the serial data transfer device according to claim 1, wherein the first lane can bidirectionally communicate the control signal between the controller and the image input engine, and the image data The image data can be transferred from the image input engine to the controller, and the second lane can transfer image data from the image input engine to the controller.

According to a seventh aspect of the present invention, in the image input device according to the sixth aspect, the image input engine has a plurality of input mechanisms corresponding to each color component for color, and the first lane has each color component for color. The image data of any one of the color components is transferred from the controller to the image output engine, and the second lane is the color component transferred by the first lane among the color components for the color. Image data of color components other than the image data is transferred from the controller to the image output engine.

  An image forming apparatus according to an eighth aspect of the present invention includes an image output engine and a controller for controlling and driving the image input engine, the image output apparatus according to the fourth or fifth aspect, and the image input apparatus according to the sixth or seventh aspect; .

  According to the present invention, the serial data transfer device serving as an interface in various image devices includes at least one bidirectional transfer path and includes physical layers having different numbers of signal lines depending on the data transfer direction. In addition, the physical layer configuration requires only the number of signal lines defined by the data transfer direction, and an interface function that is advantageous in terms of cost, power consumption, and the like, and that is less wasteful can be exhibited. In particular, when considering high-speed serial transfer according to the PCI Express standard, it can be easily realized by controlling the number of lanes in the digital transmission / reception unit of the logical sub-block of the physical layer. By making the transaction layer and the data link layer conform to the PCI Express specification, versatility as an interface can be enhanced.

  Such a serial data transfer device includes an image output device such as a printer in which the data transfer direction is one direction, an image input device such as a scanner, a digital copier having both of them, and an image forming device such as an MFP. By applying to image equipment such as the above, the merit can be maximized.

  The best mode for carrying out the present invention will be described with reference to the drawings.

[Outline of PCI Express standard]
First, this embodiment conforms to PCI Express (registered trademark), which is one of high-speed serial buses. As a premise of this embodiment, an outline of the PCI Express standard is a part of Non-Patent Document 1. Explained with excerpts. Here, the high-speed serial bus means an interface capable of exchanging data at high speed (about 100 Mbps or more) by serial (serial) transmission using a single transmission line.

  PCI Express is a standardized expansion bus that can be used for all computers as a successor to PCI. In general, low-voltage differential signal transmission, point-to-point independent communication channels, and packetization Split transactions and high scalability due to differences in link configuration.

  FIG. 1 shows a configuration example of an existing PCI system, and FIG. 2 shows a configuration example of a PCI Express system. In the existing PCI system, PCI-X (PCI upward compatible standard) devices 104a and 104b connect the PCI-X bridge 105a to the host bridge 103 to which the CPU 100, the AGP graphics 101, and the memory 102 are connected. A tree structure in which a PCI-X bridge 105b to which PCI-X devices 104c and 104d are connected and a PCI bridge 107 to which a PCI bus slot 106 is connected are connected via a PCI-X bridge 105c ( Tree structure).

  On the other hand, in the PCI Express system, the PCI Express graphics 113 is connected by the PCI Express 114a to the root complex 112 to which the CPU 110 and the memory 111 are connected, and the endpoint 115a and the legacy endpoint 116a. The switch 117a connected by the PCI Express 114b is connected by the PCI Express 114c, and the PCI bridge 119 to which the end point 115b and the legacy end point 116b are connected by the PCI Express 114d and the PCI bus slot 118 are connected to the PCI bridge 119. The switch 117c connected by the Express 114e has a tree structure (tree structure) connected by the PCI Express 114f.

  An example of an actually assumed PCI Express platform is shown in FIG. The illustrated example shows an application example to a desktop / mobile. For example, graphics 125 is connected to a memory hub 124 (corresponding to a root complex) to which a CPU 121 is connected by a CPU host bus 122 and a memory 123 is connected. An x16 PCI Express 126a and an I / O hub 127 having a conversion function are connected by a PCI Express 126b. For example, a memory 129 is connected to the I / O hub 127 by a Serial ATA 128, a local I / O 131 is connected by an LPC 130, and a USB 2.0 132 and a PCI bus slot 133 are connected. Furthermore, a switch 134 is connected to the I / O hub 127 by a PCI Express 126c. The switch 134 is connected to the mobile dock 135, Gigabit Ethernet (Ethernet is a registered trademark) 136, and an add-in by PCI Express 126d, 126e, and 126f, respectively. A card 137 is connected.

  That is, in the PCI Express system, the conventional PCI, PCI-X, AGP bus is replaced with PCI Express, and a bridge is used to connect an existing PCI / PCI-X device. Connection between chipsets is also PCI Express connection, and existing buses such as IEEE1394, Serial ATA, and USB 2.0 are connected to PCI Express by an I / O hub.

[Components of PCI Express]
A. Port / Lane / Link
FIG. 4 shows the structure of the physical layer. A port is a set of transmitters / receivers that are physically in the same semiconductor and form a link, and logically means an interface that connects components one-to-one (point-to-point). The transfer rate is, for example, one-way 2.5 Gbps (in the future, 5 Gbps or 10 Gbps is assumed). The lane is, for example, a set of 0.8 V differential signal pairs, and includes a transmission-side signal pair (two) and a reception-side signal pair (two). A link is a collection of lanes connecting two ports and the two ports, and is a dual simplex communication bus between components. The “xN link” is composed of N lanes, and N = 1, 2, 4, 8, 16, 32 are defined in the current standard. The illustrated example is an x4 link example. For example, as shown in FIG. 5, by changing the lane width N connecting the devices A and B, a scalable bandwidth can be configured.

B. Root Complex
The root complex 112 is located at the highest level of the I / O structure, and connects the CPU and the memory subsystem to the I / O. In a block diagram or the like, as shown in FIG. 3, it is often described as “memory hub”. The root complex 112 (or 124) has one or more PCI Express ports (root ports) (indicated by squares in the root complex 112 in FIG. 2), and each port is an independent I / O hierarchical domain. Form. The I / O hierarchical domain is a simple endpoint (for example, the example of the endpoint 115a side in FIG. 2), or is formed from a large number of switches and endpoints (for example, the endpoint in FIG. 2). 115b and switches 117b and 115c side).

C. End point
The endpoint 115 is a device having a configuration space header of type 00h (specifically, a device other than a bridge), and is divided into a legacy endpoint and a PCI Express endpoint. The major difference between the two is that the PCI Express endpoint basically does not request I / O port resources in the BAR (base address register), and therefore does not request an I / O request. PCI Express endpoints also do not support lock requests.

D. Switch
The switch 117 (or 134) couples two or more ports and performs packet routing between the ports. From the configuration software, the switch is recognized as a collection of virtual PCI-PCI bridges 141 as shown in FIG. In the figure, double-headed arrows indicate PCI Express links 114 (or 126), and 142a to 142d indicate ports. Of these, the port 142a is an upstream port closer to the root complex, and the ports 142b to 142d are downstream ports farther from the root complex.

E. PCI Express 114e-PCI bridge 119
Provides connection from PCI Express to PCI / PCI-X. Thereby, an existing PCI / PCI-X device can be used on the PCI Express system.

[Hierarchical architecture]
As shown in FIG. 7A, the conventional PCI architecture has a structure in which protocols and signaling are closely related and has no concept of hierarchy. In PCI Express, as shown in FIG. 7B, Like general communication protocols and InfiniBand, it has an independent hierarchical structure, and specifications are defined for each layer. In other words, the transaction layer 153, the data link layer 154, and the physical layer 155 are provided between the uppermost software layer 151 and the lowermost mechanism (mechanical) unit 152. Thereby, the modularity of each layer is ensured, and it becomes possible to provide scalability and reuse the module. For example, when adopting a new signal coding method or transmission medium, it is possible to cope with only changing the physical layer without changing the data link layer or the transaction layer.

  The core of the PCI Express architecture is a transaction layer 153, a data link layer 154, and a physical layer 155, each having the following roles described with reference to FIG.

A. Transaction layer 153
The transaction layer 153 is located at the highest level and has a function of assembling and disassembling a transaction layer packet (TLP). The transaction layer packet (TLP) is used for transmission of transactions such as read / write and various events. The transaction layer 153 performs flow control using credits for transaction layer packets (TLP). An outline of a transaction layer packet (TLP) in each of the layers 153 to 155 is shown in FIG. 9 (details will be described later).

B. Data link layer 154
The main role of the data link layer 154 is to guarantee data integrity of the transaction layer packet (TLP) by error detection / correction (retransmission) and link management. Packets for link management and flow control are exchanged between the data link layers 154. This packet is called a data link layer packet (DLLP) to distinguish it from a transaction layer packet (TLP).

C. Physical layer 155
The physical layer 155 includes circuits necessary for interface operations such as a driver, an input buffer, a parallel-serial / serial-parallel converter, a PLL, and an impedance matching circuit. It also has interface initialization / maintenance functions as logical functions. The physical layer 155 also serves to make the data link layer 154 / transaction layer 153 independent of the signaling technology used in the actual link.

  The PCI Express hardware configuration uses a technology called embedded clock, there is no clock signal, the clock timing is embedded in the data signal, and the receiving side is based on the crosspoint of the data signal. The clock is extracted.

[Configuration space]
PCI Express has a configuration space like conventional PCI, but its size is expanded to 4096 bytes as shown in FIG. 10, whereas conventional PCI has 256 bytes. As a result, sufficient space is secured in the future even for devices (such as host bridges) that require a large number of device-specific register sets. In PCI Express, the configuration space is accessed by accessing a flat memory space (configuration read / write), and the bus / device / function / register number is mapped to a memory address.

  The first 256 bytes of the space can be accessed as a PCI configuration space by a method using an I / O port from a BIOS or a conventional OS. The function of converting conventional access to PCI Express access is implemented on the host bridge. From 00h to 3Fh, it is a PCI2.3 compatible configuration header. As a result, a conventional OS and software can be used as they are except for functions extended by PCI Express. That is, the software layer in PCI Express inherits a load / store architecture (a method in which a processor directly accesses an I / O register) that is compatible with the existing PCI. However, in order to use functions expanded by PCI Express (for example, functions such as synchronous transfer and RAS (Reliability, Availability and Serviceability)), it is necessary to make it possible to access a 4 Kbyte PCI Express expansion space.

  Various form factors (shapes) are conceivable as PCI Express. Examples of specific examples include add-in cards, plug-in cards (NEWCARD), and Mini PCI Express.

[PCI Express architecture details]
The transaction layer 153, data link layer 154, and physical layer 155, which are the core of the PCI Express architecture, will be described in detail.

A. Transaction layer 153
The main role of the transaction layer 153 is to assemble and disassemble transaction layer packets (TLP) between the upper software layer 151 and the lower data link layer 154 as described above.

a. Address space and transaction type
In PCI Express, memory space (for data transfer with memory space), I / O space (for data transfer with I / O space), and configuration space (device configuration and setup) supported by conventional PCI In addition to message space (in-band event notification between PCI Express devices and general message transmission (exchange) ... Interrupt requests and confirmations are communicated by using the message as a "virtual wire" And four address spaces are defined. Transaction types are defined for each space (memory space, I / O space, configuration space is read / write, and message space is basic (including vendor definition)).

b. Transaction layer packet (TLP)
PCI Express performs communication in units of packets. In the transaction layer packet (TLP) format shown in FIG. 9, the header length of the header is 3DW (DW is an abbreviation of double word; total 12 bytes) or 4DW (16 bytes), and the transaction layer packet (TLP) format ( Information such as header length and presence / absence of payload), transaction type, traffic class (TC), attribute, and payload length are included. The maximum payload length in the packet is 1024 DW (4096 bytes).

  ECRC is an end-to-end data integrity guarantee and is a 32-bit CRC of the transaction layer packet (TLP) portion. This is because when an error occurs in the transaction layer packet (TLP) inside the switch or the like, the LCRC (link CRC) cannot detect the error (because the LCRC is recalculated with the TLP in error).

  Some requests do not require a completion packet, and some requests.

c. Traffic class (TC) and virtual channel (VC)
Upper software can differentiate (prioritize) traffic by using a traffic class (TC). For example, video data can be transferred with priority over network data. There are eight traffic classes (TC) from TC0 to TC7.

  A virtual channel (VC) is an independent virtual communication bus (a mechanism that uses a plurality of independent data flow buffers sharing the same link), each having resources (buffers and queues) As shown in FIG. 11, independent flow control is performed. Thereby, even if the buffer of one virtual channel becomes full (full), the transfer of another virtual channel can be performed. In other words, it can be used effectively by physically dividing one link into a plurality of virtual channels. For example, as shown in FIG. 11, when a route link is divided into a plurality of devices via a switch, the priority of traffic of each device can be controlled. VC0 is indispensable, and other virtual channels (VC1 to VC7) are mounted in accordance with the cost performance trade-off. The solid line arrow in FIG. 11 indicates the default virtual channel (VC0), and the broken line arrow indicates the other virtual channels (VC1 to VC7).

  Within the transaction layer, a traffic class (TC) is mapped to a virtual channel (VC). One or more traffic classes (TC) can be mapped to one virtual channel (VC) (when the number of virtual channels (VC) is small). In a simple example, it can be considered that each traffic class (TC) is mapped to each virtual channel (VC) on a one-to-one basis, and all traffic classes (TC) are mapped to the virtual channel VC0. The mapping of TC0-VC0 is essential / fixed, and the other mappings are controlled from the upper software. The software can control the priority of the transaction by using the traffic class (TC).

d. Flow control Flow control (FC) is performed to avoid the overflow of the reception buffer and establish the transmission order. Flow control is done point-to-point between links, not end-to-end. Therefore, it cannot be confirmed that the packet has reached the final partner (completer) by flow control.

  PCI Express flow control is performed on a credit basis (a mechanism that confirms the buffer availability on the receiving side before starting data transfer and prevents overflow and underflow). That is, the receiving side notifies the transmitting side of the buffer capacity (credit value) at the time of link initialization, and the transmitting side compares the credit value with the length of the packet to be transmitted, and transmits the packet only when there is a certain remaining. There are six types of credits.

  Flow control information exchange is performed using data link layer packets (DLLP) in the data link layer. The flow control is applied only to the transaction layer packet (TLP) and not to the data link layer packet (DLLP) (DLLP can always be transmitted / received).

B. Data link layer 154
The main role of the data link layer 154 is to provide a reliable transaction layer packet (TLP) exchange function between two components on the link, as described above.

a. Handling of transaction layer packet (TLP) For the transaction layer packet (TLP) received from the transaction layer 153, a 2-byte sequence number at the beginning and a 4-byte link CRC (LCRC) at the end are added to the physical layer. To 155 (see FIG. 9). The transaction layer packet (TLP) is stored in the retry buffer and retransmitted until a reception confirmation (ACK) is received from the partner. When the transmission of the transaction layer packet (TLP) continues to fail, it is determined that the link is abnormal, and the physical layer 155 is requested to retrain the link. If link training fails, the state of the data link layer 154 transitions to inactive.

  The transaction layer packet (TLP) received from the physical layer 155 is inspected for the sequence number and the link CRC (LCRC). If normal, the transaction layer packet (TLP) is passed to the transaction layer 153. If there is an error, a retransmission is requested.

b. Data link layer packet (DLLP)
A packet generated by the data link layer 154 is called a data link layer packet (DLLP), and is exchanged between the data link layers 154. Data link layer packet (DLLP)
-Ack / Nak: TLP reception confirmation, retry (retransmission)
-InitFC1 / InitFC2 / UpdateFC: Flow control initialization and update-DLLLP for power management
There are different types.

  As shown in FIG. 12, the length of the data link layer packet (DLLP) is 6 bytes. From the DLLP type (1 byte) indicating the type, the information specific to the type of DLLP (3 bytes), and CRC (2 bytes) Composed.

C. Physical layer-logical sub-block 156
The main role of the physical layer 155 in the logical sub-block 156 shown in FIG. 8 is to convert the packet received from the data link layer 154 into a format that can be transmitted by the electrical sub-block 157. It also has a function of controlling / managing the physical layer 155.

a. Data encoding and parallel-serial conversion
PCI Express uses 8B / 10B conversion for data encoding so that consecutive “0” s and “1” s do not continue (in order not to maintain a state where there is no cross point for a long period of time). The converted data is serial-converted and transmitted from the LSB onto the lane as shown in FIG. Here, when there are a plurality of lanes (FIG. 13 illustrates the case of x4 link), data is allocated to each lane in units of bytes before encoding. In this case, it looks like a parallel bus at first glance, but since the transfer is performed independently for each lane, the skew which is a problem with the parallel bus is greatly reduced.

b. Power management and link state As shown in Table 1, a link state of L0 / L0s / L1 / L2 is defined in order to keep the power consumption of the link low.

  L0 is a normal mode, and power consumption is reduced from L0s to L2, but it takes time to return to L0. As shown in FIG. 14, by actively performing active state power management in addition to software power management, it is possible to reduce power consumption as much as possible.

D. Physical layer—Electric sub-block 157
The main role of the physical layer 155 in the electrical sub-block 157 is to transmit the data serialized in the logical sub-block 156 onto the lane, and to receive the data on the lane and pass it to the logical sub-block 156. is there.

a. AC coupling On the transmission side of the link, a capacitor for AC coupling is mounted. This eliminates the need for the DC common mode voltage on the transmission side and the reception side to be the same. For this reason, it is possible to use different designs, semiconductor processes, and power supply voltages on the transmission side and the reception side.

b. De-emphasis
In PCI Express, as described above, processing is performed so that continuous “0” and “1” do not continue as much as possible by 8B / 10B encoding, but continuous “0” and “1” may continue (maximum). 5 times). In this case, it is specified that the transmission side must perform de-emphasis transfer. When bits of the same polarity are consecutive, it is necessary to increase the noise margin of the signal received on the receiving side by dropping the differential voltage level (amplitude) from the second bit by 3.5 ± 0.5 dB. . This is called de-emphasis. Due to the frequency-dependent attenuation of the transmission line, there are many high-frequency components in the case of changing bits, and the waveform on the receiving side becomes small due to attenuation. Becomes larger. For this reason, de-emphasis is performed in order to make the waveform on the receiving side constant.

[Serial data transfer device]
The serial data transfer apparatus according to the present embodiment is used in an image output apparatus such as a printer, an image input apparatus such as a scanner, and a high-speed image apparatus such as a digital copying machine and an image forming apparatus such as an MFP. It is used as a serial interface and conforms to the PCI Express standard as described above.

  The serial data transfer apparatus according to the present embodiment is assumed to be applied to an image device in which the data transfer direction is one direction, such as a printer or a scanner, and is particularly characterized in the configuration of its physical layer. This will be described in comparison with a physical layer configuration example of a serial data transfer device based on the PCI Express standard.

  FIG. 15B shows an example of the configuration of the physical layer 155 of the serial data transfer device according to the PCI Express standard. The lane configuration connecting the ports according to the PCI Express standard shown in FIG. Has been.

  On the other hand, FIG. 15A shows a configuration example of the physical layer 2 of the serial data transfer apparatus 1 of the present embodiment. For example, when the data transfer direction is one direction from the port 3 to the port 4, at least The physical layer configuration includes one bidirectional transfer path 5 and the number of signal lines differs depending on the data transfer direction. In the illustrated example shown in FIG. 15A corresponding to FIG. 15B, the lane configuration when viewed from the upper side to the lower side (port 3 to port 4) corresponds to the x4 lane configuration (the number of signal lines). On the other hand, the lane configuration when viewed from the bottom to the top (port 4 to port 3) is the x1 lane configuration (corresponding to the number of signal lines), so that only one way Due to the absence of lanes, the number of signal lines is different.

  As described above, since the physical layer 2 includes at least one bidirectional transfer path 5 and has a different number of signal lines depending on the data transfer direction, the minimum transfer function is ensured by the bidirectional transfer path 5, and the data The physical layer configuration requires only the number of signal lines defined by the transfer direction, and an interface function that is advantageous in terms of cost, power consumption, and the like, and that is less wasteful can be exhibited.

  Here, a method for controlling the number of lanes in such a physical layer will be described with reference to FIG. First, FIG. 16B shows an example of the configuration of the physical layer 155 in the case of x2 lanes in both the left and right directions of the serial data transfer device according to the PCI Express standard. In this case, the digital transmission / reception units 160 and 161 of the logical sub-block of the physical layer 155 transfer a differential signal pair indicated by D + and D− between the analog transmission units 162a to 162d and the analog reception units 163a to 163d. These digital transmission / reception units 160 and 161 control the lane usage method of transfer data, such as data rate negotiation, link lane order determination, link width negotiation, and the like.

  On the other hand, FIG. 16A shows the lane configuration when viewed from the left to the right (port 3 to port 4) of the serial data transfer apparatus 1 of the present embodiment according to FIG. 15A. The x2 lane configuration, conversely, the lane configuration when viewed from the right to the left (port 4 to port 3) shows an example of the physical layer 2 configuration in the case of the x1 lane configuration. In this case, the number of lanes is controlled by the digital transmission / reception units 6 and 7 of the logical sub-block of the physical layer 2, and the analog transmission units 8a to 8c, which are one less in comparison with FIG. The differential signal pairs indicated by D + and D− are transferred between the units 9a to 9c. According to the PCI Express standard, these digital transmission / reception units 6 and 7 can negotiate the data rate, and the lanes within the link. The present invention is realized by controlling the lane usage method of transfer data, such as order determination and link width negotiation. Note that the transaction layer and the data link layer above the physical layer 2 are not specifically shown, but conform to the PCI Express specification (conform to the transaction layer 153 and the data link layer 154).

  According to this, especially when high-speed serial transfer according to the PCI Express standard is considered, it is easily realized by controlling the number of lanes in the digital transmission / reception units 6 and 7 of the logical sub-block of the physical layer 2 In addition, if the transaction layer and data link layer above the physical layer 2 conform to the PCI Express specification, versatility as an interface can be enhanced. Compared with the case of normal PCI Express, signal lines (that is, electrical sub-blocks of the physical layer 2) can be reduced, which is advantageous in terms of cost and power consumption.

[Example of application to image output device]
The serial data transfer device as described above can be suitably applied to an image output device such as a laser printer as an example of an image device. That is, in a configuration including at least a printer engine (image output unit) that is an image output engine and a controller that controls and drives the printer engine, a data transfer direction is used as an interface that connects between the controller and the printer engine. The above-described serial data transfer device 1 may be used so that the controller side becomes the printer engine side. That is, the serial data transfer device 1 transmits a control line between the controller and the printer engine, which is capable of bi-directional communication, and a transfer line from the controller to the printer engine. And a data line for performing direction communication.

  As an example of application to such a printer, for example, a full-color printer that handles 2-bit image data of each color of CMYK is particularly suitable.

  FIG. 17 is a block diagram schematically showing an application example to a full-color printer as an image output apparatus. That is, the image output device 11 includes an image output unit (printer engine) 12 having a plurality of output mechanisms (for example, a well-known tandem engine structure) corresponding to color components such as CMYK, and the image output unit. And the controller 13 for controlling and driving the serial data 12 as an interface for connecting the controller 13 and the image output unit 12 so that the data transfer direction is from the controller 13 side to the image output unit 12 side. The transfer device 1 is used, and a control line (lane) by the bidirectional transfer path 5 capable of bidirectional communication for exchanging various control signals between the controller 13 and the image output unit 12, and the transfer direction from the controller 13. A plurality of CMYK data lines (lanes) for performing one-way communication of image data as the image output unit 12 It is obtaining configuration.

  As described above, by applying the serial data transfer device 1 to the image output device 11 such as a printer in which the data transfer direction is one direction, an interface function which is advantageous in terms of cost and power consumption and less wasteful is exhibited. Can be made.

[Example of application to image input device]
The serial data transfer device as described above can be suitably applied to an image input device such as an image scanner as an example of an image device. That is, in a configuration including at least a scanner engine (image input unit) that is an image input engine and a controller that controls and drives the scanner engine, the data transfer direction is an interface that connects between these controllers and the scanner engine. The above-described serial data transfer device 1 may be used so that the scanner engine side becomes the controller side. That is, the serial data transfer device 1 transmits a control line between the controller and the scanner engine and transmits a control signal by a bidirectional transfer path capable of bidirectional communication, and sets the transfer direction from the scanner engine to the controller as a piece of image data. And a data line for performing direction communication.

  As an example of application to such a printer, for example, a full-color scanner that handles 8-bit image data of RGB colors is particularly suitable.

  FIG. 18 is a block diagram schematically showing an application example to a full color scanner as an image output apparatus. That is, the image input device 21 includes an image input unit (scanner engine) 22 having a plurality of input mechanisms (for example, known RGB color CCDs) corresponding to color components such as RGB, and the image input unit 22. A controller 23 for controlling and driving the above-mentioned serial data as an interface for connecting the controller 23 and the image input unit 22 such that the data transfer direction is from the image input unit 22 side to the controller 23 side. The transfer device 1 is used, and a control line (lane) by the bidirectional transfer path 5 capable of bidirectional communication for exchanging various control signals between the controller 23 and the image input unit 22, and the transfer direction of the image input unit. And a plurality of RGB data lines (lanes) for performing one-way communication of image data from the controller 22 to the controller 23. It is formed.

  Thus, by applying the serial data transfer device 1 to the image input device 21 such as a scanner in which the data transfer direction is one direction, an interface function that is advantageous in terms of cost, power consumption, etc., and has little waste is exhibited. Can be made.

[Example of application to image forming apparatus]
The serial data transfer apparatus as described above can be suitably applied to an image forming apparatus such as a digital copying machine including an image input apparatus such as a scanner and an image output apparatus such as a laser printer as an example of an image device. That is, the configuration shown in FIG. 17 is combined with the configuration shown in FIG. 18. The image forming apparatus 31 includes an image output unit 12 as an image output engine and an image output engine as illustrated in FIG. A controller 32 for controlling and driving the image input unit 22 as an image input engine is included, and serial data transfer is performed between the image output unit 12 and the image input unit 22 and the controller 32 in the same manner as shown in FIGS. The device 1 is connected.

  As an image forming apparatus, for example, as shown in FIG. 20, in addition to the image output unit 12 and the image input unit 22, an image processing unit 34 for processing various image data, read image data and image processing are performed. The present invention can be similarly applied to an image forming apparatus 33 that is a multifunction peripheral (MFP) including a data storage unit 35 that stores image data and the like. Here, in the case of the image forming apparatus 33 which is a multifunction peripheral, the data transfer direction is one direction as the high-speed serial interfaces (serial data transfer apparatuses) 36 and 37 between the image processing unit 34, the data storage unit 35 and the controller 32. Therefore, the PCI Express standard shown in FIG. 15B or the like is used as it is.

  Thus, by applying the serial data transfer apparatus 1 to the image forming apparatuses 31 and 33 including the image output unit 12 and the image input unit 22 such as a printer in which the data transfer direction is one direction, cost and power consumption are achieved. This makes it possible to exhibit an interface function that is advantageous and less wasteful.

It is a block diagram which shows the structural example of the existing PCI system. FIG. 2 is a block diagram illustrating a configuration example of a PCI Express system. It is a block diagram which shows the structural example of the PCI Express platform in desktop / mobile. It is a schematic diagram which shows the structural example of the physical layer in the case of x4. It is a schematic diagram which shows the example of lane connection between devices. It is a block diagram which shows the logical structural example of a switch. (A) is a block diagram showing an existing PCI architecture, and (b) is a block diagram showing a PCI Express architecture. It is a block diagram which shows the hierarchical structure of PCI Express. It is explanatory drawing which shows the format example of a transaction layer packet. It is explanatory drawing which shows the configuration space of PCI Express. It is a schematic diagram for demonstrating the concept of a virtual channel. It is explanatory drawing which shows the format example of a data link layer packet. It is a schematic diagram which shows the byte striping example in x4 link. It is a time chart which shows the example of control of active state power management. It is explanatory drawing which shows the structural example of the physical layer of the serial data transfer apparatus of one embodiment of this invention in contrast with the structural example of the physical layer of the serial data transfer apparatus by PCI Express specification. It is a block diagram which shows the example of a physical layer structure of the serial data transfer apparatus of one embodiment of this invention compared with the example of a structure of the physical layer of the serial data transfer apparatus by PCI Express specification. It is a schematic block diagram which shows the example of application to an image output device. It is a schematic block diagram which shows the example of application to an image input device. It is a schematic block diagram which shows the example of application to an image forming apparatus. It is a schematic block diagram which shows the example of application to MFP.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 Serial data transfer apparatus 2 Physical layer 5 Bidirectional communication path 6, 7 Digital transmission / reception part 11 Image output apparatus 21 Image input apparatus 31, 33 Image formation apparatus

Claims (8)

A first lane is a set of the first port and the second is a lane that is provided over a port control signals and enabling bidirectional communication signal line data,
A physical layer that conforms to the PCI Express standard and includes a second lane that is a lane provided across the first port and the second port and that is a signal line that can communicate in one direction as a data line for transferring data. And when transferring data from the first port to the second port, the data is transferred via the first lane and the second lane, and the first port transmits the first lane. When transferring data to a port, the data is transferred through the first lane . The serial data transfer device according to claim 1, wherein the physical layer controls the number of lanes by a digital transmitting / receiving unit of a logical sub-block of the physical layer.   The serial data transfer device according to claim 2, wherein a transaction layer and a data link layer above the physical layer conform to the PCI Express specification. 4. At least an image output engine, a controller for controlling and driving the image output engine, and an interface by the serial data transfer device according to claim 1 for connecting between the controller and the image output engine. Prepared,
The first lane can bidirectionally communicate the control signal between the controller and the image output engine, and can transfer image data from the controller to the image output engine.
The second lane is an image output device capable of transferring image data from the controller to the image output engine. The image output engine has a plurality of output mechanisms corresponding to each color component for color,
The first lane transfers image data of any one of the color components for the color from the controller to the image output engine,
The second lane transfers image data of a color component other than the image data of the color component transferred by the first lane among the color components for the color from the controller to the image output engine. Item 5. The image output device according to Item 4. 4. At least an image input engine, a controller for controlling and driving the image input engine, and an interface by the serial data transfer device according to claim 1 for connecting between the controller and the image input engine. Prepared,
The first lane can bidirectionally communicate the control signal between the controller and the image input engine, and can transfer image data from the image input engine to the controller.
The second lane is an image input device capable of transferring image data from the image input engine to the controller. The image input engine has a plurality of input mechanisms corresponding to each color component for color,
The first lane transfers image data of any one of the color components for the color from the controller to the image output engine,
The second lane transfers image data of a color component other than the image data of the color component transferred by the first lane among the color components for the color from the controller to the image output engine. Item 7. The image input device according to Item 6. A controller for controlling and driving the image output engine and the image input engine;
An image output device according to claim 4 or 5,
An image input device according to claim 6 or 7,
An image forming apparatus comprising:

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