JP4777723B2 - Information processing system, program, and data transfer method - Google Patents

Description

  The present invention relates to an information processing system such as a multifunction peripheral (MFP) that handles various images and performs various processes, a program, and a data transfer method.

  In general, in an information processing system such as a digital copying machine or a multifunction peripheral (MFP) that handles image data and other data, a PCI bus is used as an interface between devices. However, the parallel PCI bus has problems such as racing and skew, and the transfer rate has been low for use in high-speed and high-quality image forming apparatuses. The use of a high-speed serial interface such as IEEE1394 or USB is being considered in place of the parallel interface. For example, according to Patent Document 1, it is proposed to use a high-speed serial interface such as IEEE1394 or USB as an internal interface.

  As another high-speed serial interface, an interface called PCI Express (registered trademark), which is a successor to the PCI bus system, has been proposed and has been put to practical use (for example, see Non-Patent Document 1). This PCI Express system is schematically configured as a data communication network having a tree structure (tree structure) such as a root complex-switch (arbitrary hierarchy) -device as shown in FIG. Has been.

JP 2001-016382 A “Outline of PCI Express Standard” Interface, July’2003 Naoshi Satomi

  However, in the case of Patent Document 1, there is no mention of a problem when simultaneously transferring a plurality of image data.

  In addition, since it becomes possible to construct a serial and highly flexible system, a plurality of traffics are generated. However, there is no mention of influences such as timing restrictions on line synchronous transfer.

  The present invention has been made in view of the above, and by effectively utilizing a PCI Express standard high-speed serial bus having features such as high scalability, even if there is a timing constraint for line synchronous transfer, An object is to enable reliable image data output and simultaneous transfer.

To solve the above problems and achieve the object, the invention according to claim 1, the serial bus, in the information processing system that performs a plurality of image data transfer at the same time, pre-carboxymethyl real bus by lines synchronous transfer For timing-constrained image data, a request-dedicated synchronization signal different from the image data transfer line synchronization signal is used, and when the image data transfer line synchronization signal falls, the issue of the read request command is terminated. I was like that .

The invention according to claim 2, shea by real bus, image data in the information processing system that performs a plurality of image data transfer at the same time, from the printer controller to the image output unit in synchronization prior to the line synchronizing signal by carboxymethyl real bus As for the transfer, the request-dedicated synchronization signal different from the line synchronization signal for image data transfer is used, and when the line synchronization signal for image data transfer falls, the issue of the read request command is completed. I did .

  According to a third aspect of the present invention, in the information processing system according to the second aspect, a memory write transaction is used in the image input unit for transferring image data to the printer controller, and a memory read transaction is used in the image output unit. As a result, the image input unit and the image output unit perform data transfer by a data transfer method in which an initiator of image data transfer is performed.

  According to a fourth aspect of the present invention, in the information processing system according to the second aspect, two transactions are assigned to different traffic classes TC.

  The invention according to claim 5 is the information processing system according to claim 4, wherein the priority of the traffic class TC of the memory read transaction of the image output unit is set to the memory write of the image input unit by setting a virtual channel. The priority was higher than the priority of the traffic class TC of the transaction.

  According to a sixth aspect of the present invention, in the information processing system according to the fifth aspect, the strict priority is set so that the memory write transaction is issued after all the memory read transactions are issued.

The invention according to claim 7, shea by real bus, image data in the information processing system that performs a plurality of image data transfer at the same time, from the printer controller to the image output unit in synchronization prior to the line synchronizing signal by carboxymethyl real bus As for the transfer, the request-dedicated synchronization signal different from the line synchronization signal for image data transfer is used, and when the line synchronization signal for image data transfer falls, the issue of the read request command is completed. I did .

  According to an eighth aspect of the present invention, in the information processing system according to the seventh aspect, the image processing unit for transferring image data to the printer controller uses a memory write transaction, and the image output unit uses a memory read transaction. As a result, the image processing unit and the image output unit perform data transfer by a data transfer method in which an initiator of image data transfer is performed.

  According to a ninth aspect of the present invention, in the information processing system according to the seventh aspect, two transactions are assigned to different traffic classes TC.

  According to a tenth aspect of the present invention, in the information processing system according to the ninth aspect, the priority of the traffic class TC of the memory read transaction of the image output unit is set to the memory write of the image processing unit by setting a virtual channel. The priority was higher than the priority of the traffic class TC of the transaction.

  In the invention according to claim 11, in the information processing system according to claim 10, the strict priority is set so that the memory write transaction is issued after all the memory read transactions are issued.

  According to a twelfth aspect of the present invention, in the information processing system according to any one of the first to eleventh aspects, the request-dedicated synchronization signal has the same cycle and the same phase as the line synchronization signal for image data transfer. It is a different signal.

  The invention according to claim 13 is the information processing system according to claim 12, further comprising phase difference measuring means for measuring a phase difference between the request-dedicated synchronization signal and the image data transfer line synchronization signal. The request-dedicated synchronization signal is generated from the line synchronization signal for image data transfer based on the phase difference amount measured by the phase difference measuring means.

  According to a fourteenth aspect of the present invention, in the information processing system according to the thirteenth aspect, the phase difference measurement means is generated by a measurement packet generation unit that generates a delay amount measurement packet and the measurement packet generation unit. A delay amount detection unit for detecting the delay amount based on the output time of the measured delay amount packet and the reception time of the return packet from the endpoint, and a delay amount storage for storing the delay amount detected by the delay amount detection unit And a section.

The invention according to claim 15, in claims 1 to 14 information processing system of any one described before alkoxy real bus is a high-speed serial bus PCI Express standard.

The invention according to claim 16 by real bus, a program for executing the simultaneous transmission of a plurality of image data to the computer, before the image data in accordance with carboxymethyl real buses timing constraints of line synchronizing transfer A request-dedicated synchronization signal that is different from the line synchronization signal for image data transfer is used, and when the line synchronization signal for image data transfer falls, the issue of the read request command is completed .

The invention according to claim 17 by real bus, a program for executing the simultaneous transmission of a plurality of image data to the computer, before carboxymethyl real bus image output unit from the printer controller in synchronization with the line synchronization signal by For the transfer of image data to the image data, a request-dedicated synchronization signal different from the line synchronization signal for image data transfer is used, and when the line synchronization signal for image data transfer falls, the issue of the read request command is terminated. I was like that .

The invention according to claim 18, the serial bus, the data transfer method of performing a plurality of image data transfer simultaneously, the image data with timing constraints before carboxymethyl real bus by line synchronous transmission, the image data transfer By using a request-dedicated synchronization signal that is different from the line synchronization signal for use, the read request command is issued when the line synchronization signal for image data transfer falls .

The invention according to claim 19, sheet by real bus, image data of a data transfer method for performing a plurality of image data transfer at the same time, from the printer controller to the image output unit in synchronization prior to the line synchronizing signal by carboxymethyl real bus As for the transfer, the request-dedicated synchronization signal different from the line synchronization signal for image data transfer is used, and when the line synchronization signal for image data transfer falls, the issue of the read request command is completed. I did .

  According to the first aspect of the invention, since the delay margin is increased for the reception of the request command within the line effective period of the line synchronization signal for image data transfer, variation in the influence of path delay (variation due to change in connection configuration) , Timing variations due to competing data transfer, etc.) and improved extensibility, so even if there are timing restrictions on line synchronous transfer, high-speed image data output and simultaneous transfer can be performed without wasting resources There is an effect that it can be performed.

  According to the second aspect of the present invention, the delay margin is increased for the reception of the read request command within the line valid period of the line synchronization signal for image data transfer. (Variation due to change, timing variation due to competing data transfer, etc.) and improved expandability, so even if there is a timing constraint for line synchronous transfer, high-speed image data output can be performed without wasting resources. There is an effect that simultaneous transfer can be performed.

  According to the invention of claim 3, even if there is a timing restriction of the line synchronization signal, it is possible to output the image data at high speed, and it is possible to perform a plurality of image data transfers simultaneously.

  According to the invention of claim 4, even if there is a timing restriction on the line synchronization signal, it is possible to output image data at a high speed, and it is possible to simultaneously transfer a plurality of image data.

  According to the invention of claim 5, even if there is a timing restriction on the line synchronization signal, it is possible to output image data at a high speed, and it is possible to simultaneously transfer a plurality of image data.

  According to the invention of claim 6, even if there is a timing constraint on the line synchronization signal, it is possible to output image data at a high speed, and it is possible to simultaneously transfer a plurality of image data.

  According to the seventh aspect of the present invention, since the delay margin increases for the reception of the read request command within the line effective period of the line synchronization signal for image data transfer, the variation in the influence of the path delay (the connection configuration (Variation due to change, timing variation due to competing data transfer, etc.) and improved expandability, so even if there is a timing constraint for line synchronous transfer, high-speed image data output can be performed without wasting resources. There is an effect that simultaneous transfer can be performed.

  According to the eighth aspect of the invention, it is possible to output image data at a high speed even when there is a timing constraint on the line synchronization signal, and it is possible to simultaneously transfer a plurality of image data.

  According to the ninth aspect of the invention, even if there is a timing restriction on the line synchronization signal, it is possible to output image data at a high speed, and it is possible to simultaneously transfer a plurality of image data.

  According to the tenth aspect of the present invention, even if there is a timing constraint on the line synchronization signal, it is possible to output image data at a high speed, and a plurality of image data transfers can be performed simultaneously.

  According to the invention of claim 11, even if there is a timing restriction on the line synchronization signal, the image data can be output at a high speed, and a plurality of image data can be transferred simultaneously.

  According to the twelfth aspect of the present invention, when the line synchronization signal for image data transfer falls, the issue of the read request command can be completed.

  According to the thirteenth aspect of the present invention, by controlling the phase difference between the request-dedicated synchronization signal and the image data transfer line synchronization signal according to the measured delay amount, the delay amount can be dynamically varied. Even if there is, there is an effect that the request-dedicated synchronization signal can always be generated based on the actual measurement value.

  According to the fourteenth aspect of the present invention, there is an effect that the phase difference between the request-dedicated synchronization signal and the image data transfer line synchronization signal can be reliably measured.

  According to the invention of claim 15, high-speed image data can be obtained even when there is a timing restriction of line synchronous transfer by effectively utilizing a PCI Express standard high-speed serial bus having features such as high scalability. There is an effect that output and simultaneous transfer can be performed.

  According to the sixteenth aspect of the present invention, the delay margin for receiving a request command within the line effective period of the line synchronization signal for image data transfer is increased, so that variation in the influence of path delay (change in connection configuration) , Fluctuations due to competing data transfer, and timing expansion due to competing data transfer, etc. There is an effect that transfer can be performed.

  According to the seventeenth aspect of the present invention, the delay margin increases for the reception of the read request command within the line valid period of the line synchronization signal for image data transfer. (Variation due to change, timing variation due to competing data transfer, etc.) and improved expandability, so even if there is a timing constraint for line synchronous transfer, high-speed image data output can be performed without wasting resources. There is an effect that simultaneous transfer can be performed.

  According to the eighteenth aspect of the present invention, since the delay margin increases for the reception of the request command within the line valid period of the line synchronization signal for image data transfer, the variation in the influence of the path delay (change in connection configuration) , Fluctuations due to competing data transfer, and timing expansion due to competing data transfer, etc. There is an effect that transfer can be performed.

  According to the nineteenth aspect of the present invention, since the delay margin increases for the reception of the read request command within the line valid period of the line synchronization signal for image data transfer, the variation in the influence of the path delay (connection configuration (Variation due to change, timing variation due to competing data transfer, etc.) and improved expandability, so even if there is a timing constraint for line synchronous transfer, high-speed image data output can be performed without wasting resources. There is an effect that simultaneous transfer can be performed.

  Exemplary embodiments of an information processing system, a program, and a data transfer method according to the present invention will be explained below in detail with reference to the accompanying drawings.

  The best mode for carrying out the present invention will be described with reference to the drawings. In the following, details of PCI Express will be described in the columns [Outline of PCI Express Standard] to [Details of Architecture of PCI Express], and then the information processing system according to the present embodiment will be described in the [Information Processing System] column. I will explain it.

[Outline of PCI Express standard]
First, this embodiment uses PCI Express (registered trademark), which is one of high-speed serial buses. As an assumption of this embodiment, an outline of the PCI Express standard is a part of Non-Patent Document 1. Explained with excerpts. Here, the high-speed serial bus means an interface capable of exchanging data at high speed (about 100 Mbps or more) by serial (serial) transmission using a single transmission line.

  PCI Express is a standardized expansion bus that can be used for all computers as a successor to PCI. In general, low-voltage differential signal transmission, point-to-point independent communication channels, and packetization Split transactions and high scalability due to differences in link configuration.

  FIG. 1 shows a configuration example of an existing PCI system, and FIG. 2 shows a configuration example of a PCI Express system. In the existing PCI system, PCI-X (PCI upward compatible standard) devices 104a and 104b connect the PCI-X bridge 105a to the host bridge 103 to which the CPU 100, the AGP graphics 101, and the memory 102 are connected. Or a PCI bridge 105b to which the PCI devices 104c and 104d are connected and a PCI bridge 107 to which the PCI bus slot 106 is connected are connected via the PCI bridge 105c (tree structure). Yes.

  On the other hand, in the PCI Express system, the PCI Express graphics 113 is connected by the PCI Express 114a to the root complex 112 to which the CPU 110 and the memory 111 are connected, and the endpoint 115a and the legacy endpoint 116a. The switch 117a connected by the PCI Express 114b is connected by the PCI Express 114c, and the PCI bridge 119 to which the end point 115b and the legacy end point 116b are connected by the PCI Express 114d and the PCI bus slot 118 are connected to the PCI bridge 119. The switch 117c connected by the Express 114e has a tree structure (tree structure) connected by the PCI Express 114f.

  An example of an actually assumed PCI Express platform is shown in FIG. The illustrated example shows an application example to desktop / mobile. For example, graphics 125 is x16 with respect to a memory hub 124 (corresponding to a root complex) to which a CPU 121 is connected by a CPU host bus 122 and a memory 123 is connected. PCI Express 126a and an I / O hub 127 having a conversion function are connected by PCI Express 126b. For example, a storage 129 is connected to the I / O hub 127 by a Serial ATA 128, a local I / O 131 is connected by an LPC 130, and a USB 2.0 132 and a PCI bus slot 133 are connected. Furthermore, a switch 134 is connected to the I / O hub 127 by a PCI Express 126c, and the mobile dock 135, Gigabit Ethernet 136 (Ethernet is a registered trademark), and an add-in are connected to the switch 134 by PCI Express 126d, 126e, and 126f, respectively. A card 137 is connected.

  That is, in the PCI Express system, the conventional PCI, PCI-X, AGP bus is replaced with PCI Express, and a bridge is used to connect an existing PCI / PCI-X device. Connection between chipsets is also PCI Express connection, and existing buses such as IEEE1394, Serial ATA, and USB 2.0 are connected to PCI Express by an I / O hub.

[Components of PCI Express]
A. Port / Lane / Link
FIG. 4 shows the structure of the physical layer. A port is a set of transmitters / receivers that are physically in the same semiconductor and form a link, and logically means an interface that connects component links in a one-to-one relationship (point-to-point). . The transfer rate is, for example, 2.5 Gbps in one direction. The lane is, for example, a set of 0.8 V differential signal pairs, and includes a transmission-side signal pair (two) and a reception-side signal pair (two). A link is a collection of lanes connecting two ports and the two ports, and is a dual simplex communication bus between components. The “xN link” is composed of N lanes, and N = 1, 2, 4, 8, 16, 32 are defined in the current standard. The illustrated example is an x4 link example. For example, as shown in FIG. 5, by changing the lane width N connecting the devices A and B, a scalable bandwidth can be configured.

B. Root Complex
The root complex 112 is located at the highest level of the I / O structure, and connects the CPU and the memory subsystem to the I / O. In a block diagram or the like, as shown in FIG. 3, it is often described as “memory hub”. The root complex 112 (or 124) has one or more PCI Express ports (root ports) (indicated by squares in the root complex 112 in FIG. 2), and each port is an independent I / O hierarchical domain. Form. The I / O hierarchical domain is a simple endpoint (for example, the example of the endpoint 115a side in FIG. 2), or is formed from a large number of switches and endpoints (for example, the endpoint in FIG. 2). 115b and switches 117b and 115c side).

C. End point
The endpoint 115 is a device having a configuration space header of type 00h (specifically, a device other than a bridge), and is divided into a legacy endpoint and a PCI Express endpoint. The major difference between the two is that the PCI Express endpoint does not request I / O resources in the BAR (Base Address Register), and therefore does not request an I / O request. PCI Express endpoints also do not support lock requests.

D. Switch
The switch 117 (or 134) couples two or more ports and performs packet routing between the ports. From the configuration software, the switch is recognized as a collection of virtual PCI-PCI bridges 141 as shown in FIG. In the figure, double-headed arrows indicate PCI Express links 114 (or 126), and 142a to 142d indicate ports. Of these, the port 142a is an upstream port closer to the root complex, and the ports 142b to 142d are downstream ports farther from the root complex.

E. PCI Express 114e-PCI bridge 119
Provides connection from PCI Express to PCI / PCI-X. Thereby, an existing PCI / PCI-X device can be used on the PCI Express system.

[Hierarchical architecture]
As shown in FIG. 7A, the conventional PCI architecture has a structure in which protocols and signaling are closely related and there is no concept of hierarchy. In PCI Express, as shown in FIG. Like the standard communication protocol and InfiniBand, it has an independent hierarchical structure, and specifications are defined for each layer. In other words, a transaction layer 153, a data link layer 154, and a physical layer 155 are provided between the uppermost software 151 and the lowermost mechanism (mechanical) unit 152. Thereby, the modularity of each layer is ensured, and it becomes possible to provide scalability and reuse the module. For example, when adopting a new signal coding method or transmission medium, it is possible to cope with only changing the physical layer without changing the data link layer or the transaction layer.

  The core of the PCI Express architecture is a transaction layer 153, a data link layer 154, and a physical layer 155, each having the following roles described with reference to FIG.

A. Transaction layer 153
The transaction layer 153 is located at the highest level and has a function of assembling and disassembling a transaction layer packet (TLP). The transaction layer packet (TLP) is used for transmission of transactions such as read / write and various events. The transaction layer 153 performs flow control using credits for transaction layer packets (TLP). An outline of a transaction layer packet (TLP) in each of the layers 153 to 155 is shown in FIG. 9 (details will be described later).

B. Data link layer 154
The main role of the data link layer 154 is to guarantee data integrity of the transaction layer packet (TLP) by error detection / correction (retransmission) and link management. Packets for link management and flow control are exchanged between the data link layers 154. This packet is called a data link layer packet (DLLP) to distinguish it from a transaction layer packet (TLP).

C. Physical layer 155
The physical layer 155 includes circuits necessary for interface operations such as a driver, an input buffer, a parallel-serial / serial-parallel converter, a PLL, and an impedance matching circuit. It also has interface initialization / maintenance functions as logical functions. The physical layer 155 also serves to make the data link layer 154 / transaction layer 153 independent of the signaling technology used in the actual link.

  The PCI Express hardware configuration employs a technology called embedded clock, there is no clock signal, the clock timing is embedded in the data signal, and the receiving side is based on the cross-point of the data signal. The system extracts the clock.

[Configuration space]
PCI Express has a configuration space like conventional PCI, but its size is expanded to 4096 bytes as shown in FIG. 10, whereas conventional PCI has 256 bytes. As a result, sufficient space is secured in the future even for devices (such as host bridges) that require a large number of device-specific register sets. In PCI Express, the configuration space is accessed by accessing a flat memory space (configuration read / write), and the bus / device / function / register number is mapped to a memory address.

  The first 256 bytes of the space can be accessed as a PCI configuration space by a method using an I / O port from a BIOS or a conventional OS. The function of converting conventional access to PCI Express access is implemented on the host bridge. From 00h to 3Fh, it is a PCI2.3 compatible configuration header. As a result, a conventional OS and software can be used as they are except for functions extended by PCI Express. That is, the software layer in PCI Express inherits a load / store architecture (a method in which a processor directly accesses an I / O register) that is compatible with the existing PCI. However, in order to use functions expanded by PCI Express (for example, functions such as synchronous transfer and RAS (Reliability, Availability and Serviceability)), it is necessary to make it possible to access a 4 Kbyte PCI Express expansion space.

  Various form factors (shapes) are conceivable as PCI Express. Examples of specific examples include add-in cards, plug-in cards (Express Cards), and Mini PCI Express.

[PCI Express architecture details]
The transaction layer 153, data link layer 154, and physical layer 155, which are the core of the PCI Express architecture, will be described in detail.

A. Transaction layer 153
The main role of the transaction layer 153 is to assemble and disassemble transaction layer packets (TLP) between the upper software layer 151 and the lower data link layer 154 as described above.

a. Address space and transaction type
In PCI Express, memory space (for data transfer with memory space), I / O space (for data transfer with I / O space), and configuration space (device configuration and setup) supported by conventional PCI In addition to message space (in-band event notification between PCI Express devices and general message transmission (exchange) ... Interrupt requests and confirmations are communicated by using the message as a "virtual wire" And four address spaces are defined. Transaction types are defined for each space (memory space, I / O space, configuration space is read / write, and message space is basic (including vendor definition)).

b. Transaction layer packet (TLP)
PCI Express performs communication in units of packets. In the transaction layer packet (TLP) format shown in FIG. 9, the header length of the header is 3DW (DW is an abbreviation of double word; total 12 bytes) or 4DW (16 bytes), and the transaction layer packet (TLP) format ( Information such as header length and presence / absence of payload), transaction type, traffic class (TC), attribute, and payload length are included. The maximum payload length in the packet is 1024 DW (4096 bytes).

  ECRC is an end-to-end data integrity guarantee and is a 32-bit CRC of the transaction layer packet (TLP) portion. This is because when an error occurs in the transaction layer packet (TLP) inside the switch or the like, the LCRC (link CRC) cannot detect the error (because the LCRC is recalculated with the TLP in error).

  Some requests do not require a completion packet, and some requests.

c. Traffic class (TC) and virtual channel (VC)
Upper software can differentiate (prioritize) traffic by using a traffic class (TC). For example, video data can be transferred with priority over network data. There are eight traffic classes (TC) from TC0 to TC7.

  A virtual channel (VC) is an independent virtual communication bus (a mechanism that uses a plurality of independent data flow buffers sharing the same link), each having resources (buffers and queues) As shown in FIG. 11, independent flow control is performed. Thereby, even if the buffer of one virtual channel becomes full (full), the transfer of another virtual channel can be performed. In other words, it can be used effectively by physically dividing one link into a plurality of virtual channels. For example, as shown in FIG. 11, when a route link is divided into a plurality of devices via a switch, the priority of traffic of each device can be controlled. VC0 is indispensable, and other virtual channels (VC1 to VC7) are mounted in accordance with the cost performance trade-off. The solid line arrow in FIG. 11 indicates the default virtual channel (VC0), and the broken line arrow indicates the other virtual channels (VC1 to VC7).

  Within the transaction layer, a traffic class (TC) is mapped to a virtual channel (VC). One or more traffic classes (TC) can be mapped to one virtual channel (VC) (when the number of virtual channels (VC) is small). In a simple example, it can be considered that each traffic class (TC) is mapped to each virtual channel (VC) on a one-to-one basis, and all traffic classes (TC) are mapped to the virtual channel VC0. The mapping of TC0-VC0 is essential / fixed, and the other mappings are controlled from the upper software. The software can control the priority of the transaction by using the traffic class (TC).

d. Flow control Flow control (FC) is performed in order to avoid overflow of the reception buffer and establish the transmission order. Flow control is done point-to-point between links, not end-to-end. Therefore, it cannot be confirmed that the packet has reached the final partner (completer) by flow control.

  PCI Express flow control is performed on a credit basis (mechanism to check the buffer availability on the receiving side before starting data transfer and prevent overflow and underflow). That is, the receiving side notifies the transmitting side of the buffer capacity (credit value) at the time of link initialization, and the transmitting side compares the credit value with the length of the packet to be transmitted, and transmits the packet only when there is a certain remaining. There are six types of credits.

  Flow control information exchange is performed using data link layer packets (DLLP) in the data link layer. The flow control is applied only to the transaction layer packet (TLP) and not to the data link layer packet (DLLP) (DLLP can always be transmitted / received).

B. Data link layer 154
The main role of the data link layer 154 is to provide a reliable transaction layer packet (TLP) exchange function between two components on the link, as described above.

a. Handling of transaction layer packet (TLP) For the transaction layer packet (TLP) received from the transaction layer 153, a 2-byte sequence number at the beginning and a 4-byte link CRC (LCRC) at the end are added to the physical layer. To 155 (see FIG. 9). The transaction layer packet (TLP) is stored in the retry buffer and retransmitted until a reception confirmation (ACK) is received from the partner. When the transmission of the transaction layer packet (TLP) continues to fail, it is determined that the link is abnormal, and the physical layer 155 is requested to retrain the link. If link training fails, the state of the data link layer 154 transitions to inactive.

  The transaction layer packet (TLP) received from the physical layer 155 is inspected for the sequence number and the link CRC (LCRC). If normal, the transaction layer packet (TLP) is passed to the transaction layer 153. If there is an error, a retransmission is requested.

b. Data link layer packet (DLLP)
The transaction layer packet (TLP) is automatically divided into data link layer packets (DLLP) as shown in FIG. 12 and transmitted to each lane when transmitted from the physical layer. A packet generated by the data link layer 154 is called a data link layer packet (DLLP), and is exchanged between the data link layers 154. Data link layer packet (DLLP)
-Ack / Nak: TLP reception confirmation, retry (retransmission)
-InitFC1 / InitFC2 / UpdateFC: Flow control initialization and update-DLLLP for power management
There are different types.

  As shown in FIG. 12, the length of the data link layer packet (DLLP) is 6 bytes. From the DLLP type (1 byte) indicating the type, the information specific to the type of DLLP (3 bytes), and CRC (2 bytes) Composed.

C. Physical layer-logical sub-block 156
The main role of the physical layer 155 in the logical sub-block 156 shown in FIG. 8 is to convert the packet received from the data link layer 154 into a format that can be transmitted by the electrical sub-block 157. It also has a function of controlling / managing the physical layer 155.

a. Data encoding and parallel-serial conversion
PCI Express uses 8B / 10B conversion for data encoding so that consecutive “0” s and “1” s do not continue (in order not to maintain a state where there is no cross point for a long period of time). The converted data is serial-converted and transmitted from the LSB onto the lane as shown in FIG. Here, when there are a plurality of lanes (FIG. 13 illustrates the case of x4 link), data is allocated to each lane in units of bytes before encoding. In this case, it looks like a parallel bus at first glance, but since the transfer is performed independently for each lane, the skew which is a problem with the parallel bus is greatly reduced.

b. Power Management and Link State In order to keep the power consumption of the link low, a link state of L0 / L0s / L1 / L2 is defined as shown in FIG.

  L0 is a normal mode, and power consumption is reduced from L0s to L2, but it takes time to return to L0. As shown in FIG. 15, by actively performing active state power management in addition to software power management, it is possible to reduce power consumption as much as possible.

D. Physical layer—Electric sub-block 157
The main role of the physical layer 155 in the electrical sub-block 157 is to transmit the data serialized in the logical sub-block 156 onto the lane, and to receive the data on the lane and pass it to the logical sub-block 156. is there.

a. AC coupling On the transmission side of the link, a capacitor for AC coupling is mounted. This eliminates the need for the DC common mode voltage on the transmission side and the reception side to be the same. For this reason, it is possible to use different designs, semiconductor processes, and power supply voltages on the transmission side and the reception side.

b. De-emphasis
In PCI Express, as described above, processing is performed so that continuous “0” and “1” do not continue as much as possible by 8B / 10B encoding, but continuous “0” and “1” may continue (maximum). 5 times). In this case, it is specified that the transmission side must perform de-emphasis transfer. When bits of the same polarity are consecutive, it is necessary to increase the noise margin of the signal received on the receiving side by dropping the differential voltage level (amplitude) from the second bit by 3.5 ± 0.5 dB. . This is called de-emphasis. Due to the frequency-dependent attenuation of the transmission line, there are many high-frequency components in the case of changing bits, and the waveform on the receiving side becomes small due to attenuation. Becomes larger. For this reason, de-emphasis is performed in order to make the waveform on the receiving side constant.

[Information processing system]
An information processing system such as a digital copying machine or MFP according to the present embodiment uses a PCI Express standard high-speed serial bus as described above for its internal interface.

  FIG. 16 is a schematic block diagram illustrating a configuration example of the information processing system according to the present embodiment. The information processing system 1 according to the present embodiment is applied to a device such as an MFP, and includes, as its components, a control unit 2, an input unit 3 that is an image input unit, and an output unit 4 that is an image output unit. A processing unit 5 which is an image processing unit and a storage unit 6 are provided. Here, the control unit 2 includes a CPU that controls the entire system according to an installed program (software), and means a device portion (printer controller) that performs processing such as path control and path determination. The input unit 3 is a device or unit for capturing image data based on a document image or the like into the system, and is configured by, for example, a scanner engine that photoelectrically reads a document image and acquires image data. Yes. The output unit 4 is a device or unit that prints out image data on paper or the like, and includes, for example, an electrophotographic plotter (printer) engine. The processing unit 5 is a device or unit portion that performs some kind of image processing such as enlargement / reduction, rotation, etc. on image data, and includes, for example, a magnification changer, a rotator, and a compression / decompression unit. Yes. The storage unit 6 is a device or unit including a memory, HDD, or the like that stores image data. In the present embodiment, the storage unit 6 is configured by, for example, a printer controller.

  With respect to the components of such an information processing system (MFP), in the present embodiment, for example, the processing unit 5 is configured to integrally include the input unit 3 and the output unit 4, and the storage unit 6 (printer controller). Is configured to include the control unit 2 and the devices of the processing unit 5 and the storage unit 6 are connected by the high-speed serial bus 7 according to the PCI Express standard as described above (therefore, the processing unit 5 and the storage unit). 6 has a port).

  In such a configuration, the image data captured from the input unit 3 under the control of the control unit 2 is subjected to image processing by the processing unit 5 as necessary, and then transferred to the storage unit 6 via the high-speed serial bus 7. And temporarily stored in the memory in the storage unit 6. Thereafter, the image data stored in the memory of the storage unit 6 is taken into the processing unit 5 via the high-speed serial bus 7 and is subjected to image processing as necessary, and then transferred to the output unit 4 for printout and the like. .

  In the case of the present embodiment, the processing unit 5 and the storage unit 6 are connected to each other in the information processing system 1 such as an MFP by the high-speed serial bus 7 based on the PCI Express standard. And can be configured by mounting the electrical system of each device on a separate board, greatly expanding design flexibility without sacrificing high-speed performance, and reducing costs by reducing board area Can also be planned.

  Note that the present embodiment shown in FIG. 16 is merely an example, and can be configured in various aspects as shown below, for example.

  In the configuration example shown in FIG. 17, the control unit 2 is provided in the processing unit 5.

  The configuration example shown in FIG. 18 makes the control unit 2 independent by individually connecting the input unit 3, the processing unit 5, the output unit 4, and the storage unit 6 to the control unit 2 through the high-speed serial buses 7a to 7d. The input unit 3, the processing unit 5, the output unit 4, and the storage unit 6 can be handled equivalently. Therefore, the control unit 2 in this case can be easily realized by using, for example, a root complex located at the root in the tree structure of the PCI Express system.

  Thus, for example, the image data captured by the input unit 3 is transferred into the control unit 2 through the high-speed serial bus 7a, transferred to the processing unit 5 through the high-speed serial bus 7b, and necessary image processing is performed. The data can be transferred to the storage unit 6 via the serial paths 7b and 7d and temporarily stored in the memory. In parallel with this, the image data stored in the memory of the storage unit 6 is transferred to the processing unit 5 through the high-speed serial buses 7d and 7b, and necessary image processing is performed, and further output through the high-speed serial paths 7b and 7c. The data can be transferred to the unit 4 and used for printout or the like.

  In the configuration example shown in FIG. 19, the input unit 3, the processing unit 5, and the output unit 4 are individually connected to the storage unit 6 having the control unit 2 by high-speed serial buses 7 a to 7 c, respectively. The unit 3, the processing unit 5, and the output unit 4 can be handled equivalently. As in the case of FIG. 18, the control unit 2 in this case can also use a root complex located at the root in the tree structure of the PCI Express system, for example.

  As a result, for example, image data captured by the input unit 3 is transferred to the storage unit 6 via the high-speed serial bus 7a, transferred to the processing unit 5 via the high-speed serial bus 7b, and necessary image processing is performed. The data can be transferred to the storage unit 6 via the serial path 7b and temporarily stored in the memory. In parallel with this, the image data stored in the memory of the storage unit 6 can be transferred to the output unit 4 via the high-speed serial bus 7c and used for printout or the like.

  In the configuration example shown in FIG. 20, the input unit 3 and the storage unit 6 are interchanged in comparison with FIG. 19. In the configuration example shown in FIG. 21, the processing unit 5 and the storage unit 6 are interchanged in comparison with FIG. 19. The configuration example shown in FIG. 22 is obtained by replacing the output unit 4 and the storage unit 6 with respect to FIG.

  In the configuration example shown in FIG. 23, in the configuration shown in FIG. 18, the switch 8 in the tree structure of the PCI Express system is interposed downstream of the control unit 2 via the high-speed serial bus 7e, and the input unit 3, processing unit 5, the output unit 4 and the storage unit 6 are respectively connected to the downstream ports of the switch 8 by high-speed serial buses 7a to 7d.

  FIGS. 24 to 27 are the same as the configurations shown in FIGS. 19 to 22, respectively, with the switch 8 in the tree structure of the PCI Express system interposed.

  By the way, an example of the optimum configuration of an information processing system in the case where a switch in a tree structure of a PCI Express system is interposed on a PCI Express standard high-speed serial bus path to achieve both expandability and high speed will be described with reference to FIG. To do. The configuration example of the information processing system shown in FIG. 28 is an example of an information processing system constructed by connecting a plurality of devices, not an example of an information processing system having a single configuration like the MFP described above. Basically, first, a plotter (or printer) 11 corresponding to an output unit and image memories 12 and 13 corresponding to a storage unit include a PCI Express standard high-speed serial bus 14a, 14b, 14c and a single-stage PCI. It is connected in the vicinity via an Express standard switch 15. Here, as the image memories 12 and 13, for example, dedicated memories for storing final dot data for printing out by the plotter 11 are used. However, it is not always necessary to use the final dot data, and if there is a real-time compression / decompression unit or the like on the way, a memory for storing the compressed data may be used. As described above, in addition to the basic configuration in which the plotter 11 and the image memories 12 and 13 are connected in the vicinity by the one-stage switch 15, the CPU 16 and the system memory 17 are connected to connect the route complex 18 corresponding to the control unit. May be connected to the upstream side of the switch 15 via a PCI Express standard high-speed serial bus 14d. Furthermore, when there is no timing restriction or it may be delayed, for example, when connecting a scanner 19 as an input unit or an image processing arithmetic unit 20 as a processing unit, an expansion unit is provided downstream of the switch 15. What is necessary is just to connect by the PCI Express standard high-speed serial buses 14e, 14f, and 14g through the PCI Express standard switch 21. That is, by interposing the switch 15, the system can be arbitrarily configured based on the expandability of the switch 15, and it is necessary to transfer image data in synchronization with the line synchronization signal. Since the plotter 11 with strict timing control and the image memories 12 and 13 are connected in the vicinity, a delay in data transfer can be suppressed and high-speed data transfer from the image memory 12 or 13 to the plotter 11 can be handled.

  In the system configuration example shown in FIG. 28, since the interface is common, the MFP 22 having both the scanner as the input unit and the plotter as the output unit is also compatible with the switch 15 according to the PCI Express standard. An example of connection via a high-speed serial bus 14h is shown. Also in this case, the plotter in the MFP 22 and the image memories 12 and 13 are connected in the vicinity via the one-stage switch 15 and are synchronized with the line synchronization signal from the image memory 12 or 13 to the plotter. The transferred image data can be transferred without delay.

  Data transfer in these configuration examples will be further described. For example, FIG. 16, FIG. 17, FIG. 19 and FIG. 23 to FIG. 27 can transfer data directly from the input unit 3 to the storage unit 6 and transfer data directly from the storage unit 6 to the output unit 4. As an example of data transfer applicable to the configuration example, image data is transferred from the input unit 3 to the storage unit 6 in synchronization with the line synchronization signal by the high-speed serial bus 7, and the image data is synchronized with the line synchronization signal. Basically, the data is transferred from the storage unit 6 to the output unit 4. In this case, it is preferable to adopt a transfer method in which data transfer from the storage unit 6 to the output unit 4 is performed with priority over data transfer from the input unit 3 to the storage unit 6.

  More specifically, in the present embodiment, a transfer method in which the input unit 3 and the output unit 4 are image data transfer initiators is used, the input unit 3 uses a memory write transaction, and the output unit 4 uses a memory read transaction. A data transfer method is used, and these two transactions are assigned to different traffic classes TC. At this time, by setting the virtual channel VC, the priority of the traffic class TC of the memory read transaction of the output unit 4 is made higher than the priority of the traffic class TC of the memory write transaction of the input unit 3, and all the memory read transactions are issued. By setting the strict priority so that a memory write transaction is issued after that, it is possible to output image data at high speed even when there is a timing restriction on line synchronous transfer, and to simultaneously transfer multiple image data Can do.

  FIG. 29 is a schematic timing chart showing a conventional command issue order. In FIG. 29A, the read request command MemReadReq. And the write request command MemWriteReq. Of the image data are transmitted using the high-speed serial bus 7 without setting the priority in synchronization with the line synchronization signal XLDSYNC and the read request command MemReadReq. The operation example in the case of receiving the read data MemReadComp. According to the above shows an example of the case where the read data MemReadComp. Cannot be received within the line valid period XLGATE due to the timing constraint of the line synchronous transfer.

  On the other hand, FIG. 29-2 shows the priority of the traffic class TC of the memory read transaction (read request command MemReadReq.) Of the output unit 4 (Engine TX) in the case similar to the above, as described above. 3 (Engine RX) memory write transaction (write request command MemWriteReq.) Higher than the priority of traffic class TC, and set the strict priority so that the memory write transaction is issued after all memory read transactions are issued Therefore, even if there are timing restrictions on line synchronous transfer, image data can be output at high speed, read data MemReadComp. Can be received within the line valid period XLGATE, and multiple image data transfers can be performed simultaneously. .

  However, even when the command is issued as shown in FIG. 29-2, the image data transfer is performed due to the influence of the influence of the path delay (the dispersion due to the change in the connection configuration, the timing dispersion due to the competing data transfer, etc.). May not be performed normally. That is, there may be a case where the read data MemReadComp. Cannot be received within the line valid period XLGATE as in the case of FIG.

  Here, FIG. 30 is a characteristic diagram exemplarily showing the influence of delay in the case of passing through the switch and in the case of not passing through the switch. As shown in FIG. 30, when passing through a switch that is one of the delay elements in the path, the delay differs depending on the difference in the mounting method (for example, memory mounting method) inside the switch (structure 1-3). It can be seen that the characteristics change due to the variation. Here, the difference in the memory mounting method is whether it is a dual port memory or a single port memory.

  FIG. 31 is a characteristic diagram exemplarily showing the influence of the delay due to the change in the number of stages when passing through the switch. As shown in FIG. 31, it can be seen that the variation in characteristics is further increased by changing the number of stages of switches, which is one of the delay elements in the path.

  Therefore, in this embodiment, commands are issued according to a timing chart as shown in FIG. More specifically, the read request command MemReadReq. Is issued using a request-dedicated synchronization signal (XREQSYNC) that is independent of the line synchronization signal (XLGATE) for image data transfer. The request-dedicated synchronization signal (XREQSYNC) is, for example, a signal having the same period and a different phase from the line synchronization signal (XLGATE) for transferring image data. That is, in the command issuance as shown in FIG. 29-2, the read request command MemReadReq. Is issued after the line synchronization signal (XLGATE) for image data transfer falls, but the line for image data transfer When the line synchronization signal for image data transfer (XLGATE) falls using the request dedicated synchronization signal (XREQSYNC) separately from the synchronization signal (XLGATE), the issue of the read request command MemReadReq. I did it. This increases the delay margin for receiving the read data MemReadComp. Within the line valid period XLGATE of the line synchronization signal for image data transfer, so variations in the effects of path delay (variations due to changes in connection configuration, competitive data transfer, etc.) This increases the scalability, and the expandability is improved. That is, even if there is a timing restriction for line synchronous transfer, high-speed image data output and simultaneous transfer can be performed without wasting resources.

  The phase difference between the request-dedicated synchronization signal (XREQSYNC) and the image data transfer line synchronization signal (XLGATE) can be measured using a delay amount measurement packet. FIG. 33 is a block diagram exemplarily showing a PCI Express system including a delay amount detection circuit. As shown in FIG. 33, a route complex (phase difference measuring means) 31 corresponding to the control unit to which the CPU 30 is connected includes a measurement packet generation circuit 31a that is a measurement packet generation unit and a delay that is a delay amount detection unit. An amount detection circuit 31b and a delay amount storage circuit 31c as a delay amount storage unit are provided. The delay amount detection circuit 31b detects the delay amount (delay time) based on the output time of the delay amount measurement packet generated by the measurement packet generation circuit 31a and the reception time of the return packet from the end point 32. The detected delay amount (delay time) is stored in the delay amount storage circuit 31c. Then, the CPU 30 controls the phase difference between the request dedicated synchronization signal (XREQSYNC) and the image data transfer line synchronization signal (XLGATE) according to the delay amount (delay time) stored in the delay amount storage circuit 31c. Even when there is a dynamic variation in the delay amount, the request-dedicated synchronization signal (XREQSYNC) can always be generated based on the actual measurement value.

  Here, the image data is transferred from the input unit 3 to the storage unit 6 in synchronization with the line synchronization signal by the high-speed serial bus 7 through the switch 8 (same for the switch 15), and in synchronization with the line synchronization signal. When transferring image data from the storage unit 6 to the output unit 4, a transfer method that preferentially performs data transfer from the storage unit 6 to the output unit 4 over data transfer from the input unit 3 to the storage unit 6. The mechanism will be described with reference to FIG. The example shown in FIG. 34 is a configuration example in which nodes 1, 2, and 3 are physically connected to different ports B, D, and E of the switch 8 by one port A, C, and F, respectively. In this example, the node 1 corresponds to the input unit 3, the node 2 corresponds to the output unit 4, and the node 3 corresponds to the storage unit 6.

  Here, the transfer method in which the input unit 3 and the output unit 4 are image data transfer initiators, the input unit 3 uses a memory write transaction, the output unit 4 uses a memory read transaction, and these In this method, two transactions are assigned to the same traffic class TC. In the example of this embodiment, four traffic classes TC indicated by TC0 to TC3 are assigned, and four routes indicated by changing line types are assigned to these two transactions to the same traffic class TC. It shows how it is. Each port A, C, F in each node 1, 2, 3 is provided with virtual channels VC0-VC3 that can be prioritized for traffic classes TC0-TC3 in accordance with the PCI Express standard. It is set to which virtual channel VC0 to VC3 TC3 is allocated. Virtual channels VC0 to VC3 corresponding to the ports A, C, and F are also assigned to the input ports B and D and the output port E on the switch 8 side. Here, VC arbitration 9a for arbitrating and serializing the virtual channels VC0 to VC3 of the ports A and B, VC arbitration 9b for arbitrating and serializing the virtual channels VC0 to VC3 of the ports C and D, ports E, A VC arbitration 9c is provided in each of the ports A, C, E for arbitrating between the F virtual channels VC0 to VC3 and serializing them.

  In addition to such a configuration, the switch 8 is connected to the ports B and D and transfers image data from the node 3 (storage unit 6) to the node 2 (output unit 4). Port arbitration 10 that performs arbitration for port E is provided so as to preferentially transfer image data from node 3) to node 3 (storage unit 6). In the port arbitration 10, when there are two traffics from the ports B and D, the traffics of the same traffic class TC0 to TC3 are once collected and the input ports B and B are assigned to the same virtual channels VC0 to VC3. Arbitration is performed according to the set priority, and the virtual channels VC0 to VC3 remaining after being arbitrated due to the difference between the input ports B and D are serialized by the VC arbitration 9c to obtain node 3 (storage unit 6). ) Side for transfer output.

  Transfer of image data from the node 3 (storage unit 6) to the node 2 (output unit 4) is transferred from the node 1 (input unit 3) to the node 3 (storage unit 6) by such a mechanism according to the PCI Express standard. However, according to the PCI Express standard, the round-robin (RR), the weighted round-robin (WRR), and the time distribution algorithm are used in the port arbitration 10 in this case. Any algorithm of time based weighted round robin (TBWRR) including concept management may be used. Here, when using an algorithm called weighted round robin (WRR), it is preferable to consider the payload size together. Incidentally, even when using an algorithm such as round robin (RR) or time base weighted round robin (TBWRR), it is preferable to consider the payload size. By considering the payload size, more precise priority control can be realized.

  The basic characteristics of each of these algorithms when the four types of data transfer of the traffic classes TC0 to TC3 are performed, including the strict algorithm described above, will be briefly described with reference to FIG. In any case, since the measurement result of the arbitration characteristic needs to observe a dynamic fluctuation, it is shown as a data integration diagram in FIG. In the figure, the horizontal axis represents time, and the vertical axis represents the amount of transferred data (integrated value). Note that the payload size is an example of measurement under the condition of 128 bytes (about 8000) for all four types. FIG. 35A shows a strict characteristic, which is an algorithm that simply flows data in order. FIG. 35-2 shows a round robin (RR) characteristic, which is an algorithm in which four types of data are flowed while being equally divided in order. In the drawing, the four types of characteristics are represented by overlapping one characteristic. Yes. FIG. 35-3 shows an example of characteristics when weighted round robin (WRR) characteristics are set so that data transfer is performed at a ratio of 1: 2: 4: 8 for the four types, and data transfer of one traffic class is performed. When finished, the algorithm is such that the data is transferred while changing the ratio of the remaining traffic class, such as 8: 4: 2 and further 8: 4. Time-based weighted round robin (TBWRR) is a weighted round robin (WRR) that includes the management of the concept of time.

  FIG. 36 shows the basic characteristics of the payload when measured by the strict algorithm. As can be seen from FIG. 36, the smaller the payload size, the slower the transfer rate, and the larger the payload size, the larger the transfer rate. Such payload characteristics are the same when other arbitration algorithms are used. In particular, in the case of a weighted round robin (WRR) algorithm, the payload size is determined in order to determine the transfer rate according to the ratio. It is effective to consider

  A PCI Express standard switch 8 is interposed on the high-speed serial bus 7 path, and the input unit 3, the output unit 4, and the storage unit 6 are connected to different ports of the switch 8, respectively. Two transactions that transfer image data from the input unit 3 to the storage unit 6 in synchronization with the synchronization signal and transfer image data from the storage unit 6 to the output unit 4 in synchronization with the line synchronization signal are performed in different traffic classes TC. 34, with reference to FIG. 34, the transfer of image data from the storage unit 6 to the output unit 4 is input by setting the strict priority of the arbitration 9c of the virtual channel VC of the output port E in the switch 8. It is desirable that the image data be transferred with priority from the unit 3 to the storage unit 6.

  On the other hand, for example, the data can be directly transferred from the processing unit 5 to the storage unit 6 and can be directly transferred from the storage unit 6 to the output unit 4. As an example of data transfer applicable to the 27 configuration examples, the high-speed serial bus 7 transfers image data from the processing unit 5 to the storage unit 6 in synchronization with the line synchronization signal, and also synchronizes with the line synchronization signal. Basically, data is transferred from the storage unit 6 to the output unit 4. In this case, it is preferable to adopt a transfer method in which data transfer from the storage unit 6 to the output unit 4 is performed with priority over data transfer from the processing unit 5 to the storage unit 6.

  More specifically, in the present embodiment, a transfer method in which the processing unit 5 and the output unit 4 are initiators of image data transfer is used, the processing unit 5 uses a memory write transaction, and the output unit 4 uses a memory read transaction. A data transfer method is used, and these two transactions are assigned to different traffic classes TC. At this time, by setting the virtual channel VC, the priority of the traffic class TC of the memory read transaction of the output unit 4 is made higher than the priority of the traffic class TC of the memory write transaction of the processing unit 5, and all the memory read transactions are issued. By setting the strict priority so that a memory write transaction is issued after that, it is possible to output image data at high speed even when there is a timing restriction on line synchronous transfer, and to simultaneously transfer multiple image data Can do.

  In this case as well, the example shown in FIG. 28 can be applied.

It is a block diagram which shows the structural example of the existing PCI system. FIG. 2 is a block diagram illustrating a configuration example of a PCI Express system. It is a block diagram which shows the structural example of the PCI Express platform in desktop / mobile. It is a schematic diagram which shows the structural example of the physical layer in the case of x4. It is a schematic diagram which shows the example of lane connection between devices. It is a block diagram which shows the logical structural example of a switch. It is a block diagram which shows the architecture of the existing PCI. It is a block diagram which shows the architecture of PCI Express. It is a block diagram which shows the hierarchical structure of PCI Express. It is explanatory drawing which shows the format example of a transaction layer packet. It is explanatory drawing which shows the configuration space of PCI Express. It is a schematic diagram for demonstrating the concept of a virtual channel. It is explanatory drawing which shows the format example of a data link layer packet. It is a schematic diagram which shows the byte striping example in x4 link. It is explanatory drawing explaining the definition of the link state of L0 / L0s / L1 / L2. It is a time chart which shows the example of control of active state power management. It is a schematic block diagram which shows the structural example of the information processing system of one Embodiment of this invention. It is a block diagram which shows the modification structural example schematically. It is a block diagram which shows the modification structural example schematically. It is a block diagram which shows the modification structural example schematically. It is a block diagram which shows the modification structural example schematically. It is a block diagram which shows the modification structural example schematically. It is a block diagram which shows the modification structural example schematically. It is a block diagram which shows the modification structural example schematically. It is a block diagram which shows the modification structural example schematically. It is a block diagram which shows the modification structural example schematically. It is a block diagram which shows the modification structural example schematically. It is a block diagram which shows the modification structural example schematically. It is a schematic block diagram which shows the example of an optimal structure of an information processing system. It is a typical timing chart which shows the conventional command issue order. It is a typical timing chart which shows the conventional command issue order. It is a characteristic view which shows the influence of the delay in the case where it does not pass through the case where it goes through via a switch. It is a characteristic view which shows the influence of the delay by the change of the stage number at the time of passing through a switch exemplarily. It is a typical timing chart which shows command issue order. 1 is a configuration diagram exemplarily showing a PCI Express system including a delay amount detection unit. FIG. It is a schematic block diagram which shows the structure of a data transfer system. It is explanatory drawing which shows arbitration characteristic. It is explanatory drawing which shows arbitration characteristic. It is explanatory drawing which shows arbitration characteristic. It is a characteristic view which shows the basic characteristic of a payload.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 Information processing system 2 Printer controller 3 Image input part 4 Image output part 5 Image processing part 7 High-speed serial bus 31 Phase difference measurement means 31a Measurement packet generation part 31b Delay amount detection part 31c Delay amount storage part

Claims (19)

The serial bus, in the information processing system that performs a plurality of image data transfer at the same time,
Before the image data in accordance with carboxymethyl real buses timing constraints of line synchronizing transfer, using a different request only synchronization signal and line synchronization signal for image data transfer, fall line synchronizing signal for the image data transfer The issue of the read request command was finished when
An information processing system characterized by this. The serial bus, in the information processing system that performs a plurality of image data transfer at the same time,
The transfer of image data to the image output unit from the printer controller synchronized previously carboxymethyl real bus by the line synchronizing signal, the line synchronizing signal of the image data transferred using different request only synchronization signal, the image data transfer The issue of read request command is finished when the line sync signal for
An information processing system characterized by this. Data in which the image input unit that transfers image data to the printer controller uses a memory write transaction, and the image output unit uses a memory read transaction so that the image input unit and the image output unit are initiators of image data transfer. Let the data transfer by the transfer method,
The information processing system according to claim 2. Assigned two transactions to different traffic classes TC.
The information processing system according to claim 2. Due to the setting of the virtual channel, the priority of the traffic class TC of the memory read transaction of the image output unit is made higher than the priority of the traffic class TC of the memory write transaction of the image input unit.
The information processing system according to claim 4. The strict priority is set so that the memory write transaction is issued after all the memory read transactions are issued.
The information processing system according to claim 5. The serial bus, in the information processing system that performs a plurality of image data transfer at the same time,
The transfer of image data to the image output unit from the printer controller synchronized previously carboxymethyl real bus by the line synchronizing signal, the line synchronizing signal of the image data transferred using different request only synchronization signal, the image data transfer The issue of read request command is finished when the line sync signal for
An information processing system characterized by this. The image processing unit for transferring image data to the printer controller uses a memory write transaction, and the image output unit uses a memory read transaction so that the image processing unit and the image output unit serve as initiators for image data transfer. Let the data transfer by the transfer method,
The information processing system according to claim 7. Assigned two transactions to different traffic classes TC.
The information processing system according to claim 7. Due to the setting of the virtual channel, the priority of the traffic class TC of the memory read transaction of the image output unit is made higher than the priority of the traffic class TC of the memory write transaction of the image processing unit,
The information processing system according to claim 9. The strict priority is set so that the memory write transaction is issued after all the memory read transactions are issued.
The information processing system according to claim 10. The request-dedicated synchronization signal is a signal having the same period and only a phase different from the line synchronization signal for image data transfer.
The information processing system according to claim 1, wherein the information processing system is an information processing system. A phase difference measuring means for measuring the phase difference between the request-dedicated synchronization signal and the image data transfer line synchronization signal;
Generating the request-dedicated synchronization signal from the line synchronization signal for image data transfer based on the phase difference amount measured by the phase difference measuring means;
The information processing system according to claim 12. The phase difference measuring means includes a measurement packet generator that generates a delay measurement packet, an output time of the delay measurement packet generated by the measurement packet generator, and a reception time of a return packet from the end point. A delay amount detection unit that originally detects the delay amount, and a delay amount storage unit that stores the delay amount detected by the delay amount detection unit,
The information processing system according to claim 13. Before carboxymethyl real bus is a high-speed serial bus of the PCI Express standard,
The information processing system according to any one of claims 1 to 14, wherein The serial bus, a program for executing the simultaneous transmission of a plurality of image data to the computer,
Before the image data in accordance with carboxymethyl real buses timing constraints of line synchronizing transfer, using a different request only synchronization signal and line synchronization signal for image data transfer, fall line synchronizing signal for the image data transfer The issue of the read request command was finished when
A program characterized by that. The serial bus, a program for executing the simultaneous transmission of a plurality of image data to the computer,
The transfer of image data to the image output unit from the printer controller synchronized previously carboxymethyl real bus by the line synchronizing signal, the line synchronizing signal of the image data transferred using different request only synchronization signal, the image data transfer The issue of read request command is finished when the line sync signal for
A program characterized by that. The serial bus, the data transfer method of performing a plurality of image data transfer at the same time,
Before the image data in accordance with carboxymethyl real buses timing constraints of line synchronizing transfer, using a different request only synchronization signal and line synchronization signal for image data transfer, fall line synchronizing signal for the image data transfer The issue of the read request command was finished when
A data transfer method characterized by the above. The serial bus, the data transfer method of performing a plurality of image data transfer at the same time,
The transfer of image data to the image output unit from the printer controller synchronized previously carboxymethyl real bus by the line synchronizing signal, the line synchronizing signal of the image data transferred using different request only synchronization signal, the image data transfer The issue of read request command is finished when the line sync signal for
A data transfer method characterized by the above.

Images