JP2007062076A - Information processing system, program, and data transferring method - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To accelerate the processing when a large amount of copies are output. <P>SOLUTION: When a plurality of copies of image data are printed, a rout complex 6 transmits a plurality of copies of the image data at the same timing to at least two image forming devices 9 located under a switch 7 through the switch 7. Thus, a simultaneous printing regarding the same image data in all image forming devices 9, i.e., a large number of copies can simultaneously be printed. Therefore, the printing period of time can be shortened, and the process when a large number of copies are output can be accelerated. At the same time, by broadcast-transmitting by a message packet, the quantity of lanes for links of high speed serial buses 8 and 10 by PCI Express regulation may respectively be "x1", and in the link on the upstream side, the number of lanes of the links for the number of units of the image forming devices 9 becomes unnecessary, and the number of lanes for the links can be reduced. <P>COPYRIGHT: (C)2007,JPO&INPIT

Description

  The present invention relates to an information processing system, a program, and a data transfer method.

  In recent years, an interface called PCI Express (registered trademark), which is a successor to the PCI bus system, has been proposed as a high-speed serial interface, and has been put into practical use (for example, see Non-Patent Document 1). This PCI Express system is schematically configured as a data communication network having a tree structure (tree structure) such as a root complex-switch (arbitrary hierarchy) -device as shown in FIG. Has been.

“Outline of PCI Express Standard” Interface, July’2003 Naoshi Satomi

  However, the PCI Express standard as described in Non-Patent Document 1 is configured as a data communication network having a tree structure (tree structure) such as a root complex, a switch (arbitrary layer), and a device. If a large amount of data is transmitted using a route through the root complex located at the root of the (tree structure), the data transfer speed cannot be increased, and the processing when a large number of copies are output In some cases, the speed cannot be increased.

  The present invention has been made in view of the above, and an object thereof is to increase the processing speed when a large number of copies are output.

  In order to solve the above-described problems and achieve the object, an information processing system according to claim 1 includes at least two or more image forming apparatuses capable of forming an image on a medium such as paper based on image data; A switch that connects these image forming apparatuses via a high-speed serial bus, and a root complex that is positioned above the switch and that connects the switch via a high-speed serial bus and transmits the image data to the switch And comprising.

  According to a second aspect of the present invention, in the information processing system according to the first aspect, the root complex is provided in multiple stages and the switches are connected by a high-speed serial bus.

  According to a third aspect of the present invention, in the information processing system according to the first or second aspect, the high-speed serial bus is a PCI Express standard high-speed serial bus.

  According to a fourth aspect of the present invention, there is provided the information processing system according to the third aspect, wherein the root complex includes the image data when the image data is formed by at least two image forming apparatuses. A data packet using a standard message packet is generated, and the data packet is transmitted to the switch using a broadcast mode of the PCI Express standard. The switch broadcasts the data packet transmitted from an upstream port. When transmission is designated, the image data of the data packet is copied and transmitted to all downstream ports.

According to a fifth aspect of the present invention, in the information processing system according to the fourth aspect, when the route complex broadcasts a data packet using a PCI Express standard message packet including the image data, the PCI Express standard The structure of the TLP (Transaction Layer Packet) header
Fmt: 11 (MsgD)
Type: 10011 (broadcast)
Code: 0111 1110 or 0111 1111 (Vendor-Defined)
Length: The size of the data payload is set, and the message packet including the image data to be transmitted to the data payload is generated.

  According to a sixth aspect of the present invention, in the information processing system according to the third aspect, the root complex reads the image data from the input unit when the image data is formed by at least two image forming apparatuses. The image data is distributed to the addresses of the image forming apparatuses.

  According to a seventh aspect of the present invention, in the information processing system according to any one of the first to sixth aspects, a high-speed printer is used as each of the image forming apparatuses.

  According to an eighth aspect of the present invention, in the information processing system according to any one of the first to sixth aspects, a low-speed printer is used as each of the image forming apparatuses.

  According to a ninth aspect of the present invention, there is provided a program that connects at least two or more image forming apparatuses capable of forming an image on a medium such as paper on the basis of image data by a PCI Express standard high-speed serial bus. On the other hand, a program for operating a computer provided in a controller connected by a PCI Express standard high-speed serial bus, wherein the image data is formed by at least two or more image forming apparatuses. A data packet using a PCI Express standard message packet is generated, and the data packet is transmitted to the switch using a PCI Express standard broadcast mode.

According to a tenth aspect of the present invention, in the program according to the ninth aspect, when a data packet using a PCI Express standard message packet including the image data is broadcasted, a PCI Express standard TLP (Transaction Layer Packet) Header configuration
Fmt: 11 (MsgD)
Type: 10011 (broadcast)
Code: 0111 1110 or 0111 1111 (Vendor-Defined)
Length: The size of the data payload is set, and the message packet including the image data to be transmitted to the data payload is generated.

  According to another aspect of the present invention, there is provided a program that connects at least two or more image forming apparatuses capable of forming an image on a medium such as a sheet based on image data by a PCI Express standard high-speed serial bus. On the other hand, a program for operating a computer provided in a controller connected by a PCI Express standard high-speed serial bus, wherein the image data is formed by at least two or more image forming apparatuses. Are assigned to the addresses of the image forming apparatuses.

  In the data transfer method according to the twelfth aspect of the present invention, at least two or more image forming apparatuses capable of forming an image on a medium such as paper based on the image data are connected to each other by a PCI Express standard high-speed serial bus. A data transfer method in a controller connected to a switch by a PCI Express standard high-speed serial bus, wherein the image data is formed by at least two or more image forming apparatuses. A data packet using an Express standard message packet is generated, and the data packet is transmitted to the switch using a PCI Express standard broadcast mode.

According to a thirteenth aspect of the present invention, in the data transfer method according to the twelfth aspect, when a data packet using a PCI Express standard message packet including the image data is broadcasted, a PCI Express standard TLP (Transaction Layer) is transmitted. Packet) header configuration
Fmt: 11 (MsgD)
Type: 10011 (broadcast)
Code: 0111 1110 or 0111 1111 (Vendor-Defined)
Length: The size of the data payload is set, and the message packet including the image data to be transmitted to the data payload is generated.

  In the data transfer method according to the fourteenth aspect of the present invention, at least two or more image forming apparatuses capable of forming an image on a medium such as paper based on the image data are respectively connected by a PCI Express standard high-speed serial bus. A data transfer method in a controller connected to a switch by a PCI Express standard high-speed serial bus, and when the image data is formed by at least two or more image forming apparatuses, the image data Assign to the address of the image forming apparatus.

  According to the first aspect of the present invention, when printing a plurality of copies of image data, the root complex has a plurality of copies at the same timing via the switch to at least two or more image forming apparatuses positioned below the switch. By sending the image data, it is possible to print the same image data in all image forming devices simultaneously, that is, to print multiple copies at the same time, thus shortening the printing time and outputting a large number of copies. In this case, the processing speed can be increased.

  Further, according to the invention of claim 2, the system can be expanded by providing the root complex in multiple stages and connecting the switches with a high-speed serial bus.

  According to the invention of claim 3, the high-speed serial bus is a PCI Express standard high-speed serial bus, so that low-voltage differential signal transmission, point-to-point independent transmission and reception communication channels, and packetization It has the effect of having features such as high scalability due to differences in split transactions and link configurations.

  According to the fourth aspect of the present invention, since the number of lanes of the link of the high-speed serial bus according to the PCI Express standard may be “x1” by broadcasting by message packet, image formation is performed on the upstream link. There is no need for the number of link lanes corresponding to the number of devices, and the number of link lanes can be reduced.

  In addition, according to the fifth aspect of the present invention, there is an effect that image data addressed to the image forming apparatus as all end points can be transmitted from the root complex.

  According to the invention of claim 6, the number of link lanes upstream of the switch is required by the number of link lanes downstream of the switch (that is, the number of link lanes corresponding to the number of image forming apparatuses). However, it is possible to increase the processing speed when outputting a large number of copies.

  Further, according to the seventh aspect of the present invention, it is possible to further increase the speed by using a high-speed printer as the image forming apparatus.

  According to the invention of claim 8, by using a low-speed printer as the image forming apparatus, simultaneous printing of the same image data in all low-speed printers, that is, by simultaneously printing a large number of copies, low speed is achieved. Even with this printer, the speed can be increased.

  According to the ninth aspect of the present invention, the same image data in all the image forming apparatuses can be simultaneously printed, that is, multiple copies can be simultaneously printed. In the case where the number of copies is output, the processing speed can be increased, and the number of lanes of the link of the high-speed serial bus according to the PCI Express standard can be “x1” by broadcast transmission using message packets. The number of link lanes corresponding to the number of image forming apparatuses is unnecessary for the link on the side, and the number of link lanes can be reduced.

  In addition, according to the tenth aspect of the invention, it is possible to transmit image data addressed to the image forming apparatus as all end points from the root complex.

  According to the invention of claim 11, the number of link lanes upstream of the switch is required by the number of link lanes downstream of the switch (that is, the number of link lanes corresponding to the number of image forming apparatuses). However, it is possible to increase the processing speed when outputting a large number of copies.

  According to the invention of claim 12, since the same image data in all image forming apparatuses can be simultaneously printed, that is, multiple copies can be simultaneously printed, the printing time can be shortened, In the case where the number of copies is output, the processing speed can be increased, and the number of lanes of the link of the high-speed serial bus according to the PCI Express standard can be “x1” by broadcast transmission using message packets. The number of link lanes corresponding to the number of image forming apparatuses is unnecessary for the link on the side, and the number of link lanes can be reduced.

  Further, according to the thirteenth aspect of the invention, there is an effect that image data addressed to the image forming apparatus as all end points can be transmitted from the root complex.

  According to the fourteenth aspect of the present invention, the number of lanes on the upstream side of the switch is required by the number of lanes on the downstream side of the switch (that is, the number of link lanes corresponding to the number of image forming apparatuses). However, it is possible to increase the processing speed when outputting a large number of copies.

  Exemplary embodiments of an information processing system, a program, and a data transfer method according to the present invention will be explained below in detail with reference to the accompanying drawings.

[First Embodiment]
A first embodiment of the present invention will be described with reference to FIGS. In the following, details of PCI Express will be described in the columns [Outline of PCI Express Standard] to [Details of Architecture of PCI Express], and then the information processing system according to the present embodiment will be described in the [Information Processing System] column. I will explain it.

[Outline of PCI Express standard]
First, this embodiment uses PCI Express (registered trademark), which is one of high-speed serial buses. As an assumption of this embodiment, an outline of the PCI Express standard is a part of Non-Patent Document 1. Explained with excerpts. Here, the high-speed serial bus means an interface capable of exchanging data at high speed (about 100 Mbps or more) by serial (serial) transmission using a single transmission line.

  PCI Express is a standardized expansion bus that can be used for all computers as a successor to PCI. In general, low-voltage differential signal transmission, point-to-point independent communication channels, and packetization Split transactions and high scalability due to differences in link configuration.

  FIG. 1 shows a configuration example of an existing PCI system, and FIG. 2 shows a configuration example of a PCI Express system. In an existing PCI system, PCI-X (PCI upward compatible standard) devices 104a and 104b connect a PCI-X bridge 105a to a host bridge 103 to which a CPU 100, AGP graphics 101, and memory 102 are connected. Or a PCI bridge 105b to which the PCI devices 104c and 104d are connected and a PCI bridge 107 to which the PCI bus slot 106 is connected are connected via the PCI bridge 105c (tree structure). Yes.

  On the other hand, in the PCI Express system, the PCI Express graphics 113 is connected by the PCI Express 114a to the root complex 112 to which the CPU 110 and the memory 111 are connected, and the endpoint 115a and the legacy endpoint 116a. PCI Express 114b connects the switch 117a to which the PCI Express 114b is connected, and the PCI bridge 119 to which the switch 117b to which the endpoint 115b and the legacy endpoint 116b are connected by the PCI Express 114d and the PCI bus slot 118 are connected. The switch 117c connected by the Express 114e has a tree structure (tree structure) connected by the PCI Express 114f.

  An example of an actually assumed PCI Express platform is shown in FIG. The illustrated example shows an application example to desktop / mobile. For example, graphics 125 is x16 with respect to a memory hub 124 (corresponding to a root complex) to which a CPU 121 is connected by a CPU host bus 122 and a memory 123 is connected. PCI Express 126a and an I / O hub 127 having a conversion function are connected by PCI Express 126b. For example, a storage 129 is connected to the I / O hub 127 by a Serial ATA 128, a local I / O 131 is connected by an LPC 130, and a USB 2.0 132 and a PCI bus slot 133 are connected. Further, a switch 134 is connected to the I / O hub 127 by a PCI Express 126c, and the mobile dock 135, Gigabit Ethernet 136 (Ethernet is a registered trademark), and an add-in are connected to the switch 134 by PCI Express 126d, 126e, and 126f, respectively. A card 137 is connected.

  That is, in the PCI Express system, the conventional PCI, PCI-X, AGP bus is replaced with PCI Express, and a bridge is used to connect an existing PCI / PCI-X device. Connection between chipsets is also PCI Express connection, and existing buses such as IEEE1394, Serial ATA, and USB 2.0 are connected to PCI Express by an I / O hub.

[Components of PCI Express]
A. Port / Lane / Link
FIG. 4 shows the structure of the physical layer. A port is a set of transmitters / receivers that are physically in the same semiconductor and form a link, and logically means an interface that connects component links in a one-to-one relationship (point-to-point). . The transfer rate is, for example, 2.5 Gbps in one direction. The lane is, for example, a set of 0.8 V differential signal pairs, and includes a transmission-side signal pair (two) and a reception-side signal pair (two). A link is a collection of lanes connecting two ports and the two ports, and is a dual simplex communication bus between components. The “xN link” is composed of N lanes, and N = 1, 2, 4, 8, 16, 32 are defined in the current standard. The illustrated example is an x4 link example. For example, as shown in FIG. 5, by changing the lane width N connecting the devices A and B, a scalable bandwidth can be configured.

B. Root Complex
The root complex 112 is located at the highest level of the I / O structure, and connects the CPU and the memory subsystem to the I / O. In a block diagram or the like, as shown in FIG. 3, it is often described as “memory hub”. The root complex 112 (or 124) has one or more PCI Express ports (root ports) (indicated by squares in the root complex 112 in FIG. 2), and each port is an independent I / O hierarchical domain. Form. The I / O hierarchical domain is a simple endpoint (for example, the example of the endpoint 115a side in FIG. 2), or is formed from a large number of switches and endpoints (for example, the endpoint in FIG. 2). 115b and switches 117b and 115c side).

C. End point
The endpoint 115 is a device having a configuration space header of type 00h (specifically, a device other than a bridge), and is divided into a legacy endpoint and a PCI Express endpoint. The major difference between the two is that the PCI Express endpoint does not request I / O resources in the BAR (Base Address Register), and therefore does not request an I / O request. PCI Express endpoints also do not support lock requests.

D. Switch
The switch 117 (or 134) couples two or more ports and performs packet routing between the ports. From the configuration software, the switch is recognized as a collection of virtual PCI-PCI bridges 141 as shown in FIG. In the figure, double arrows indicate the PCI Express link 114 (or 126), and 142a to 142d indicate ports. Among these, the port 142a is an upstream port closer to the root complex, and the ports 142b to 142d are downstream ports farther from the root complex.

E. PCI Express 114e-PCI bridge 119
Provides connection from PCI Express to PCI / PCI-X. Thereby, an existing PCI / PCI-X device can be used on the PCI Express system.

[Hierarchical architecture]
As shown in FIG. 7A, the conventional PCI architecture has a structure in which protocols and signaling are closely related and there is no concept of hierarchy. In PCI Express, as shown in FIG. Like the standard communication protocol and InfiniBand, it has an independent hierarchical structure, and specifications are defined for each layer. In other words, a transaction layer 153, a data link layer 154, and a physical layer 155 are provided between the uppermost software 151 and the lowermost mechanism (mechanical) unit 152. Thereby, the modularity of each layer is ensured, and it becomes possible to provide scalability and reuse the module. For example, when adopting a new signal coding method or transmission medium, it is possible to cope with only changing the physical layer without changing the data link layer or the transaction layer.

  The core of the PCI Express architecture is a transaction layer 153, a data link layer 154, and a physical layer 155, each having the following roles described with reference to FIG.

A. Transaction layer 153
The transaction layer 153 is located at the highest level and has a function of assembling and disassembling a transaction layer packet (TLP). The transaction layer packet (TLP) is used for transmission of transactions such as read / write and various events. The transaction layer 153 performs flow control using credits for transaction layer packets (TLP). An outline of a transaction layer packet (TLP) in each of the layers 153 to 155 is shown in FIG. 9 (details will be described later).

B. Data link layer 154
The main role of the data link layer 154 is to guarantee data integrity of the transaction layer packet (TLP) by error detection / correction (retransmission) and link management. Packets for link management and flow control are exchanged between the data link layers 154. This packet is called a data link layer packet (DLLP) to distinguish it from a transaction layer packet (TLP).

C. Physical layer 155
The physical layer 155 includes circuits necessary for interface operations such as a driver, an input buffer, a parallel-serial / serial-parallel converter, a PLL, and an impedance matching circuit. It also has interface initialization / maintenance functions as logical functions. The physical layer 155 also serves to make the data link layer 154 / transaction layer 153 independent of the signaling technology used in the actual link.

  The PCI Express hardware configuration employs a technology called embedded clock, there is no clock signal, the clock timing is embedded in the data signal, and the receiving side is based on the cross-point of the data signal. The system extracts the clock.

[Configuration space]
PCI Express has a configuration space like conventional PCI, but its size is expanded to 4096 bytes as shown in FIG. 10, whereas conventional PCI has 256 bytes. As a result, sufficient space is secured in the future even for devices (such as host bridges) that require a large number of device-specific register sets. In PCI Express, the configuration space is accessed by accessing a flat memory space (configuration read / write), and the bus / device / function / register number is mapped to a memory address.

  The first 256 bytes of the space can be accessed as a PCI configuration space by a method using an I / O port from a BIOS or a conventional OS. The function of converting the conventional access to the access by PCI Express is implemented on the host bridge. From 00h to 3Fh, it is a PCI2.3 compatible configuration header. As a result, a conventional OS and software can be used as they are except for functions extended by PCI Express. That is, the software layer in PCI Express inherits a load / store architecture (a method in which a processor directly accesses an I / O register) that is compatible with the existing PCI. However, in order to use functions extended by PCI Express (for example, functions such as synchronous transfer and RAS (Reliability, Availability and Serviceability)), it is necessary to make it possible to access a 4 Kbyte PCI Express expansion space.

  Various form factors (shapes) are conceivable as PCI Express. Examples of specific examples include add-in cards, plug-in cards (Express Cards), and Mini PCI Express.

[PCI Express architecture details]
The transaction layer 153, data link layer 154, and physical layer 155, which are the core of the PCI Express architecture, will be described in detail.

A. Transaction layer 153
The main role of the transaction layer 153 is to assemble and disassemble transaction layer packets (TLP) between the upper software layer 151 and the lower data link layer 154 as described above.

a. Address space and transaction type
In PCI Express, memory space (for data transfer with memory space), I / O space (for data transfer with I / O space), and configuration space (device configuration and setup) supported by conventional PCI In addition to message space (in-band event notification between PCI Express devices and general message transmission (exchange) ... Interrupt requests and confirmations are communicated by using the message as a "virtual wire" And four address spaces are defined. Transaction types are defined for each space (memory space, I / O space, configuration space is read / write, and message space is basic (including vendor definition)).

b. Transaction layer packet (TLP)
PCI Express performs communication in units of packets. In the transaction layer packet (TLP) format shown in FIG. 9, the header length of the header is 3DW (DW is an abbreviation of double word; total 12 bytes) or 4DW (16 bytes), and the transaction layer packet (TLP) format ( Information such as header length and presence / absence of payload), transaction type, traffic class (TC), attribute, and payload length are included. The maximum payload length in the packet is 1024 DW (4096 bytes).

  ECRC is an end-to-end data integrity guarantee and is a 32-bit CRC of the transaction layer packet (TLP) portion. This is because when an error occurs in the transaction layer packet (TLP) inside the switch or the like, the LCRC (link CRC) cannot detect the error (because the LCRC is recalculated with the TLP in error).

  Some requests do not require a completion packet, and some requests.

c. Traffic class (TC) and virtual channel (VC)
Upper software can differentiate (prioritize) traffic by using a traffic class (TC). For example, video data can be transferred with priority over network data. There are eight traffic classes (TC) from TC0 to TC7.

  A virtual channel (VC) is an independent virtual communication bus (a mechanism that uses a plurality of independent data flow buffers sharing the same link), each having resources (buffers and queues) As shown in FIG. 11, independent flow control is performed. Thereby, even if the buffer of one virtual channel becomes full (full), the transfer of another virtual channel can be performed. In other words, it can be used effectively by physically dividing one link into a plurality of virtual channels. For example, as shown in FIG. 11, when a route link is divided into a plurality of devices via a switch, the priority of traffic of each device can be controlled. VC0 is indispensable, and other virtual channels (VC1 to VC7) are mounted in accordance with the cost performance trade-off. The solid line arrow in FIG. 11 indicates the default virtual channel (VC0), and the broken line arrow indicates the other virtual channels (VC1 to VC7).

  Within the transaction layer, a traffic class (TC) is mapped to a virtual channel (VC). One or more traffic classes (TC) can be mapped to one virtual channel (VC) (when the number of virtual channels (VC) is small). In a simple example, it can be considered that each traffic class (TC) is mapped to each virtual channel (VC) on a one-to-one basis, and all traffic classes (TC) are mapped to the virtual channel VC0. The mapping of TC0-VC0 is essential / fixed, and the other mappings are controlled from the upper software. The software can control the priority of the transaction by using the traffic class (TC).

d. Flow control Flow control (FC) is performed in order to avoid overflow of the reception buffer and establish the transmission order. Flow control is done point-to-point between links, not end-to-end. Therefore, it cannot be confirmed that the packet has reached the final partner (completer) by flow control.

  PCI Express flow control is performed on a credit basis (mechanism to check the buffer availability on the receiving side before starting data transfer and prevent overflow and underflow). That is, the receiving side notifies the transmitting side of the buffer capacity (credit value) at the time of link initialization, and the transmitting side compares the credit value with the length of the packet to be transmitted, and transmits the packet only when there is a certain remaining. There are six types of credits.

  Flow control information exchange is performed using data link layer packets (DLLP) in the data link layer. The flow control is applied only to the transaction layer packet (TLP) and not to the data link layer packet (DLLP) (DLLP can always be transmitted / received).

B. Data link layer 154
The main role of the data link layer 154 is to provide a reliable transaction layer packet (TLP) exchange function between two components on the link, as described above.

a. Handling of transaction layer packet (TLP) For the transaction layer packet (TLP) received from the transaction layer 153, a 2-byte sequence number at the beginning and a 4-byte link CRC (LCRC) at the end are added to the physical layer. To 155 (see FIG. 9). The transaction layer packet (TLP) is stored in the retry buffer and retransmitted until a reception confirmation (ACK) is received from the partner. When the transmission of the transaction layer packet (TLP) continues to fail, it is determined that the link is abnormal, and the physical layer 155 is requested to retrain the link. If link training fails, the state of the data link layer 154 transitions to inactive.

  The transaction layer packet (TLP) received from the physical layer 155 is inspected for the sequence number and the link CRC (LCRC). If normal, the transaction layer packet (TLP) is passed to the transaction layer 153. If there is an error, a retransmission is requested.

b. Data link layer packet (DLLP)
The transaction layer packet (TLP) is automatically divided into data link layer packets (DLLP) as shown in FIG. 12 and transmitted to each lane when transmitted from the physical layer. A packet generated by the data link layer 154 is called a data link layer packet (DLLP), and is exchanged between the data link layers 154. Data link layer packet (DLLP)
-Ack / Nak: TLP reception confirmation, retry (retransmission)
-InitFC1 / InitFC2 / UpdateFC: Flow control initialization and update-DLLLP for power management
There are different types.

  As shown in FIG. 12, the length of the data link layer packet (DLLP) is 6 bytes. From the DLLP type (1 byte) indicating the type, the information specific to the type of DLLP (3 bytes), and CRC (2 bytes) Composed.

C. Physical layer-logical sub-block 156
The main role of the physical layer 155 in the logical sub-block 156 shown in FIG. 8 is to convert the packet received from the data link layer 154 into a format that can be transmitted by the electrical sub-block 157. It also has a function of controlling / managing the physical layer 155.

a. Data encoding and parallel-serial conversion
PCI Express uses 8B / 10B conversion for data encoding so that consecutive “0” s and “1” s do not continue (in order not to maintain a state where there is no cross point for a long period of time). The converted data is serial-converted and transmitted from the LSB onto the lane as shown in FIG. Here, when there are a plurality of lanes (FIG. 13 illustrates the case of x4 link), data is allocated to each lane in units of bytes before encoding. In this case, it looks like a parallel bus at first glance, but since the transfer is performed independently for each lane, the skew which is a problem with the parallel bus is greatly reduced.

b. Power Management and Link State In order to keep the power consumption of the link low, a link state of L0 / L0s / L1 / L2 is defined as shown in FIG.

  L0 is a normal mode, and power consumption is reduced from L0s to L2, but it takes time to return to L0. As shown in FIG. 15, by actively performing active state power management in addition to software power management, it is possible to reduce power consumption as much as possible.

D. Physical layer—Electric sub-block 157
The main role of the physical layer 155 in the electrical sub-block 157 is to transmit the data serialized in the logical sub-block 156 onto the lane, and to receive the data on the lane and pass it to the logical sub-block 156. is there.

a. AC coupling On the transmission side of the link, a capacitor for AC coupling is mounted. This eliminates the need for the DC common mode voltage on the transmission side and the reception side to be the same. For this reason, it is possible to use different designs, semiconductor processes, and power supply voltages on the transmission side and the reception side.

b. De-emphasis
In PCI Express, as described above, processing is performed so that continuous “0” and “1” do not continue as much as possible by 8B / 10B encoding, but continuous “0” and “1” may continue (maximum). 5 times). In this case, it is specified that the transmission side must perform de-emphasis transfer. When bits of the same polarity are consecutive, it is necessary to increase the noise margin of the signal received on the receiving side by dropping the differential voltage level (amplitude) from the second bit by 3.5 ± 0.5 dB. . This is called de-emphasis. Due to the frequency-dependent attenuation of the transmission line, there are many high-frequency components in the case of changing bits, and the waveform on the receiving side becomes small due to attenuation. Becomes larger. For this reason, de-emphasis is performed in order to make the waveform on the receiving side constant.

[Information processing system]
An information processing system such as a digital copying machine or MFP according to the present embodiment uses a PCI Express standard high-speed serial bus as described above for its internal interface.

  FIG. 16 is a schematic block diagram illustrating a configuration example of the information processing system according to the present embodiment. The information processing system 1 according to the present embodiment is applied to a device such as an MFP, and includes, as its components, a controller 2, an input unit 3 that is an image input unit, and an output unit 4 that is an image output unit. And a data storage unit 5.

  The controller 2 includes a CPU that controls the entire system according to an installed program (software), and means a device portion (printer controller) that performs processing such as path control and path determination. Further, the controller 2 performs processing such as image processing such as enlargement / reduction and rotation, compression / decompression, data conversion processing (expansion / enlargement / reduction of printer language), memory management, and the like on the image data.

  The input unit 3 is a device or unit for capturing image data based on a document image or the like into the system, and is configured by, for example, a scanner engine that photoelectrically reads a document image and acquires image data. Yes.

  The output unit 4 is a device or unit that prints out image data on paper or the like, and includes, for example, an electrophotographic plotter (printer) engine. In addition to the electrophotographic method, various methods such as an ink jet method, a sublimation type thermal transfer method, a silver salt photography method, a direct thermal recording method, and a melt type thermal transfer method can be used as the printing method of the output unit 4.

  The data storage unit 5 is a device or unit including a memory, HDD, or the like that stores image data.

  In such a configuration, under the control of the controller 2, the image data captured from the input unit 3 is subjected to image processing by the controller 2 as necessary, and then transferred to the data storage unit 5, where it is temporarily stored in the data storage unit 5. Saved. Thereafter, the image data stored in the data storage unit 5 is taken into the controller 2 and subjected to image processing as necessary, and then transferred to the output unit 4 for printout and the like.

  In addition, the controller 2 includes a root complex 6 of the PCI Express standard that connects the switch 7 by a high-speed serial bus 8 based on the PCI Express standard. Below the switch 7, a plurality of printers 9, which are image forming apparatuses that form an image on a medium such as paper based on image data, are used as high-speed serials according to the PCI Express standard as end points of the PCI Express standard. The buses 10 are connected to each other. Note that the printers 9 have the same performance. Here, the number of lanes of the link of the high-speed serial bus 8 is “x1”, and the number of lanes of the link of the high-speed serial bus 10 is “x1”.

  Here, a characteristic function provided in the information processing system 1 of the present embodiment will be described. In the information processing system 1 according to the present embodiment, when a plurality of copies of image data read from the input unit 3 are printed, a plurality of copies of the image data are sent to the plurality of printers 9 positioned below the switch 7 at the same timing. Send with. In this case, the route complex 6 transmits a data packet by a PCI Express standard message packet to the downstream side using a PCI Express standard broadcast mode. This will be described in detail below with a partial excerpt from “PCI Express Base Specification Revision 1.0a” (http://www.pcisig.com/).

  PCI Express standard TLP (Transaction Layer Packet) types are broadly classified into Memory Read / Write, IO Read / Write, Config Read / Write, Message, Completion, and the like. As shown in FIG. 17, the TLP format is composed of three sections: TLP Header, Data Payload, and TLP Digest. There may be no Data Payload depending on the type of TLP. In addition, TLP Digest is an option and not always.

  Further, the TLP Header is configured as shown in FIG. 18, and the type is determined according to the table shown in FIG. 19 by the combination of Fmt and Type.

  For normal data transfer, TLPs of Memory Read Request (MRd), Completion with Data (CplD), and Memory Write Request (MWr) shown in FIG. 19 are used.

  Here, the message packet will be described. As shown in FIG. 19, there are two types of message packets: Msg that does not include Data Payload and MsgD that includes Data Payload. In Msg and MsgD, according to the table shown in FIG. 20, the routing method of the message packet can be determined in the r [2: 0] portion. As shown in FIG. 20, by setting r [2: 0] to 011 in the message packet, it is possible to transmit a broadcast packet from the root complex (RootComplex) to all endpoints (Endpoint). is there. FIG. 21 is an explanatory diagram showing the data structure of the message request header. r [2: 0] is specified in the lower 3 bits of the Type field in FIG. Such a message packet is basically used for transmitting a specific message such as interrupt notification, power management, error notification, lock transaction, slot power limit, hot plug, and the like. However, in the PCI Express standard, Vendor # Defined Messages is also defined, and can be used to send data other than the purpose determined in advance by the standard. In order to use Vendor # Degined Message, the MessageCode field may be specified as one of Type 0 and Type 1 shown in FIG. When a packet is transmitted by broadcast, 011 is specified in the Routing r [2: 0] portion shown in FIG.

  When sending Data Payload by such a message packet, set Fmt field to 11. When Datapayload is included, the Datapayload size is specified in the Length field of TLP.

As mentioned above, in order to send vendor-defined data by Broadcast transmission by Message TLP, the structure of TLP header is
Fmt: 11 (MsgD)
Type: 10011 (broadcast)
Code: 0111 1110 or 0111 1111 (Vendor-Defined)
Length: Data Payload size, and by generating a message packet that includes data to be sent to Data Payload, it is possible to send data addressed to all Endpoints from the Rootcomplex.

  In such a packet in which broadcast is designated, data sent from the upstream port in the switch is copied and transmitted to all downstream ports.

  As described above, according to the present embodiment, the controller 2 generates a message packet including image data, and transmits the message packet from the root complex 6 to all the printers 9 via the switch 7 using the broadcast mode. Thus, the same image data in all the printers 9 can be simultaneously printed, that is, multiple copies can be simultaneously printed, so that the printing time can be shortened and the processing speed when a large number of copies are output is high. Can be achieved. Of course, the use of a high-speed printer as the printer 9 can further increase the speed. Even when a low-speed printer is used as the printer 9, the same image data in all low-speed printers can be simultaneously printed, that is, multiple copies can be simultaneously printed, so that even a low-speed printer can perform high-speed printing. Can be achieved.

  In the case of broadcast transmission using message packets, the number of links in the high-speed serial buses 8 and 10 according to the PCI Express standard may be “x1”. The number of lanes becomes unnecessary, and the number of link lanes can be reduced.

  As shown in FIG. 23, the system is expanded by providing the root complex 11 in multiple stages with respect to the configuration shown in FIG. 16 and connecting the switch 12 with the high-speed serial bus 13 according to the PCI Express standard. Can do.

  As described above, according to the present embodiment, when printing a plurality of copies of image data, the root complex 6 has at least two or more printers 9 positioned below the switch 7 at the same timing via the switch 7. By transmitting a plurality of copies of image data, the same image data in all the printers 9 can be simultaneously printed, that is, multiple copies can be simultaneously printed, so that the printing time can be shortened and a large number of copies can be obtained. Can be speeded up.

  In addition, since the number of link lanes of the high-speed serial buses 8 and 10 according to the PCI Express standard may be “x1” by broadcast transmission using message packets, link lanes corresponding to the number of printers 9 are provided on the upstream link. The number is unnecessary, and the number of link lanes can be reduced.

[Second Embodiment]
Next, a second embodiment of the present invention will be described with reference to FIG. The same parts as those in the first embodiment described above are denoted by the same reference numerals, and description thereof is also omitted.

  In the first embodiment, message packets including image data are broadcasted to a plurality of printers 9 so that multiple copies are simultaneously printed. In the present embodiment, addresses are assigned. The data is output to a downstream printer.

  FIG. 24 is a schematic block diagram illustrating a configuration example of the information processing system according to the present embodiment. The information processing system 1 according to the present embodiment is structurally different from the first embodiment in that the number of lanes of the link of the high-speed serial bus 8 is “x4”. That is, in the present embodiment, the number of lanes on the upstream side of the switch 7 is required by the number of lanes on the downstream side of the switch 7 (that is, the number of lanes on the link corresponding to the number of printers 9). ing.

  That is, in the present embodiment, the image data is distributed to the address of each printer 9 by the root complex 6.

  Thus, according to this embodiment, the number of lanes on the upstream side of the switch 7 is required by the number of lanes on the downstream side of the switch 7 (that is, the number of link lanes corresponding to the number of printers 9). However, it is possible to speed up the processing when outputting a large number of copies.

It is a block diagram which shows the structural example of the existing PCI system. FIG. 2 is a block diagram illustrating a configuration example of a PCI Express system. It is a block diagram which shows the structural example of the PCI Express platform in desktop / mobile. It is a schematic diagram which shows the structural example of the physical layer in the case of x4. It is a schematic diagram which shows the example of lane connection between devices. It is a block diagram which shows the logical structural example of a switch. It is a block diagram which shows the architecture of the existing PCI. It is a block diagram which shows the architecture of PCI Express. It is a block diagram which shows the hierarchical structure of PCI Express. It is explanatory drawing which shows the format example of a transaction layer packet. It is explanatory drawing which shows the configuration space of PCI Express. It is a schematic diagram for demonstrating the concept of a virtual channel. It is explanatory drawing which shows the format example of a data link layer packet. It is a schematic diagram which shows the byte striping example in x4 link. It is explanatory drawing explaining the definition of the link state of L0 / L0s / L1 / L2. It is a time chart which shows the example of control of active state power management. It is a schematic block diagram which shows the structural example of the information processing system of the 1st Embodiment of this invention. It is explanatory drawing which shows the data format of TLP of a PCI Express standard. It is explanatory drawing which shows TLP Header. It is a table which shows the kind of TLP. It is a table which shows the routing system of a message packet. It is explanatory drawing which shows the data structure of a message request header. It is explanatory drawing which shows the field of MessageCode. It is a schematic block diagram which shows the modification of a structure of an information processing system. It is a schematic block diagram which shows the structural example of the information processing system of the 2nd Embodiment of this invention.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 Information processing system 6,11 Route complex 7,12 Switch 8,10,13 High-speed serial bus 9 Image forming apparatus

Claims (14)

At least two or more image forming apparatuses capable of forming an image on a medium such as paper based on image data;
A switch connecting these image forming apparatuses via a high-speed serial bus, and
A high-order serial bus connected to the switch located above the switch, and a route complex for transmitting the image data to the switch,
An information processing system comprising: A route complex is provided in multiple stages, and switches are connected by a high-speed serial bus.
The information processing system according to claim 1. The high-speed serial bus is a PCI Express standard high-speed serial bus.
The information processing system according to claim 1 or 2. The root complex generates a data packet using a PCI Express standard message packet including the image data when the image data is formed by at least two of the image forming apparatuses, and the data packet is converted into a PCI Express standard. To the switch using the broadcast mode of
When the broadcast transmission is designated for the data packet sent from the upstream port, the switch copies the image data of the data packet and sends it to all downstream ports.
The information processing system according to claim 3. When the root complex broadcasts a data packet using a PCI Express standard message packet including the image data, the configuration of the TLP (Transaction Layer Packet) header of the PCI Express standard,
Fmt: 11 (MsgD)
Type: 10011 (broadcast)
Code: 0111 1110 or 0111 1111 (Vendor-Defined)
Length: Data Payload size and generate the message packet including the image data to be sent to Data Payload.
The information processing system according to claim 4. The root complex distributes the image data read from the input unit to addresses of the image forming apparatuses when the image data is formed by at least two or more image forming apparatuses.
The information processing system according to claim 3. A high-speed printer is used as each of the image forming apparatuses.
The information processing system according to claim 1, wherein the information processing system is an information processing system. A low-speed printer is used as each image forming apparatus.
The information processing system according to claim 1, wherein the information processing system is an information processing system. Connected to a switch that connects at least two or more image forming devices that can form images on a medium such as paper based on image data using a PCI Express high-speed serial bus, using a PCI Express high-speed serial bus. A program for operating a computer provided in a controller,
When forming the image data with at least two or more image forming apparatuses, a data packet using a PCI Express standard message packet including the image data is generated, and the data packet is used in a PCI Express standard broadcast mode. Send to the switch,
A program characterized by that. When a data packet using a PCI Express standard message packet including the image data is broadcast, the configuration of a TLP (Transaction Layer Packet) header of the PCI Express standard,
Fmt: 11 (MsgD)
Type: 10011 (broadcast)
Code: 0111 1110 or 0111 1111 (Vendor-Defined)
Length: Data Payload size and generate the message packet including the image data to be sent to Data Payload.
The program according to claim 9. Connected to a switch that connects at least two or more image forming devices that can form images on a medium such as paper based on image data using a PCI Express high-speed serial bus, using a PCI Express high-speed serial bus. A program for operating a computer provided in a controller,
When the image data is formed by at least two or more of the image forming apparatuses, the image data is distributed to addresses of the image forming apparatuses;
A program characterized by that. Connected to a switch that connects at least two or more image forming devices that can form images on a medium such as paper based on image data using a PCI Express standard high-speed serial bus, using a PCI Express standard high-speed serial bus. A data transfer method in a controller,
When the image data is formed by at least two or more image forming apparatuses, a data packet using a PCI Express standard message packet including the image data is generated, and the data packet is used in a PCI Express standard broadcast mode. Send to the switch,
A data transfer method characterized by the above. When broadcasting a data packet using a PCI Express standard message packet including the image data, the configuration of the TLP (Transaction Layer Packet) header of the PCI Express standard,
Fmt: 11 (MsgD)
Type: 10011 (broadcast)
Code: 0111 1110 or 0111 1111 (Vendor-Defined)
Length: Data Payload size and generate the message packet including the image data to be sent to Data Payload.
13. A data transfer method according to claim 12, wherein: Connected to a switch that connects at least two or more image forming devices that can form images on a medium such as paper based on image data using a PCI Express standard high-speed serial bus, using a PCI Express standard high-speed serial bus. A data transfer method in a controller,
When the image data is formed by at least two or more of the image forming apparatuses, the image data is distributed to addresses of the image forming apparatuses;
A data transfer method characterized by the above.

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