JP2007282187A - Information processor, information processing system, and data communication method - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide an information processor and a data communication method for freely extending a device having different traffic with various features with respect to a high-speed serial switch fabric. <P>SOLUTION: In an information processor 1 where a plurality of devices 3 to 10 are connected through a high-speed serial switch fabric 2 configured to perform a mapping of a traffic class that is capable of differentiating traffics onto a virtual channel, the traffic class is set for each of traffics in the devices 3 to 10 having the conflict, and each of set traffic classes is assigned to different virtual channels, and a priority of data communication is given to each of the set traffic classes. Thus, it is possible to freely extend the devices 3 to 10 having different traffics with various features with respect to a high-speed serial switch fabric 2. <P>COPYRIGHT: (C)2008,JPO&INPIT

Description

  The present invention relates to an information processing apparatus, an information processing system, and a data communication method in which a plurality of devices are connected via a high-speed serial switch fabric capable of mapping a traffic class capable of differentiating traffic to a virtual channel.

  In general, in an information processing apparatus such as a digital copying machine or a multifunction peripheral (MFP) that handles image data and other data, a PCI bus is used as an interface between devices.

  However, the parallel PCI bus has problems such as racing and skew, and the transfer rate has been low for use in high-speed and high-quality image forming apparatuses. The use of a high-speed serial interface such as IEEE1394 or USB is being considered in place of the parallel interface. For example, according to Patent Document 1, it is proposed to use a high-speed serial interface such as IEEE1394 or USB as an internal interface.

  As another high-speed serial interface, an interface called PCI Express (registered trademark), which is a successor to the PCI bus system, has been proposed and has been put to practical use (for example, see Non-Patent Document 1). This PCI Express system is schematically configured as a data communication network having a tree structure (tree structure) such as a root complex-switch (arbitrary hierarchy) -device as shown in FIG. Has been.

  In recent years, the Advanced Switching Interconnect standard, which is a high-speed serial switch fabric based on the PCI Express architecture, has been formulated. This Advanced Switching Interconnect is designed to support a wider range of applications while directly adopting the physical layer and link layer technologies of PCI Express high-speed serial transmission, and its connection target is Chip-to-Chip, Assume Board-to-Board. According to this Advanced Switching Interconnect, traffic can be differentiated (prioritized) by mapping a traffic class to a virtual channel.

JP 2001-016382 A “Outline of PCI Express Standard” Interface, July’2003 Naoshi Satomi

  However, even when a PCI Express interface is used as an interface between devices, there is a problem that must be solved. In general, traffic control is insufficient, multi-host is not possible, scalability is limited, and the like.

  The present invention has been made in view of the above, and is an information processing apparatus that uses a high-speed serial switch fabric and can freely expand devices having various different traffic characteristics to the high-speed serial switch fabric. It is another object of the present invention to provide a data communication method.

  The present invention has been made in view of the above, and provides an information processing system that can cope with high-speed data transfer when a memory read command and a memory write command compete in a high-speed serial switch fabric. The purpose is to provide.

  In order to solve the above-described problems and achieve the object, the invention according to claim 1 is directed to a plurality of traffic classes capable of differentiating traffic via a high-speed serial switch fabric capable of mapping to a virtual channel. In the information processing apparatus to which the devices are connected, a traffic class setting unit that sets the traffic class for each traffic in the device in which contention occurs, and the traffic classes set by the traffic class setting unit are different from each other. Channel setting means for assigning priority to data communication by assigning to each virtual channel.

  According to a second aspect of the present invention, in the information processing apparatus according to the first aspect, the high-speed serial switch fabric is a switch fabric of an Advanced Switching Interconnect standard.

  According to a third aspect of the present invention, in the information processing apparatus according to the first or second aspect, the priority of the traffic class of traffic having isochronous restrictions in line synchronization signal units is set by the setting of the virtual channel. The priority is higher than the priority of the traffic class of the traffic having isochronous restrictions on a page basis.

  According to a fourth aspect of the present invention, in the information processing apparatus according to the first or second aspect, the priority of the traffic class of the memory read transaction is set to the priority of the traffic class of the memory write transaction by setting the virtual channel. Higher than the degree.

  The invention according to claim 5 outputs an image input device that reads image data, a storage device that stores image data read by the image input device, and the image data stored in the storage device. In an information processing system in which a plurality of information processing apparatuses each having an image output device are connected via a high-speed serial switch fabric, each piece of information is obtained by multicast output of image data read by the image input device of the one information processing apparatus When data is transferred to the storage device of the processing device and the image data stored in each storage device is output from the image output device of each information processing device, data communication in the virtual channel of the high-speed serial switch fabric Priority, memory read command> And Mori write command.

  The invention according to claim 6 outputs an image input device that reads image data, a storage device that stores image data read by the image input device, and the image data stored in the storage device. In an information processing system in which a plurality of information processing apparatuses including an image output device are connected via a high-speed serial switch fabric, image data read by the image input device of one information processing apparatus is transferred to the storage device When the image output device of each information processing apparatus issues a memory read command to output the image data stored in the storage device to the storage device in which the image data is stored, Data communication in virtual channel of serial switch fabric The priority, and the memory read command> memory write command.

  The invention according to claim 7 outputs an image input device that reads image data, a storage device that stores image data read by the image input device, and the image data stored in the storage device. In an information processing system in which a plurality of information processing apparatuses including an image output device are connected via a high-speed serial switch fabric, image data read by the image input device of one information processing apparatus is transferred to the storage device When the image data stored in the storage device is output from the image output device of each information processing apparatus by generating a memory write transfer by multicast output, the data communication in the virtual channel of the high-speed serial switch fabric is performed. Prioritize the memory read frame De> and memory write command.

  The invention according to claim 8 is a data communication method in an information processing apparatus in which a plurality of devices are connected via a high-speed serial switch fabric capable of mapping a traffic class capable of performing traffic differentiation to a virtual channel. A traffic class setting step for setting the traffic class for each traffic in the device in which contention occurs, and assigning the traffic classes set by the traffic class setting step to different virtual channels. And a channel setting step for giving priority of data communication.

  The invention according to claim 9 is the data communication method according to claim 8, wherein the high-speed serial switch fabric is a switch fabric of an Advanced Switching Interconnect standard.

  Further, the invention according to claim 10 is the data communication method according to claim 8 or 9, wherein the priority of the traffic class of traffic having isochronous restrictions in line synchronization signal units is set by the setting of the virtual channel. The priority is higher than the priority of the traffic class of the traffic having isochronous restrictions on a page basis.

  The invention according to claim 11 is the data communication method according to claim 8 or 9, wherein the priority of the traffic class of the memory read transaction is set to the priority of the traffic class of the memory write transaction by setting the virtual channel. Higher than the degree.

  According to the first aspect of the present invention, a traffic class is set for each traffic in a device in which contention occurs, and each of the set traffic classes is assigned to a different virtual channel to give priority to data communication. It is possible to freely expand devices having different traffic characteristics to the high-speed serial switch fabric.

  According to the second aspect of the invention, the high-speed serial switch fabric is an advanced switching interconnect standard switch fabric, so that the communication speed between devices can be increased. Also, by tunneling various higher level protocols, it is possible to construct a local system that realizes communication such as TCP / IP at a higher speed than normal Ethernet (registered trademark) processing. In addition, the system can be made redundant by adapting the fabric structure, etc. to improve the robustness, and dynamic routing paths can be switched.

  According to the invention of claim 3, by setting the virtual channel, the priority of the traffic class of traffic having isochronous restrictions in units of line synchronization signals is set, and the traffic of traffic having isochronous restrictions in units of pages. By making the priority higher than the class priority, the priority of traffic that has isochronous restrictions in units of line synchronization signals from devices such as scanners and plotters should be made higher than the traffic that has isochronous restrictions in units of pages. Therefore, it is possible to ensure isochronism of a scanner, a plotter, etc. when mixed.

  According to the invention of claim 4, the data read by the scanner is set by setting the priority of the traffic class of the memory read transaction higher than the priority of the traffic class of the memory write transaction by setting the virtual channel. When the image data is transferred to the image memory and the image data stored in the image memory is output from the plotter, the image data memory write command is issued after all the image data memory read commands are issued. As a result, it is possible to cope with high-speed data transfer.

  According to the invention of claim 5, priority is given to data communication in the virtual channel of the high-speed serial switch fabric when the memory read command and the memory write command conflict in the high-speed serial switch fabric of each information processing apparatus. When the memory read command is greater than the memory write command, it is possible to cope with high-speed data transfer.

  According to the invention of claim 6, priority is given to data communication in the virtual channel of the high-speed serial switch fabric when the memory read command and the memory write command compete in the high-speed serial switch fabric of each information processing apparatus. When the memory read command is greater than the memory write command, it is possible to cope with high-speed data transfer.

  According to the seventh aspect of the present invention, priority is given to data communication in the virtual channel of the high-speed serial switch fabric when the memory read command and the memory write command conflict in the high-speed serial switch fabric of each information processing apparatus. When the memory read command is greater than the memory write command, it is possible to cope with high-speed data transfer.

  According to the invention of claim 8, by setting a traffic class for each traffic in a device in which contention occurs, assigning each set traffic class to a different virtual channel to give priority to data communication. This has the effect that devices having different traffic of various properties can be freely extended to the high-speed serial switch fabric.

  According to the invention of claim 9, since the high-speed serial switch fabric is an Advanced Switching Interconnect standard switch fabric, the communication speed between devices can be increased. Also, by tunneling various higher level protocols, it is possible to construct a local system that realizes communication such as TCP / IP at a higher speed than normal Ethernet (registered trademark) processing. In addition, the system can be made redundant by adapting the fabric structure, etc. to improve the robustness, and dynamic routing paths can be switched.

  Further, according to the invention of claim 10, by setting the virtual channel, the priority of the traffic class of traffic having isochronous restrictions in units of line synchronization signals is set, and the traffic of traffic having isochronous restrictions in units of pages. By making the priority higher than the class priority, the priority of traffic that has isochronous restrictions in units of line synchronization signals from devices such as scanners and plotters should be made higher than the traffic that has isochronous restrictions in units of pages. Therefore, it is possible to ensure isochronism of a scanner, a plotter, etc. when mixed.

  According to the invention of claim 11, the data read by the scanner is set by making the priority of the traffic class of the memory read transaction higher than the priority of the traffic class of the memory write transaction by setting the virtual channel. When the image data is transferred to the image memory and the image data stored in the image memory is output from the plotter, the image data memory write command is issued after all the image data memory read commands are issued. As a result, it is possible to cope with high-speed data transfer.

  Exemplary embodiments of an information processing apparatus and a data communication method according to the present invention are explained in detail below with reference to the accompanying drawings.

  The best mode for carrying out the present invention will be described with reference to the drawings. In the following, details of PCI Express are explained in the [Outline of PCI Express Standard] to [Detailed Architecture of PCI Express] columns, and Advanced Switch Interconnect using PCI Express technology [What is Advanced Switch Interconnect] The description will be given in the section of [Features of Advanced Switch Interconnect technology], and the information processing apparatus of the present embodiment will be described in the sections of [Configuration of information processing apparatus] to [Operation example].

[Outline of PCI Express standard]
First, this embodiment uses PCI Express (registered trademark), which is one of high-speed serial buses. As an assumption of this embodiment, an outline of the PCI Express standard is a part of Non-Patent Document 1. Explained with excerpts. Here, the high-speed serial bus means an interface capable of exchanging data at high speed (about 100 Mbps or more) by serial (serial) transmission using a single transmission line.

  PCI Express is a standardized expansion bus that can be used for all computers as a successor to PCI. In general, low-voltage differential signal transmission, point-to-point independent communication channels, and packetization Split transactions and high scalability due to differences in link configuration.

  FIG. 1 shows a configuration example of an existing PCI system, and FIG. 2 shows a configuration example of a PCI Express system. In an existing PCI system, PCI-X (PCI upward compatible standard) devices 104a and 104b connect a PCI-X bridge 105a to a host bridge 103 to which a CPU 100, AGP graphics 101, and memory 102 are connected. Or a PCI bridge 105b to which the PCI devices 104c and 104d are connected and a PCI bridge 107 to which the PCI bus slot 106 is connected are connected via the PCI bridge 105c (tree structure). Yes.

  On the other hand, in the PCI Express system, the PCI Express graphics 113 is connected by the PCI Express 114a to the root complex 112 to which the CPU 110 and the memory 111 are connected, and the endpoint 115a and the legacy endpoint 116a. PCI Express 114b connects the switch 117a to which the PCI Express 114b is connected, and the PCI bridge 119 to which the switch 117b to which the endpoint 115b and the legacy endpoint 116b are connected by the PCI Express 114d and the PCI bus slot 118 are connected. The switch 117c connected by the Express 114e has a tree structure (tree structure) connected by the PCI Express 114f.

  An example of an actually assumed PCI Express platform is shown in FIG. The illustrated example shows an application example to desktop / mobile. For example, graphics 125 is x16 with respect to a memory hub 124 (corresponding to a root complex) to which a CPU 121 is connected by a CPU host bus 122 and a memory 123 is connected. PCI Express 126a and an I / O hub 127 having a conversion function are connected by PCI Express 126b. For example, a storage 129 is connected to the I / O hub 127 by a Serial ATA 128, a local I / O 131 is connected by an LPC 130, and a USB 2.0 132 and a PCI bus slot 133 are connected. Further, a switch 134 is connected to the I / O hub 127 by a PCI Express 126c, and the mobile dock 135, Gigabit Ethernet 136 (Ethernet is a registered trademark), and an add-in are connected to the switch 134 by PCI Express 126d, 126e, and 126f, respectively. A card 137 is connected.

  That is, in the PCI Express system, the conventional PCI, PCI-X, AGP bus is replaced with PCI Express, and a bridge is used to connect an existing PCI / PCI-X device. Connection between chipsets is also PCI Express connection, and existing buses such as IEEE1394, Serial ATA, and USB 2.0 are connected to PCI Express by an I / O hub.

[Components of PCI Express]
A. Port / Lane / Link
FIG. 4 shows the structure of the physical layer. A port is a set of transmitters / receivers that are physically in the same semiconductor and form a link, and logically means an interface that connects component links in a one-to-one relationship (point-to-point). . The transfer rate is, for example, 2.5 Gbps in one direction. The lane is, for example, a set of 0.8 V differential signal pairs, and includes a transmission-side signal pair (two) and a reception-side signal pair (two). A link is a collection of lanes connecting two ports and the two ports, and is a dual simplex communication bus between components. The “xN link” is composed of N lanes, and N = 1, 2, 4, 8, 16, 32 are defined in the current standard. The illustrated example is an x4 link example. For example, as shown in FIG. 5, by changing the lane width N connecting the devices A and B, a scalable bandwidth can be configured.

B. Root Complex
The root complex 112 is located at the highest level of the I / O structure, and connects the CPU and the memory subsystem to the I / O. In a block diagram or the like, as shown in FIG. 3, it is often described as “memory hub”. The root complex 112 (or 124) has one or more PCI Express ports (root ports) (indicated by squares in the root complex 112 in FIG. 2), and each port is an independent I / O hierarchical domain. Form. The I / O hierarchical domain is a simple endpoint (for example, the example of the endpoint 115a side in FIG. 2), or is formed from a large number of switches and endpoints (for example, the endpoint in FIG. 2). 115b and switches 117b and 115c side).

C. End point
The endpoint 115 is a device having a configuration space header of type 00h (specifically, a device other than a bridge), and is divided into a legacy endpoint and a PCI Express endpoint. The major difference between the two is that the PCI Express endpoint does not request I / O resources in the BAR (Base Address Register), and therefore does not request an I / O request. PCI Express endpoints also do not support lock requests.

D. Switch
The switch 117 (or 134) couples two or more ports and performs packet routing between the ports. From the configuration software, the switch is recognized as a collection of virtual PCI-PCI bridges 141 as shown in FIG. In the figure, double arrows indicate the PCI Express link 114 (or 126), and 142a to 142d indicate ports. Among these, the port 142a is an upstream port closer to the root complex, and the ports 142b to 142d are downstream ports farther from the root complex.

E. PCI Express 114e-PCI bridge 119
Provides connection from PCI Express to PCI / PCI-X. Thereby, an existing PCI / PCI-X device can be used on the PCI Express system.

[Hierarchical architecture]
As shown in FIG. 7A, the conventional PCI architecture has a structure in which protocols and signaling are closely related and there is no concept of hierarchy. In PCI Express, as shown in FIG. Like the standard communication protocol and InfiniBand, it has an independent hierarchical structure, and specifications are defined for each layer. In other words, a transaction layer 153, a data link layer 154, and a physical layer 155 are provided between the uppermost software 151 and the lowermost mechanism (mechanical) unit 152. Thereby, the modularity of each layer is ensured, and it becomes possible to provide scalability and reuse the module. For example, when adopting a new signal coding method or transmission medium, it is possible to cope with only changing the physical layer without changing the data link layer or the transaction layer.

  The core of the PCI Express architecture is a transaction layer 153, a data link layer 154, and a physical layer 155, each having the following roles described with reference to FIG.

A. Transaction layer 153
The transaction layer 153 is located at the highest level and has a function of assembling and disassembling a transaction layer packet (TLP). The transaction layer packet (TLP) is used for transmission of transactions such as read / write and various events. The transaction layer 153 performs flow control using credits for transaction layer packets (TLP). An outline of a transaction layer packet (TLP) in each of the layers 153 to 155 is shown in FIG. 9 (details will be described later).

B. Data link layer 154
The main role of the data link layer 154 is to guarantee data integrity of the transaction layer packet (TLP) by error detection / correction (retransmission) and link management. Packets for link management and flow control are exchanged between the data link layers 154. This packet is called a data link layer packet (DLLP) to distinguish it from a transaction layer packet (TLP).

C. Physical layer 155
The physical layer 155 includes circuits necessary for interface operations such as a driver, an input buffer, a parallel-serial / serial-parallel converter, a PLL, and an impedance matching circuit. It also has interface initialization / maintenance functions as logical functions. The physical layer 155 also serves to make the data link layer 154 / transaction layer 153 independent of the signaling technology used in the actual link.

  The PCI Express hardware configuration employs a technology called embedded clock, there is no clock signal, the clock timing is embedded in the data signal, and the receiving side is based on the cross-point of the data signal. The system extracts the clock.

[Configuration space]
PCI Express has a configuration space like conventional PCI, but its size is expanded to 4096 bytes as shown in FIG. 10, whereas conventional PCI has 256 bytes. As a result, sufficient space is secured in the future even for devices (such as host bridges) that require a large number of device-specific register sets. In PCI Express, the configuration space is accessed by accessing a flat memory space (configuration read / write), and the bus / device / function / register number is mapped to a memory address.

  The first 256 bytes of the space can be accessed as a PCI configuration space by a method using an I / O port from a BIOS or a conventional OS. The function of converting the conventional access to the access by PCI Express is implemented on the host bridge. From 00h to 3Fh, it is a PCI2.3 compatible configuration header. As a result, a conventional OS and software can be used as they are except for functions extended by PCI Express. That is, the software layer in PCI Express inherits a load / store architecture (a method in which a processor directly accesses an I / O register) that is compatible with the existing PCI. However, in order to use functions extended by PCI Express (for example, functions such as synchronous transfer and RAS (Reliability, Availability and Serviceability)), it is necessary to make it possible to access a 4 Kbyte PCI Express expansion space.

  Although various form factors (shapes) can be considered as PCI Express, examples of specific examples include an add-in card, a plug-in card (Express Card), and Mini PCI Express.

[PCI Express architecture details]
The transaction layer 153, data link layer 154, and physical layer 155, which are the core of the PCI Express architecture, will be described in detail.

A. Transaction layer 153
The main role of the transaction layer 153 is to assemble and disassemble transaction layer packets (TLP) between the upper software layer 151 and the lower data link layer 154 as described above.

a. Address space and transaction type
In PCI Express, memory space (for data transfer with memory space), I / O space (for data transfer with I / O space), and configuration space (device configuration and setup) supported by conventional PCI In addition to message space (in-band event notification between PCI Express devices and general message transmission (exchange) ... Interrupt requests and confirmations are communicated by using the message as a "virtual wire" And four address spaces are defined. Transaction types are defined for each space (memory space, I / O space, configuration space is read / write, and message space is basic (including vendor definition)).

b. Transaction layer packet (TLP)
PCI Express performs communication in units of packets. In the transaction layer packet (TLP) format shown in FIG. 9, the header length of the header is 3DW (DW is an abbreviation of double word; total 12 bytes) or 4DW (16 bytes), and the transaction layer packet (TLP) format ( Information such as header length and presence / absence of payload), transaction type, traffic class (TC), attribute, and payload length are included. The maximum payload length in the packet is 1024 DW (4096 bytes).

  ECRC is an end-to-end data integrity guarantee and is a 32-bit CRC of the transaction layer packet (TLP) portion. This is because when an error occurs in the transaction layer packet (TLP) inside the switch or the like, the LCRC (link CRC) cannot detect the error (because the LCRC is recalculated with the TLP in error).

  Some requests do not require a completion packet, and some requests.

c. Traffic class (TC) and virtual channel (VC)
Upper software can differentiate (prioritize) traffic by using a traffic class (TC). For example, video data can be transferred with priority over network data. There are eight traffic classes (TC) from TC0 to TC7.

  A virtual channel (VC) is an independent virtual communication bus (a mechanism that uses a plurality of independent data flow buffers sharing the same link), each having resources (buffers and queues) As shown in FIG. 11, independent flow control is performed. Thereby, even if the buffer of one virtual channel becomes full (full), the transfer of another virtual channel can be performed. In other words, it can be effectively used by physically dividing one link into a plurality of virtual channels. For example, as shown in FIG. 11, when a route link is divided into a plurality of devices via a switch, the priority of traffic of each device can be controlled. VC0 is indispensable, and other virtual channels (VC1 to VC7) are mounted in accordance with the cost performance trade-off. The solid line arrow in FIG. 11 indicates the default virtual channel (VC0), and the broken line arrow indicates the other virtual channels (VC1 to VC7).

  Within the transaction layer, a traffic class (TC) is mapped to a virtual channel (VC). One or more traffic classes (TC) can be mapped to one virtual channel (VC) (when the number of virtual channels (VC) is small). In a simple example, it can be considered that each traffic class (TC) is mapped to each virtual channel (VC) on a one-to-one basis, and all traffic classes (TC) are mapped to the virtual channel VC0. The mapping of TC0-VC0 is essential / fixed, and the other mappings are controlled from the upper software. The software can control the priority of the transaction by using the traffic class (TC).

d. Flow control Flow control (FC) is performed in order to avoid overflow of the reception buffer and establish the transmission order. Flow control is done point-to-point between links, not end-to-end. Therefore, it cannot be confirmed that the packet has reached the final partner (completer) by flow control.

  PCI Express flow control is performed on a credit basis (mechanism to check the buffer availability on the receiving side before starting data transfer and prevent overflow and underflow). That is, the receiving side notifies the transmitting side of the buffer capacity (credit value) at the time of link initialization, and the transmitting side compares the credit value with the length of the packet to be transmitted, and transmits the packet only when there is a certain remaining. There are six types of credits.

  Flow control information exchange is performed using data link layer packets (DLLP) in the data link layer. The flow control is applied only to the transaction layer packet (TLP) and not to the data link layer packet (DLLP) (DLLP can always be transmitted / received).

B. Data link layer 154
The main role of the data link layer 154 is to provide a reliable transaction layer packet (TLP) exchange function between two components on the link, as described above.

a. Handling of transaction layer packet (TLP) For the transaction layer packet (TLP) received from the transaction layer 153, a 2-byte sequence number at the beginning and a 4-byte link CRC (LCRC) at the end are added to the physical layer. To 155 (see FIG. 9). The transaction layer packet (TLP) is stored in the retry buffer and retransmitted until a reception confirmation (ACK) is received from the partner. When the transmission of the transaction layer packet (TLP) continues to fail, it is determined that the link is abnormal, and the physical layer 155 is requested to retrain the link. If link training fails, the state of the data link layer 154 transitions to inactive.

  The transaction layer packet (TLP) received from the physical layer 155 is inspected for the sequence number and the link CRC (LCRC). If normal, the transaction layer packet (TLP) is passed to the transaction layer 153. If there is an error, a retransmission is requested.

b. Data link layer packet (DLLP)
The transaction layer packet (TLP) is automatically divided into data link layer packets (DLLP) as shown in FIG. 12 and transmitted to each lane when transmitted from the physical layer. A packet generated by the data link layer 154 is called a data link layer packet (DLLP), and is exchanged between the data link layers 154. Data link layer packet (DLLP)
-Ack / Nak: TLP reception confirmation, retry (retransmission)
-InitFC1 / InitFC2 / UpdateFC: Flow control initialization and update-DLLLP for power management
There are different types.

  As shown in FIG. 12, the length of the data link layer packet (DLLP) is 6 bytes. From the DLLP type (1 byte) indicating the type, the information specific to the type of DLLP (3 bytes), and CRC (2 bytes) Composed.

C. Physical layer-logical sub-block 156
The main role of the physical layer 155 in the logical sub-block 156 shown in FIG. 8 is to convert the packet received from the data link layer 154 into a format that can be transmitted by the electrical sub-block 157. It also has a function of controlling / managing the physical layer 155.

a. Data encoding and parallel-serial conversion
PCI Express uses 8B / 10B conversion for data encoding so that consecutive “0” s and “1” s do not continue (in order not to maintain a state where there is no cross point for a long period of time). The converted data is serial-converted and transmitted from the LSB onto the lane as shown in FIG. Here, when there are a plurality of lanes (FIG. 13 illustrates the case of x4 link), data is allocated to each lane in units of bytes before encoding. In this case, it looks like a parallel bus at first glance, but since the transfer is performed independently for each lane, the skew which is a problem with the parallel bus is greatly reduced.

b. Power Management and Link State In order to keep the power consumption of the link low, a link state of L0 / L0s / L1 / L2 is defined as shown in FIG.

  L0 is a normal mode, and power consumption is reduced from L0s to L2, but it takes time to return to L0. As shown in FIG. 15, by actively performing active state power management in addition to software power management, it is possible to reduce power consumption as much as possible.

D. Physical layer—Electric sub-block 157
The main role of the physical layer 155 in the electrical sub-block 157 is to transmit the data serialized in the logical sub-block 156 onto the lane, and to receive the data on the lane and pass it to the logical sub-block 156. is there.

a. AC coupling On the transmission side of the link, a capacitor for AC coupling is mounted. This eliminates the need for the DC common mode voltage on the transmission side and the reception side to be the same. For this reason, it is possible to use different designs, semiconductor processes, and power supply voltages on the transmission side and the reception side.

b. De-emphasis
In PCI Express, as described above, processing is performed so that continuous “0” and “1” do not continue as much as possible by 8B / 10B encoding, but continuous “0” and “1” may continue (maximum). 5 times). In this case, it is specified that the transmission side must perform de-emphasis transfer. When bits of the same polarity are consecutive, it is necessary to increase the noise margin of the signal received on the receiving side by dropping the differential voltage level (amplitude) from the second bit by 3.5 ± 0.5 dB. . This is called de-emphasis. Due to the frequency-dependent attenuation of the transmission line, there are many high-frequency components in the case of changing bits, and the waveform on the receiving side becomes small due to attenuation. Becomes larger. For this reason, de-emphasis is performed in order to make the waveform on the receiving side constant.

[What is Advanced Switch Interconnect]
Next, the present embodiment uses the Advanced Switch Interconnect utilizing the above-described PCI Express technology, and an outline of the Advanced Switch Interconnect will be described as a premise of the present embodiment.

  In recent years, the fusion of computing and communication has rapidly progressed against the background of advances in broadband and semiconductor technologies, and the emergence of standards capable of widely supporting new application systems has been desired. Therefore, the ASI (Advanced Switching Interconnect) standard using the PCI Express technology has appeared, and it is assumed to be applied to a wide range of applications from computing to communication. The formulation and dissemination of ASI specifications is managed by a non-profit organization, Advanced Switching Interconnect Special Interest Group (ASI-SIG).

[Overview of Advanced Switch Interconnect technology]
Next, an overview of the Advanced Switch Interconnect technology will be described.

  First, the relationship between PCI Express and ASI (Advanced Switching Interconnect) will be described. FIG. 16 shows the relationship between the PCI Express and ASI (Advanced Switching Interconnect) protocol stacks. ASI (Advanced Switching Interconnect) is a technology that uses the physical layer and link layer technology of PCI Express high-speed serial transmission as it is, and is compatible with a wider range of applications. The connection target is Chip-to-Chip. , Board-to-Board is assumed. PCI Express inherits PCI transactions cultivated in computing as it is, but ASI (Advanced Switching Interconnect) has expanded the functions by replacing the transaction layer of PCI Express, and more advanced data flow and protocol It can be adapted to. In addition, the connection structure has been expanded from the PCI Express tree structure so that a fabric structure with a higher degree of freedom can be created, and it also supports a multi-CPU environment. In ASI (Advanced Switching Interconnect), the routing method is remarkably improved and higher speed than other standards (Ethernet (registered trademark), InfiniBand, etc.) capable of the same fabric structure is achieved.

  The fabric management function (AS Fabric Mngmnt) shown in Fig. 16 is part of the ASI (Advanced Switching Interconnect) protocol that is configured by software. Connection setup and removal, event management, performance and operational status monitoring, and redundant routes Supports various services such as path invalidation, resource allocation and load leveling. FIG. 17 shows an initialization sequence in the fabric management function.

  In ASI (Advanced Switching Interconnect), as shown in FIG. 18, by adopting a method of encapsulating various protocols, an attempt is made to increase the speed of more advanced protocol (TCP / IP, Fiber Channel, etc.) services. . An upper layer of ASI (Advanced Switching Interconnect) has a part called PEI (Protocol Encapsulation Interface), and has a function of adding an ASI header to various packets arrived from the outside and converting them into ASI packets. A packet that has passed through the ASI fabric is extracted as an original packet with the ASI header removed by the PEI on the receiving side. The upstream protocol interface is called PI (pi), and it adopts a mechanism that can support various standards and also implement AS Native and Vendor Specific protocols. A profile in which PCI Express and ASI (Advanced Switching Interconnect) are connected by a bridge and the PCI Express protocol is encapsulated and transferred is defined as PI-8.

[Features of Advanced Switch Interconnect technology]
ASI (Advanced Switching Interconnect) is a feature of PCI Express, in addition to the high speed, bandwidth scalability, physical layer expandability by hierarchical structure, data reliability, etc. ) Has its own characteristics.
・ Support for unreliable (lossy) packet transmission such as video ・ Multicast and broadcast packet support ・ Multi-protocol transmission by encapsulation ・ High-speed original path routing method ・ Support for congestion management function ・ Support for fabric structure

  Such a feature makes it possible to share storage and IO resources between a plurality of devices as shown in FIG. Also, until now, PCI, PCI-X, PCI Express, HyperTransport, RapidIO, StarFabric and other standards require complicated connection methods because the physical layer is different even if the same load / store protocol is used. By using ASI (Advanced Switching Interconnect) technology, mutual communication as shown in FIG. 20 can be realized simply, and the communication speed between devices is increased. It is also possible to construct a local system that realizes communication such as TCP / IP at a higher speed than ordinary Ethernet (registered trademark) processing by tunneling various upper protocols. Furthermore, it is possible to improve the robustness by providing the system with redundancy by adapting to the fabric structure, etc., and to dynamically switch the routing path.

  In addition, Advanced Switching Interconnect superimposes the physical layer and data link layer of PCI Express with an optimized transaction layer and provides various functions. A characteristic function of the transaction layer is multi-level QoS (Quality of Service). QoS supports 20 virtual channels (VCs) and 8 traffic classes (TCs).

  A fabric management function (AS Fabric Mngmnt), which is higher-order software that controls Advanced Switching Interconnect (ASI), can differentiate (prioritize) traffic by using a traffic class (TC). For example, video data can be transferred with priority over network data. There are eight traffic classes (TC) from TC0 to TC7.

  A virtual channel (VC) is an independent virtual communication bus (a mechanism that uses a plurality of independent data flow buffers sharing the same link), each having resources (buffers and queues) Perform independent flow control. Thereby, even if the buffer of one virtual channel becomes full (full), the transfer of another virtual channel can be performed. In other words, it can be effectively used by physically dividing one link into a plurality of virtual channels.

  Within the transaction layer, a traffic class (TC) is mapped to a virtual channel (VC). One or more traffic classes (TC) can be mapped to one virtual channel (VC) (when the number of virtual channels (VC) is small). In a simple example, it can be considered that each traffic class (TC) is mapped to each virtual channel (VC) on a one-to-one basis, and all traffic classes (TC) are mapped to the virtual channel VC0. The mapping of TC0-VC0 is essential / fixed, and the other mappings are controlled from the upper software. The software can control the priority of the transaction by using the traffic class (TC).

  Also, in the ASI fabric, a Congestion state may occur due to excessive traffic. When falling into the Congestion state, there is a problem that the response time of the packet becomes long and a constant service level cannot be maintained. Therefore, in the ASI (Advanced Switching Interconnect) standard, this problem is solved by providing Status-Based Flow Control (SBFC) as a Congestion Management function.

  Here, Congestion Management will be specifically described. As shown in FIG. 21A, when traffic 1-3 exists in three switches, it is assumed that traffic 1 and traffic 2 are initially performing desired data transfer. Here, it is assumed that excessive traffic exceeding the capability of port A is generated as traffic 3. This effect appears as a decrease in traffic 2 to the same output port A. Further, not only the traffic 2 but also the traffic of the traffic 1 passing through the same link as the traffic 2 is reduced.

  Therefore, as shown in FIG. 21-2, the output of the traffic 2 can be suppressed by informing the adjacent switch that the port A is crowded using the SBFC. Is no longer affected.

By the way, there are three types of ASI (Advanced Switching Interconnect) virtual channels (VC) as shown below.
BVC (Bypass Capable Unicast): VC Ids 0-7
OVC (Ordered-Only Unicast): VC Ids 8-15
MVC (Multicast): VC Ids 16-19

  As shown in FIG. 22, BVC (Bypass Capable Unicast) allows a previously input queue to be bypassed and allows a queue input later to leave the arbiter (arbitration circuit).

  In OVC (Ordered-Only Unicast), as shown in FIG. 23, the previously input Queue is output as it is.

  In MVC (Multicast), as shown in FIG. 24, an input Queue is output in a multicast manner.

[Configuration of information processing device]
FIG. 25 is a schematic block diagram illustrating a configuration example of the information processing apparatus 1 according to the present embodiment. An information processing apparatus 1 according to the present embodiment is applied to a device such as an MFP (Multi Function Peripheral), for example, and various endpoint devices via an ASI (Advanced Switching Interconnect) 2 that is a high-speed serial switch fabric. And switch output ports (hereinafter referred to as devices). Here, as various devices connected to the ASI 2, a system controller 3, a scanner 4 as an image input device, a plotter 5 as an image output device, a first image memory 6 as a storage device, and a second as a storage device. The image memory 7, the image processing unit 8, the external I / O 9, and the operation panel 10 are connected.

  The system controller 3 includes a CPU (Central Processing Unit) that controls the entire apparatus according to an installed program (software), and means a device portion (printer controller) that performs processing such as path control and path determination. .

  The scanner 4 indicates a device or a unit part for taking in image data based on an original image or the like into the system, and is composed of, for example, a scanner engine that photoelectrically reads an original image and acquires image data. .

  The plotter 5 is a device or unit that prints out image data on paper or the like, and is configured by, for example, an electrophotographic plotter (printer) engine. As the printing method of the plotter 5, various methods such as an ink jet method, a sublimation type thermal transfer method, a silver salt photography method, a direct thermal recording method, and a melt type thermal transfer method can be used in addition to the electrophotographic method.

  The image memories 6 and 7 are HDD (Hard Disk Drive), RAM (Random Access Memory), and the like, and store image data read by the scanner 4 and the like.

  The image processing unit 8 performs various types of image processing on the image data read by the scanner 4.

  The external I / O 9 exchanges image data, control data, and the like with other connected devices.

  The operation panel 10 includes a touch panel and a display panel, and receives input of various commands to the apparatus.

  The image processing unit 13 executes various types of image processing on the image data read by the scanner 4 according to a user instruction or according to characteristics of the information processing apparatus 1. The image processing unit 13 outputs the processed image data to the plotter 5.

  Here, a characteristic function provided in the information processing apparatus 1 according to the present embodiment will be described. In the information processing apparatus 1 according to the present embodiment, traffic priorities are assigned to various devices and assigned to different virtual channels (VCs). This point will be described in detail below.

  FIG. 26 is a block diagram partially showing in detail the configuration of the information processing apparatus 1 of FIG. FIG. 26 particularly shows a state in which the scanner 4, the image processing unit 13, and the plotter 5 are connected via the ASI 2. The configuration of each device includes a communication core 20 composed of a transaction layer (TL), a data link layer (DL), and a physical layer (PL), and device-specific functions other than the communication core portion (scanner 4: data input unit 4a, image Processing unit 13: image processing unit 13 a, plotter 5: data output unit 5 a), data transfer module 30, and traffic class setting means 40.

  The traffic class setting means 40 has a function of assigning traffic generated in each data transfer module 30 to a traffic class.

  The communication core 20 transaction layer (TL) includes channel setting means 50 for assigning a traffic class (TC) to a virtual channel (VC).

  As shown in FIG. 26, the traffic class setting unit 40 and the channel setting unit 50 may be configured so that the allocation can be freely controlled, or the traffic from the data transfer module 30 is reduced to the virtual channel ( VC) may be uniquely determined.

  FIG. 27 is a block diagram showing in detail the configuration of the device. With reference to FIG. 27, the operation of each part constituting the device will be described in detail. In FIG. 27, traffic is exemplarily described.

  The traffic class setting means 40 includes a setting table 40a, a selector 40b, and an arbiter 40c. In the configuration shown in FIG. 27, the traffic of each data transfer module 30 can be set to all the traffic classes (TC), but there is no problem even if the configuration can provide the minimum necessary correspondence. At that time, a minimum number of selectors 40b and arbiters 40c may be prepared.

  FIG. 28 is a schematic diagram illustrating an example of the setting table 40a. As shown in FIG. 28, the setting table 40a stores a traffic class (TC) set by the traffic class setting unit 40 for each traffic (for each type of traffic command). In the example shown in FIG. 28, the data transfer module (1) and the data transfer module (2) issue a memory write command, and the data transfer module (3) issues a memory read command. In this embodiment, a traffic class (TC) associated with each type of traffic command is determined. Therefore, the setting table 40a is a control command for the selector (1) and the selector (2) in order to assign the data transfer module (1) and the data transfer module (2) issuing the memory write command to TC0. Issue 0 ”. In order to allocate the data transfer module (3) for issuing the memory read command to the TC 6, the setting table 40a issues “6” which is a control command for the selector (3).

  The channel setting means 50 includes a setting table 50a and an arbiter 50b. In the configuration shown in FIG. 27, the minimum necessary correspondence is possible. However, each traffic class (TC) is set so that traffic of each traffic class (TC) can be set to all virtual channels (VC). Alternatively, a selector may be provided. In this case, like the traffic class setting unit 40, the channel setting unit 50 is also configured by a setting table, a selector, and an arbiter.

  Next, an operation of associating traffic generated in the data transfer module 30 with a traffic class (TC) by the traffic class setting unit 40 will be described.

  In order to allocate the traffic (1) generated in the data transfer module (1) to TC0, a control signal is sent from the setting table 40a of the traffic class setting means 40 to the selector (1) and the arbiter (00). The selector (1) selects an output port based on the received control signal and transmits the traffic (1) to the arbiter (00). The arbiter (00) arbitrates the input signal based on the control signal from the setting table 40a, although no competing traffic is input in the example shown in FIG. As a result, traffic (1) is allocated to TC0.

  Similarly, in order to allocate the traffic (2) generated in the data transfer module (2) to TC1, a control signal is sent from the setting table 40a of the traffic class setting means 40 to the selector (2) and the arbiter (01). The selector (2) selects an output port based on the received control signal and transmits the traffic (2) to the arbiter (01). The arbiter (01) arbitrates the input signal based on the control signal from the setting table 40a, although no competing traffic is input in the example shown in FIG. As a result, traffic (2) is allocated to TC1.

  Similarly, in order to allocate the traffic (3) generated in the data transfer module (3) to the TC 6, a control signal is sent from the setting table 40a of the traffic class setting means 40 to the selector (3) and the arbiter (06). The selector (3) selects an output port based on the received control signal and transmits the traffic (3) to the arbiter (06). In the example shown in FIG. 27, the arbiter (06) does not receive competing traffic, but arbitrates the input signal based on the control signal from the setting table 40a. As a result, traffic (3) is allocated to TC6.

  Next, the operation in which the traffic associated with each traffic class (TC) is associated with the virtual channel (VC) by the channel setting means 50 will be described.

  The traffic of TC0 (traffic (1)) and TC1 (traffic (2)) is input to the arbiter (10). The arbiter (10) performs arbitration of the input signal based on the control signal from the setting table 50a. As a result, the traffic of TC0 (traffic (1)) and TC1 (traffic (2)) is allocated to VC0.

  Similarly, the traffic of TC6 (traffic (3)) and TC7 (no traffic) is input to the arbiter (13). In the example shown in FIG. 27, the arbiter (13) does not receive competing traffic, but arbitrates the input signal based on the control signal from the setting table 50a. As a result, the traffic of TC6 (traffic (3)) is allocated to VC3.

[Operation example]
Here, an operation example will be described. An example of traffic classification for data communication between devices is as follows.
・ LSYNC isochronous constraint Traffic 1 Scanner 4 → Image memory 6 (7)
Traffic 2 Image memory 6 (7) → Plotter 5
-Page isochronous constraints Traffic 3 Image memory 6 (7) → Image memory 7 (6)
Traffic 4 Image memory 6 (7) → Image processing unit 8
Traffic 5 Image processing unit 8 → Image memory 6 (7)

Then, the priority (priority) of data communication is given using the traffic class (TC) for each classified traffic. Here, the priority (priority) of data communication is set by the traffic class setting means 40,
Traffic 2> Traffic 1> Traffic 3, 4, 5
And That is, in data communication between devices, traffic with high LSYNC isochronous restrictions is preferentially data communication. Each traffic class (TC) for which the priority (priority) of data communication is determined is mapped with a virtual channel (VC) by the channel setting means 50. In the present embodiment, it is assumed that one traffic class (TC) is mapped to one virtual channel (VC). As a result, the fabric management function (AS Fabric Management), which is the upper software for controlling the Advanced Switching Interconnect (ASI), can control the priority of transactions by using the traffic class (TC). .

  Here, as shown in FIG. 29, when a copying operation is performed, that is, data read by the scanner 4 of the information processing apparatus 1 is transferred to the image memory 6, and the image data stored in the image memory 6 is transferred to the plotter. Consider the case of output from 5. In this case, it is preferable that the image data memory write command is issued after all the image data memory read commands are issued. This is because if the memory read command is not prioritized, the memory read data may not be received within the line valid period due to the timing constraint of line synchronous transfer.

Therefore, when the memory read command and the memory write command conflict with each other in the ASI (Advanced Switching Interconnect) 2, high-speed data transfer can be performed by following the priority (priority) of traffic in the virtual channel shown below. You will be able to deal with it.
Traffic 2 (memory read command)> Traffic 1 (memory write command)

  As described above, according to the present embodiment, a traffic class is set for each traffic in the devices 3 to 10 in which contention occurs, and each of the set traffic classes is assigned to a different virtual channel to give priority to data communication. As a result, the devices 3 to 10 having different traffics of various properties can be freely expanded to the ASI (Advanced Switching Interconnect) 2 that is a high-speed serial switch fabric.

[Second Embodiment]
Next, a second embodiment of the present invention will be described with reference to FIGS. The same parts as those in the first embodiment described above are denoted by the same reference numerals, and description thereof is also omitted.

  FIG. 30 is a schematic block diagram illustrating a configuration example of the information processing system 60 according to the present embodiment. An information processing system 60 according to the present embodiment is obtained by connecting information processing apparatuses 61 including a single image memory 6 via an ASI (Advanced Switching Interconnect) 2.

  In such a configuration, as shown in FIG. 31, when copying is performed in both information processing apparatuses 61, that is, each information processing apparatus is configured to output data read by the scanner 4 of one information processing apparatus 61 by multicast output. Consider a case where data is transferred to the image memory 6 of 61 and the image data stored in the image memory 6 of each information processing device 61 is output from the plotter 5 of each information processing device 61. By transferring data to the image memory 6 of each information processing device 61 in this way, the latency (data request is made after the data request is made using the image memory 6 that each has, until the data is actually transferred. The delay time) can be solved.

Even in this case, since the memory read command and the memory write command compete in the ASI (Advanced Switching Interconnect) 2 of each information processing device 61, the priority (priority) of traffic in the virtual channel shown below is obeyed. This makes it possible to cope with high-speed data transfer.
Traffic 2 (memory read command)> Traffic 1 (memory write command)

  Next, as shown in FIG. 32, when a copy operation is performed in both information processing apparatuses 61, that is, data read by the scanner 4 of one information processing apparatus 61 is converted into the image memory 6 of one information processing apparatus 61. Consider the case where the plotter 5 of each information processing device 61 issues a memory read command to each image memory 6 and outputs the image data stored in the image memory 6. Thus, by transferring data only to the image memory 6 of one information processing apparatus 61, memory consumption can be reduced.

Even in this case, since the memory read command and the memory write command compete with each other in the ASI (Advanced Switching Interconnect) 2 of the information processing apparatus 61, the priority of the traffic in the virtual channel (priority) shown below is obeyed. Will be able to deal with high-speed data transfer.
Traffic 2 (memory read command)> Traffic 1 (memory write command)

  Next, as shown in FIG. 33, when a copying operation is performed in both information processing apparatuses 61, that is, data read by the scanner 4 of one information processing apparatus 61 is converted into an image memory 6 of one information processing apparatus 61. Consider a case where the image data stored in the image memory 6 is output from the plotter 5 of each information processing device 61 by generating a memory write transfer by multicast output. By generating memory write transfer by multicast output in this way, it is possible to reduce traffic compared to when the plotter 5 of each information processing device 61 issues a memory read command to each image memory 6.

Even in this case, since the memory read command and the memory write command compete with each other in the ASI (Advanced Switching Interconnect) 2 of the information processing apparatus 61, the priority of the traffic in the virtual channel (priority) shown below is obeyed. Will be able to deal with high-speed data transfer.
Traffic 2 (memory read command)> Traffic 1 (memory write command)

It is a block diagram which shows the structural example of the existing PCI system. FIG. 2 is a block diagram illustrating a configuration example of a PCI Express system. It is a block diagram which shows the structural example of the PCI Express platform in desktop / mobile. It is a schematic diagram which shows the structural example of the physical layer in the case of x4. It is a schematic diagram which shows the example of lane connection between devices. It is a block diagram which shows the logical structural example of a switch. It is a block diagram which shows the architecture of the existing PCI. It is a block diagram which shows the architecture of PCI Express. It is a block diagram which shows the hierarchical structure of PCI Express. It is explanatory drawing which shows the format example of a transaction layer packet. It is explanatory drawing which shows the configuration space of PCI Express. It is a schematic diagram for demonstrating the concept of a virtual channel. It is explanatory drawing which shows the format example of a data link layer packet. It is a schematic diagram which shows the byte striping example in x4 link. It is explanatory drawing explaining the definition of the link state of L0 / L0s / L1 / L2. It is a time chart which shows the example of control of active state power management. It is explanatory drawing which shows the relationship between PCI Express architecture and Advanced Switching Interconnect. It is explanatory drawing which shows the initialization sequence in a fabric management function. It is explanatory drawing which shows the encapsulation of the protocol in Advanced Switching Interconnect. It is explanatory drawing which shows the sharing of the storage and IO resource between several devices by Advanced Switching Interconnect. It is explanatory drawing which shows the example of communication by Advanced Switching Interconnect. It is explanatory drawing shown about Congestion Management. It is explanatory drawing shown about Congestion Management. It is a schematic diagram for demonstrating BVC (Bypass Capable Unicast). It is a schematic diagram for demonstrating OVC (Ordered-Only Unicast). It is a schematic diagram for demonstrating MVC (Multicast). It is a schematic block diagram which shows the structural example of the information processing apparatus concerning the 1st Embodiment of this invention. FIG. 26 is a block diagram partially showing in detail the configuration of the information processing apparatus of FIG. 25. It is a block diagram which shows the structure of a device in detail. It is a schematic diagram which shows an example of a setting table. It is a schematic block diagram which shows an example of the priority control of the transaction in copy operation | movement. It is a schematic block diagram which shows the structural example of the information processing system concerning the 2nd Embodiment of this invention. It is a schematic block diagram which shows an example of the priority control of the transaction in copy operation | movement. It is a schematic block diagram which shows an example of the priority control of the transaction in copy operation | movement. It is a schematic block diagram which shows an example of the priority control of the transaction in copy operation | movement.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1,61 Information processing apparatus 2 High-speed serial switch fabric 3-10 Device 40 Traffic class setting means 50 Channel setting means 60 Information processing system

Claims (11)

In an information processing apparatus that connects multiple devices via a high-speed serial switch fabric that can map traffic classes that can differentiate traffic to virtual channels,
Traffic class setting means for setting the traffic class for each traffic in the device in which contention occurs;
Channel setting means for assigning each traffic class set by the traffic class setting means to a different virtual channel and giving priority to data communication;
An information processing apparatus comprising: The high-speed serial switch fabric is an Advanced Switching Interconnect standard switch fabric,
The information processing apparatus according to claim 1. By setting the virtual channel, the priority of the traffic class of traffic having isochronous restrictions in line synchronization signal units is made higher than the priority of the traffic class of traffic having isochronous restrictions in page units.
The information processing apparatus according to claim 1 or 2. By setting the virtual channel, the priority of the traffic class of the memory read transaction is made higher than the priority of the traffic class of the memory write transaction.
The information processing apparatus according to claim 1 or 2. Information processing apparatus comprising: an image input device that reads image data; a storage device that stores image data read by the image input device; and an image output device that outputs the image data stored in the storage device In an information processing system that connects multiple devices via a high-speed serial switch fabric,
The image data read by the image input device of the one information processing apparatus is transferred to the storage device of each information processing apparatus by multicast output, and the image data stored in each storage device is transferred to the information When outputting from the image output device of the processing device, the priority of data communication in the virtual channel of the high-speed serial switch fabric,
Memory read command> Memory write command
An information processing system characterized by this. Information processing apparatus comprising: an image input device that reads image data; a storage device that stores image data read by the image input device; and an image output device that outputs the image data stored in the storage device In an information processing system that connects multiple devices via a high-speed serial switch fabric,
The image data read by the image input device of the one information processing apparatus is transferred to the storage device, and the image output device of each information processing apparatus corresponds to the storage device in which the image data is stored. When issuing each memory read command and outputting the image data stored in the storage device, the priority of data communication in the virtual channel of the high-speed serial switch fabric,
Memory read command> Memory write command
An information processing system characterized by this. Information processing apparatus comprising: an image input device that reads image data; a storage device that stores image data read by the image input device; and an image output device that outputs the image data stored in the storage device In an information processing system that connects multiple devices via a high-speed serial switch fabric,
The image data read by the image input device of the one information processing apparatus is transferred to the storage device, and the image data stored in the storage device is subjected to memory write transfer by multicast output to generate each of the information When outputting from the image output device of the processing device, the priority of data communication in the virtual channel of the high-speed serial switch fabric,
Memory read command> Memory write command
An information processing system characterized by this. A data communication method in an information processing apparatus in which a plurality of devices are connected via a high-speed serial switch fabric capable of mapping a traffic class capable of differentiating traffic to a virtual channel,
A traffic class setting step for setting the traffic class for each traffic in the device in which contention occurs;
A channel setting step of assigning each traffic class set by the traffic class setting step to a different virtual channel to give a priority of data communication;
A data communication method comprising: The high-speed serial switch fabric is an Advanced Switching Interconnect standard switch fabric,
9. The data communication method according to claim 8, wherein: By setting the virtual channel, the priority of the traffic class of traffic having isochronous restrictions in line synchronization signal units is made higher than the priority of the traffic class of traffic having isochronous restrictions in page units.
10. The data communication method according to claim 8 or 9, wherein: By setting the virtual channel, the priority of the traffic class of the memory read transaction is made higher than the priority of the traffic class of the memory write transaction.
10. The data communication method according to claim 8 or 9, wherein:

Images