JP2004118246A - Image processing apparatus - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To reduce the cost by enhancing the use efficiency of a work area in an image processing apparatus and reducing the memory capacity required by the whole processor. <P>SOLUTION: In conducting required image processing for an input image data by a combination of a plurality of image processing means 11 to 13 for respectively conducting different image processing, a work area managing means 20 for collectively managing a work area (memory group) 30 most suitably assigns the respectively required work areas to the work area 30 according to each processing content and the processing mode by the respective image processing means 11 to 13. <P>COPYRIGHT: (C)2004,JPO

Description

[0001]
TECHNICAL FIELD OF THE INVENTION
The present invention relates to an image processing apparatus that performs a plurality of types of image processing, and for example, to an image processing apparatus that can be applied to all devices that require image processing, such as digital copiers, printers, image scanners, and digital cameras.
[0002]
[Prior art]
In a conventional image processing apparatus, generally, a work area (memory or memory area) necessary for image processing is fixed in advance to a work area having a maximum capacity required according to the content of image processing (type and mode of image processing). Had been placed.
For example, as shown in FIG. 10, an image for which image processing is performed by a combination of a first image processing unit 101, a second image processing unit 102, and a third image processing unit 103 that performs different image processing on input image data, respectively. In the processing apparatus, a first memory 104, a second memory 105, and a third memory 106 each having a maximum memory capacity required for each processing are fixed to each of the image processing units 101, 102, and 103 in advance. Are located. Therefore, the capacity of the memory provided in the entire image processing apparatus is the sum of the maximum memory capacity required by each of the image processing units 101 to 103.
[0003]
Specific examples are shown in FIGS. For example, as shown in FIG. 11, the first image processing means 101 performs image scaling processing, the second image processing means 102 performs filter processing, and the third image processing means 103 performs image compression processing. When each process has two processing modes as shown in FIG. 12, the arrangement of the memory as a work area is as shown in FIG.
In other words, the memory must be arranged for each of the image processing means 101 to 102, assuming the processing which uses the larger amount of memory among the two processing modes A and B. It is necessary to previously arrange four line memories as the first memory 104 for processing, five as the second memory 105 for the filter processing, and eight line memories as the third memory 106 for the image compression processing. Each line memory is 8 bits × 10000 words.
[0004]
In addition, a common image memory is used to temporarily store input image data or to perform image processing on the image data and store the image data.
For example, Patent Literature 1 discloses an image memory access device in which an address is converted by an image memory control device so that an image processing device performing various image processing can easily access an image memory.
Alternatively, the common memory is divided and used for a plurality of purposes, and a work area used when performing image processing and a storage area for storing processed image data are divided, and the capacity is monitored. Its use is disclosed in US Pat.
[0005]
[Patent Document 1]
JP 2001-243112 A [Patent Document 2]
JP-A-2002-117399 [0006]
Incidentally, in order to increase the speed of image processing by the image processing apparatus, it is effective to improve the access speed of the image processing means to the work area (memory or memory area). Therefore, for example, when all the memories in the image processing apparatus are SDRAMs 133, conventionally, all the memories are replaced with, for example, DDR266 which is a memory having a high access speed, thereby realizing high-speed image processing.
[0007]
[Problems to be solved by the invention]
However, in the case of the conventional image processing apparatus described with reference to FIGS. 10 to 12, the first image processing unit 101 uses the line memory of the first memory 104 when performing the image scaling processing in the processing mode A. Are used, but only two are used in the processing mode B. The second image processing means 102 uses all five line memories of the second memory 105 when performing the filter processing in the processing mode A, but uses only three line memories in the processing mode B. The third image processing means 103 uses all eight line memories of the third memory 106 when there is image compression for performing image compression in the processing mode B, but when there is no image compression in the processing mode B. Not used at all.
Therefore, there is a problem that the memory use efficiency is reduced depending on the processing mode of the image processing, and as a result, the memory amount of the entire image processing apparatus is increased.
[0008]
However, only the technique of sharing a common memory for different purposes as disclosed in Patent Literature 1 and Patent Literature 2 is an image processing for performing image processing by combining a plurality of image processing means for performing different types of image processing. The above problems in the device cannot be solved.
SUMMARY OF THE INVENTION The present invention has been made to solve this problem, and improves the use efficiency of a work area (memory or memory area) in an image processing apparatus, reduces the necessary memory capacity (number of memories) in the entire apparatus, and reduces costs. A common goal is to go down. Still another object is to realize high-speed image processing by the image processing apparatus without increasing the cost.
[0009]
[Means for Solving the Problems]
The present invention provides an image processing apparatus that performs image processing by combining a plurality of image processing units that perform different image processing on input image data, in order to achieve the above object. A work area management means for collectively managing work areas required by the plurality of image processing means, and the work area management means is required for each of the plurality of image processing means. By assigning a work area, the use efficiency of the work area is improved.
[0010]
Further, two or more types of work areas having different access speeds are provided in a work area managed by the work area management means, and the work area management means performs processing having the slowest processing speed among the plurality of image processing means. By assigning the work area having the fastest access speed among the two or more kinds of work areas to the image processing means to be performed, it is possible to increase the speed of image processing with minimum cost increase. it can. Further, the work area management means may allocate a required work area to each of the plurality of image processing means in accordance with work area control information provided from outside. This eliminates the need for the work area management means to determine the content to be processed by each image processing means, and can simplify the configuration.
[0011]
BEST MODE FOR CARRYING OUT THE INVENTION
Hereinafter, embodiments of the present invention will be specifically described with reference to the drawings. First, a basic configuration of an image processing apparatus according to the present invention will be described with reference to FIGS. FIG. 1 is a block diagram showing a basic configuration of a first embodiment of an image processing apparatus according to the present invention.
The image processing apparatus 1 mainly includes a first image processing unit 11, a second image processing unit 12, a third image processing unit 13, a work area management unit 20, and a work area 30.
[0012]
The first image processing unit 11 to the third image processing unit 13 sequentially perform different image processing such as image scaling processing, filter processing, image compression processing, and the like on input image data, and output the output image data. The work area management means 20 collectively manages a group of memories in the work area 30 and assigns them to each image processing means 11 to 13 in accordance with the processing content (type of image processing and processing mode) executed by each image processing means 11 to 13. A function of allocating a necessary work area to the work area 30 is provided.
[0013]
Next, FIG. 2 is a block diagram showing a basic configuration of a second embodiment of the image processing apparatus according to the present invention. This image processing apparatus 1 'includes a first image processing unit 11, a second image processing It mainly comprises a unit 12, a third image processing unit 13, a work area management unit 21, a first work area 30A and a second work area 30B.
In this embodiment, the difference from the first embodiment shown in FIG. 1 is that the work area managed by the work area management means 21 is a first work area 30A having a medium access speed and a second work area having a medium access speed. 2 work area 30B, and the work area management means 21 provides the work area with the fastest access speed to the image processing means which performs the slowest processing among the plurality of image processing means 11 to 13. The second embodiment has a function of allocating a second work area 30B, and the other configurations and functions are the same as those of the image processing apparatus 1 of FIG.
[0014]
FIG. 3 is a block diagram showing a basic configuration of an image processing apparatus according to a third embodiment of the present invention. This image processing apparatus 1 ″ includes a first image processing unit 11, a second image processing unit. 12, a third image processing means 13, a work area management means 22, and a work area 30.
The difference between this embodiment and the first embodiment shown in FIG. 1 is that the work area management means 22 is required for each of the image processing means 11 to 13 according to the work area control information provided from the outside. It has a function of allocating a work area to the work area 30, and other configurations and functions are the same as those of the image processing apparatus 1 of FIG.
[0015]
Here, the first embodiment shown in FIG. 1 will be described more specifically with reference to FIGS. In FIG. 5, the memory control device 40 and the memory group 50 correspond to the work area management means 20 and the work area 30 in FIG. Then, the memory control device 40 receives the image data and the image processing information from the first image processing unit 11, the second image processing unit 12, and the third image processing unit 13, respectively. It has a function of calculating a necessary memory amount and optimally allocating an area (the number of memories) in the memory group 50 as a work area to each image processing.
[0016]
FIG. 5 shows the first to third image processing means 11 to 13 in FIG. 4 in terms of image scaling processing, filter processing, and image compression processing which are the respective image processing contents. It is composed of memories 51 to 63. Each of the line memories has a storage capacity of 8 bits × 1000 words.
In order to perform the image processing in the processing mode A shown in FIG. 12 by this image processing apparatus, four images are required for the image scaling process performed by the first image processing unit 11, and the filtering process is performed for the second image processing unit 12. Five and zero line memories are required for the image compression processing performed by the third and third image processing means 13, respectively.
[0017]
The memory control device 40 switches the paths between the image processing units 11 to 13 and the line memories 51 to 63 of the memory group 50 according to the required amount, and sends the first image processing unit 11 that performs image scaling processing to the first image processing unit 11. Is connected to four line memories 51 to 54, and five line memories 55 to 59 are connected to the second image processing means 12 for performing a filtering process.
Similarly, when performing the image processing in the processing mode B shown in FIG. 12, the first image processing unit 11 that performs the image scaling process has two lines, and the second image processing unit 12 that performs the filter processing has three lines. The third image processing means 13 for performing the image compression processing requires eight line memories.
[0018]
That is, the memory control device 40 allocates the line memories 51 to 51 of the memory group 50 according to the required amount. That is, the first image processing means (image scaling processing) 11 has two line memories 51 and 52, the second image processing means (filter processing) 12 has three line memories 53 to 55, Eight line memories 56 to 63 are connected to the image processing means (image compression processing). As described above, the memory control device 40 collectively manages the memory group 50 so as to allocate a necessary number of line memories to each of the image processing units 11 to 13 in accordance with the type of image processing and the processing mode in which the content is specified. Thus, the use efficiency of the memory group 50 can be improved.
[0019]
Next, an example in which this embodiment is partially modified will be described with reference to FIG.
In the example shown in FIG. 6, the memory control device 41 has a function slightly different from that of the memory control device 40 in FIG. That is, although only the line memories 51 to 63 of the 8-bit bus are prepared in the memory group 50 of the image processing apparatus, if the first image processing means 11 performs the image scaling processing, the memory of the 16-bit bus is required. When it becomes necessary, the memory control device 41 simultaneously accesses two line memories of the 8-bit bus (the line memories 51 and 52 in this example) so that the first image processing means 11 can access the memory of the 16-bit bus. To make it look as if it were.
[0020]
When a 24-bit bus memory is required for the second image processing means 12 to perform the filtering process, the memory controller 41 simultaneously accesses the three line memories (the line memories 53 to 55 in this example). Make it possible by doing Since the memory control device 41 collectively manages the line memories 51 to 63 of the memory group 50 as described above, memories having different bit widths can be created virtually, and the image processing means 11 to 13 and the memory The difference in the bit width of the bus between the groups 50 can be absorbed.
[0021]
Next, a more specific example of the second embodiment of the present invention shown in FIG. 2 will be described with reference to FIG.
Also in FIG. 7, the first to third image processing units 11 to 13 shown in FIG. 2 are shown by image scaling processing, filter processing, and image compression processing which are the respective image processing contents. A first memory group 60 composed of SDRAMs 133 composed of line memories 65 to 69 and a second memory group 70 composed of DDR 266 composed of line memories 71 to 78 correspond to the first work area 30A and the second work area 30B in FIG. I do.
The DDR 266 as the second memory group 70 is a high-speed access memory, and has an access speed twice that of the SDRAM 133 as the first memory group 60. The memory control device 42 that collectively manages the first and second memory groups 60 and 70 as a work area corresponds to the work area management unit 21 in FIG.
[0022]
The processing speed of each image processing by the first to third image processing means 11 to 13 in this image processing apparatus is such that the image scaling processing performed by the first image processing means 11 is 10 Mbit / sec, and the processing speed of the second image processing means 12 is performed. It is assumed that the filtering process is 6 Mbit / sec and the image compression process performed by the third image processing unit 13 is 2 Mbit / sec.
In this case, the processing speed of the entire image processing apparatus depends on the image compression processing having the lowest processing speed. The processing speed is 2 Mbit / sec.
[0023]
However, in the image processing apparatus of this embodiment, when the processing mode of the image processing is set, the memory control device 42 operates the image processing means having the slowest processing speed, in this example, the third image processing means 13 which performs the image compression processing. , The line memories 71 to 78 of the second memory group 70 having a higher access speed are assigned preferentially, and the first and second image processing means 11 and 12 which perform image scaling processing and filter processing have a lower access speed. The line memories 65 to 69 of one memory group 60 are allocated according to the amount of memory required for each process.
[0024]
In this way, by using the DDR 266 of the high-speed access memory for the image compression processing, the substantial processing speed is doubled to 4 Mbit / sec. As a result, the processing speed of the entire image processing apparatus is also doubled to 4 Mbit / sec, so that the processing speed is doubled.
Therefore, according to this embodiment, the memory having the fastest access speed among the first and second memory groups 60 and 70 having different access speeds managed by the memory control device 42 is used as the image processing means having the slowest image processing speed. By allocating, the processing speed of the entire image processing apparatus can be increased.
[0025]
Further, a more specific example of the third embodiment of the present invention shown in FIG. 3 will be described with reference to FIGS.
FIG. 8 is a block diagram of the image processing apparatus 1 ″, which differs from FIG. 7 only in the memory control unit 43. This memory control unit 43 corresponds to the work area management unit 22 in FIG. The one memory group 60 and the second memory group 70 by the DDR 266 correspond to the work area 30 in FIG.
[0026]
FIG. 9 shows an example of a processing mode of image processing performed by each of the image processing units 11 to 13 of the image processing apparatus and an example of a set value of a register set in the memory control device 43. According to this processing mode, the image scaling process requires two SDRAM 133 line memories, the filtering process requires three SDRAM 133 line memories, and the image compression process requires eight DDR 266 line memories. Information on the number and type of line memories required is set as a register setting value. The register setting value is set as a two-digit number, and the first digit indicates the type of line memory, “0” for SDRAM 133 and “1” for DDR266, and the second digit is used. This indicates the number of line memories to be used.
[0027]
For example, the first digit “0” of the register setting value “20” for the image scaling process indicates that the SDRAM 133 is used, and the second digit “2” indicates that there are two line memories.
By setting this register setting value as memory control information from the outside to the memory control device 43 shown in FIG. 8, the memory control device 43 sends the first image processing means 11 to 13 to the image processing means 11 to 13 in accordance with the register setting value. A specified number of line memories of a specified type of memory group in the memory group (SDRAM 133) 60 and the second memory group (DDR 266) 70 are allocated and connected.
[0028]
As described above, according to this embodiment, when the memory control device 43 inputs the memory control information from outside the image processing device 1 ″, each of the image processing units 11 to 13 allocates the line memory required for the image processing. Therefore, the memory control device 43 can calculate a necessary memory amount based on the image processing information from each of the image processing units 11 to 13 as in the example shown in FIG. There is no need to determine the processing speed, and the internal configuration or function can be simplified.
Further, since the memory control information can be freely set from the outside, it is not necessary to change the memory control device 43 even if the content of the image processing performed by each of the image processing means 11 to 13 of the image processing device changes.
[0029]
【The invention's effect】
As described above, according to the present invention, the use efficiency of the work area (memory or memory area) in the image processing apparatus is increased, the memory capacity (the number of memories) required for the entire apparatus is reduced, and the cost is reduced. be able to.
Further, it is also possible to increase the speed of image processing by the image processing apparatus without increasing the cost much.
[Brief description of the drawings]
FIG. 1 is a block diagram illustrating a basic configuration of a first embodiment of an image processing apparatus according to the present invention.
FIG. 2 is a block diagram showing a basic configuration of a second embodiment of the image processing apparatus according to the present invention.
FIG. 3 is a block diagram showing a basic configuration of a third embodiment of the image processing apparatus according to the present invention.
FIG. 4 is a block diagram illustrating a more specific configuration example of the image processing apparatus illustrated in FIG. 1;
FIG. 5 is a block diagram showing the contents of image processing and the configuration of a memory group of the image processing apparatus shown in FIG. 4;
FIG. 6 is a block diagram illustrating a partially modified example of the image processing apparatus illustrated in FIG. 4;
FIG. 7 is a block diagram illustrating a more specific configuration example of the image processing apparatus illustrated in FIG. 2;
FIG. 8 is a block diagram illustrating a more specific configuration example of the image processing apparatus illustrated in FIG. 3;
9 is a diagram illustrating an example of image processing performed by each image processing unit of the image processing apparatus illustrated in FIG. 8, a processing mode thereof, and a register setting value that is memory control information.
FIG. 10 is a block diagram illustrating a configuration example of a conventional image processing apparatus.
11 is a block diagram showing a more specific configuration example of the image processing device shown in FIG.
12 is a diagram illustrating an example of image processing performed by each image processing unit of the image processing apparatus illustrated in FIG. 10 and a processing mode thereof.
[Explanation of symbols]
1, 1 ', 1 ": image processing apparatus 11: first image processing means 12: second image processing means 13: third image processing means 20 to 22: work area management means 30: work area 30A: first work area 30B: second work area 40 to 43: memory control device 50: memory group 51 to 63, 65 to 69, 71 to 78: line memory 60: first memory group (SDRAM 133)
70: Second memory group (DDR266)

Claims (3)

An image processing apparatus that performs image processing by a combination of a plurality of image processing units that perform different image processing on input image data,
Providing a work area management means for collectively managing the work areas required by the plurality of image processing means,
The image processing apparatus, wherein the work area management means has a function of allocating a required work area to each of the image processing means in accordance with the content to be processed by each of the plurality of image processing means. The image processing apparatus according to claim 1,
In a work area managed by the work area management means, two or more work areas having different access speeds are provided,
The work area management means allocates a work area having the fastest access speed among the two or more types of work areas to an image processing means which performs processing with the slowest processing speed among the plurality of image processing means. An image processing device having a function. An image processing apparatus that performs image processing by a combination of a plurality of image processing units that perform different image processing on input image data,
Providing a work area management means for collectively managing the work areas required by the plurality of image processing means,
The image processing apparatus according to claim 1, wherein the work area management means has a function of allocating a required work area to each of the plurality of image processing means according to work area control information provided from outside.

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