JP2002024157A - Method and device for processing dma - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide DMA transfer setting enriched in kinds with more less memory consumption. SOLUTION: A plurality of mask data 500 and 501 for DMA transfer channel selection for selecting the use/no use of respective DMA transfer channels 501, 502, 504, 505 and 513 are provided corresponding to DMA transfer channel groups 50, 51 and 52, the mask data 500 and 501 for DMA transfer channel group selection for selecting the use/no use of respective plural DMA transfer channel groups are set corresponding to respective plural kinds of DMA transfer requests, and the mask data for DMA transfer channel selection are set to a DMA transfer channel mask register 53 corresponding to respective plural kinds of DMA transfer requests. According to the mask data for DMA transfer channel group selection and the mask data 500 and 501 for DMA transfer channel selection, a transfer channel to perform DMA transfer processing is selected.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a DMA for directly transferring data between memories, between external devices and between memories, and between external devices and external devices without using a CPU or the like.
(Direct Memory Access) It relates to a processing device.

[0002]

2. Description of the Related Art In general, a DMA processor includes a transfer control register, a transfer enable register for storing transfer permission information, a transfer source address register for storing a transfer source address, and a transfer destination address register for storing a transfer destination address. And a transfer word number register storing the number of transfer words, a DMA transfer channel is defined as one transfer unit.
And DMA from multiple external devices and software
When data transfer is requested, the transfer enable register is set to be enabled, and a request for surrender of each data bus is made to the CPU so as to process DMA data transfer.

The transfer control register is a register provided for the following purpose. That is, the size of data to be transferred at one time (8 bits or 16 bits, etc.), the transfer form when a plurality of DMA transfers operate simultaneously (single word transfer or continuous transfer), whether or not to generate an interrupt after the transfer ends Set fine control.

When a plurality of DMA transfer requests occur simultaneously, a DMA transfer request priority determination circuit sets a transfer enable register of a DMA transfer channel corresponding to the highest priority DMA transfer request to be enabled,
The DMA processing device replaces the CPU with the data stored in the address position stored in the transfer source address register, and transfers the data stored in the address position stored in the transfer destination address register to the number of words stored in the transfer word number register. Only DMA transfer was performed. For example, JP-A-4-205
See 640 publication.

In the conventional DMA transfer, (1) a large number of DMA transfer channel data composed of transfer control data, transfer source address data, transfer destination address data, and transfer word number data are arranged in a memory, and a corresponding DMA transfer is performed. If a transfer request occurs and the priority of the DMA transfer request is the highest, the DMA transfer channel data is read from a memory previously allocated to the DMA transfer request,
MA transfer was being performed. The transfer control data is the same data as the data stored in the transfer control register described above, and the memory plays the same role as the transfer control register.

In the conventional DMA transfer, (2) a DMA composed of a plurality of DMA transfer channel data
A plurality of transfer channel group data are arranged in the memory, and a mask register for selecting the DMA transfer channel group data is set so that only the DMA transfer channel group corresponding to the DMA transfer request is selected. The DMA transfer channel data of the channel group is read from the memory in the order in which it is arranged on the memory, and a plurality of sets of DMA transfer are performed in response to one DMA transfer request.

The DMA transfer channel is defined by DMA transfer channel data including transfer control data, transfer source address data, transfer destination address data, and transfer word number data.
Alternatively, it comprises a plurality of DMA transfer channels. The DMA transfer channel group data includes one or a plurality of sets of DMA transfer channel data that respectively define one or a plurality of DMA transfer channels constituting the DMA transfer channel group.

[0008]

However, in the configuration such as the above (1), the D corresponding to the DMA transfer request
Since the memory address for storing the MA transfer channel data is fixed, the memory area for storing the DMA transfer channel data is occupied even though all DMA transfer requests are not used, and the memory use efficiency is deteriorated. There was a problem that.

Further, the DMA corresponding to the DMA transfer request
Since only one transfer channel can be set, when performing a plurality of DMA transfers in response to a DMA transfer request, there is a problem that a DMA transfer request must be generated a plurality of times while rewriting the DMA transfer channel data. Was.

[0010] In the above configuration (2), a plurality of DMA transfers can be performed by one DMA transfer request. However, the number of DMA transfer channel data in the DMA transfer channel group data corresponding to the DMA transfer request is limited. Are uniformly fixed, even when performing only one DMA transfer with a plurality of DMA transfer requests, the DMA transfer channel group data in which one set of DMA transfer channel data corresponding to the number of DMA transfer requests is set is stored in the memory. When the number of DMA transfer channel data in the DMA transfer channel group data corresponding to the DMA transfer request is large, the memory area for storing the DMA transfer channel group data is occupied, and the memory use efficiency is reduced. It had the problem of getting worse.

An example of the conventional DMA processor (2) will be described with reference to FIG.

For the sake of simplicity, the DMA processing apparatus includes a first DMA transfer channel group 101, a second DMA transfer channel group 102, and a third DM transfer channel group.
It is assumed that there are three A transfer channel groups 103.

First DMA transfer channel group 10
The first, second DMA transfer channel group 102, and third DMA transfer channel group 103 are sequentially processed.

Each DMA transfer channel group 101, 1
02 and 103 can store a maximum of four DMA transfer channels, respectively. In this example, the first DM
The A transfer channel group 101 includes a DMA transfer channel (A) 1011 and a DMA transfer channel (B) 1012.
And the second DMA transfer channel group 102 includes DMA transfer channels (B) 1022 and DM
A transfer channel (C) 1023 and the third
The DMA transfer channel group 103 includes a DMA transfer channel (D) 1034 and a DMA transfer channel (E) 1
Let us consider a case where there are two such as 035.

Incidentally, DMA transfer channel data (B) 1
012 and the DMA transfer channel data (B) 1022 have the same transfer contents.

DMA transfer channel groups 101 and 10
2 and 103 and DMA transfer channels 1011 and 101
2, 1022, 1023, 1034, and 1035 are arranged on the memory. That is, the data is stored as DMA transfer channel group data and DMA transfer channel data on the memory.

When it is desired to process the two DMA transfer channels (A) 1011 and the DMA transfer channel (B) 1012 existing in the first DMA transfer channel group 101 by the first DMA transfer request 104, the The transfer channel group selection mask register 107 has the first
Only the bits corresponding to the DMA transfer channel group 101 are enabled. Thereby, the first D
DMA transfer channels existing in the MA transfer channel group 101 are DMA transfer channels (A) 1011 and DMA
The processing is performed in the order of the transfer channel (B) 1012 and the memory, and the DMA transfer of a plurality of channels is performed for one DMA transfer request 104.

Similarly, in response to the second DMA transfer request 105, the two DMA transfer channels (B) 1022 existing in the second DMA transfer channel
When you want to process the A transfer channel (C) 1023,
DMA transfer channel group selection mask register 10
7, only the bits corresponding to the second DMA transfer channel group 102 are enabled. by this,
D existing in the second DMA transfer channel group 102
The MA transfer channel is the DMA transfer channel (B) 102
2. Processing is performed in the order set in the DMA and the DMA transfer channel (C) 1023, and one DMA transfer request 105
, A plurality of channels of DMA transfer are performed.

Further, in response to the third DMA transfer request 106, a DMA transfer channel (A) 1011, a DMA transfer channel (B) 1012, a DMA transfer channel (D) 1034, and a DMA transfer channel (E) 1035.
When the first DMA transfer channel group 101 and the third DMA transfer channel group 1 are stored in the DMA transfer channel group selection mask register 107,
03 is enabled. As a result, first, the DM existing in the first DMA transfer channel group 101
A transfer channel is a DMA transfer channel (A) 1011;
Processed in the order of the DMA transfer channel (B) 1012,
Next, the DMA transfer channel existing in the third DMA transfer channel group 103 is the DMA transfer channel (D) 1
034, one DMA transfer request 1 is processed in the order set in the DMA transfer channel (E) 1035 and the memory.
06, DMA transfer of a plurality of channels is performed.

In the above-described DMA processing apparatus, a DMA transfer channel for performing a DMA transfer can be selected by setting the DMA transfer channel group selection mask register 107. However, a plurality of DMA transfer channels existing in a certain DMA transfer channel group can be selected. DMA of one of the DMA channels
It is not possible to select and process only the transfer channel.
For this reason, a DMA transfer channel group consisting of only the DMA transfer channels to be processed must be separately prepared on the memory, and there is a problem that the memory area used in the DMA processing device becomes large.

The DMA transfer channel (B) 1012 and the DMA transfer channel (B) 1012 in the above-described DMA transfer example.
Even when a plurality of DMA transfer channel groups have a common DMA transfer channel as shown in FIG. 22, the DMA transfer channel cannot be shared between the DMA transfer channel groups. Had the problem that

Further, when the maximum value of the number of DMA transfer channels that can exist in one DMA transfer channel group is reduced, the selection of the DMA transfer channel becomes easy.
Since the number of bits of the mask register for selecting the MA transfer channel group is required by the number of DMA transfer channel groups, the number of hardware increases, and conversely, the number of DMA transfer channels that can exist in one DMA transfer channel group Is larger, the mask register for selecting the DMA transfer channel group can be smaller,
It becomes difficult to make fine selection settings of the DMA transfer channel, and moreover, the DMA that can exist in the DMA transfer channel group
If the DMA transfer channels up to the maximum value of the number of transfer channels are hardly used, there is a problem that the use efficiency of the memory is very poor.

Accordingly, it is an object of the present invention to provide a DMA processing method and a DMA processing apparatus capable of realizing a wide variety of DMA transfer settings with less memory consumption.

[0024]

SUMMARY OF THE INVENTION A DMA processing method according to the present invention comprises the steps of:
A DMA transfer channel defined by a set of DMA transfer channel data including MA transfer source address data and DMA transfer destination address data is used as a DMA transfer unit,
A DMA processing method for performing A transfer, wherein one or more DMAs forming one DMA transfer channel group
One or more sets of DMs each defining a transfer channel
DMA transfer channel group data comprising A transfer channel data and DMA transfer channel selection mask data for selecting use / non-use of each of one or a plurality of DMA transfer channels is converted into a plurality of DMA transfer channel groups. A plurality of DMA transfer channel groups are set correspondingly, and a plurality of DMA transfer channel group selection mask data for selecting use / non-use of each of the plurality of DMA transfer channel groups are set corresponding to a plurality of types of DMA transfer requests. DM for each type of DMA transfer request
A transfer channel selection mask data is set, and DMAs set corresponding to a plurality of types of DMA transfer requests are set.
According to the transfer channel group selection mask data, use / non-use of each of the plurality of DMA transfer channel groups is selected, and each of the selected DMA transfer channel groups is set corresponding to a plurality of types of DMA transfer requests. Use / non-use of each of the plurality of DMA transfer channels is selected according to the DMA transfer channel selection mask data, and D of the DMA transfer channel whose use is selected for each of the selected DMA transfer channel groups.
MA transfer processing is performed.

According to this method, mask data for selecting a DMA transfer channel group for selecting use / non-use of each of the plurality of DMA transfer channel groups is set in response to a plurality of types of DMA transfer requests, respectively.
D for selecting use / non-use of each of a plurality of DMA transfer channels in response to a plurality of types of DMA transfer requests, respectively
By setting the MA transfer channel selection mask data, not only a plurality of DMA transfer processes can be performed for one DMA transfer request, but also a plurality of DMA transfer channels can be shared among the plurality of DMA transfer requests. Various types of DMA transfer settings can be realized with less memory consumption.

According to a second aspect of the present invention, in the DMA processing method of the first aspect, data indicating that DMA transfer channel data is set is transmitted to a plurality of DMs.
A Set as channel group confirmation data for each transfer channel group,
D is the logical product of the transfer channel group selection mask data
It is characterized in that an MA transfer channel group is selected.

According to this method, it is possible to prevent a DMA transfer channel group in which no DMA transfer channel data exists from being selected, and to prevent an erroneous memory access due to unset DMA transfer channel data.

The DMA processing device of the present invention includes a DMA transfer channel defined by a set of DMA transfer channel data including DMA transfer control data, DMA transfer word number data, DMA transfer source address data, and DMA transfer destination address data. DM that performs DMA transfer as a DMA transfer unit
A processing apparatus, wherein one or a plurality of sets of DMA transfer channel data respectively defining one or a plurality of DMA transfer channels constituting one DMA transfer channel group, and each of the one or a plurality of DMA transfer channels DMA transfer channel group data composed of DMA transfer channel selection mask data for selecting use / non-use of a DMA transfer channel group is stored in correspondence with a plurality of DMA transfer channel groups, and each of the DMA transfer channel group data corresponds to a plurality of types of DMA transfer requests. And a DMA transfer channel group set corresponding to a plurality of types of DMA transfer requests to select use / non-use of a plurality of DMA transfer channel groups. DMA transfer channel group mask level for storing selection mask data And selecting whether to use each of the plurality of DMA transfer channel groups according to the DMA transfer channel group selection mask data set corresponding to each of the plurality of types of DMA transfer requests. A plurality of DMAs are transferred in accordance with DMA transfer channel selection mask data set corresponding to a plurality of types of DMA transfer requests for each transfer channel group.
A DMA transfer block for selecting use / non-use of each of the transfer channels and executing a DMA transfer process of the DMA transfer channel whose use is selected for each of the DMA transfer channel groups whose use is selected.

According to this configuration, the DMA transfer channel group mask register for storing the DMA transfer channel group selection mask data for selecting use / non-use of each of the plurality of DMA transfer channel groups is provided, and the memory is provided. The DMA transfer channel group data to be written includes DMA transfer channel selection mask data for selecting use / non-use of each of the plurality of DMA transfer channels, and a plurality of DMA transfer blocks are provided in accordance with the DMA transfer channel group selection mask data. D
Use / non-use of each of the MA transfer channel groups is selected, and use / non-use of each of the plurality of DMA transfer channels is selected according to the DMA transfer channel selection mask data for each of the DMA transfer channel groups whose use is selected. The DMA of the DMA transfer channel whose use is selected for each of the DMA transfer channel groups whose use is selected
Since the transfer process is executed, not only a plurality of DMA transfer processes can be performed for one DMA transfer request, but also a plurality of D
Since the MA transfer channel data can be shared among a plurality of DMA transfer requests, a wide variety of DMA transfer settings can be realized with less memory consumption.

According to a fourth aspect of the present invention, in the DMA processing apparatus of the third aspect, data indicating that the DMA transfer channel data is stored in the memory for each of the plurality of DMA transfer channel groups is confirmed by the channel group. A DMA data confirmation register for storing data is provided, and the DMA transfer block selects a DMA transfer channel group by the logical product of the channel group confirmation data and the DMA transfer channel group selection mask data.

According to this configuration, it is possible to prevent a DMA transfer channel group in which no DMA transfer channel data exists from being selected, and to prevent an erroneous memory access due to unset DMA transfer channel data.

[0032]

Embodiments of the present invention will be described below with reference to the drawings.

FIG. 1 shows data stored in a memory used in a DMA processor which has four DMA transfer channel groups, uses two DMA transfer channel groups, and performs five types of DMA transfers. It is a schematic diagram which shows an example of.

In FIG. 1, DMA transfer channel group data 20, 21 and 22 stored in the memory are arranged in a continuous area on the memory. 200,
210, 220 are each used / used of the DMA transfer channel.
DMA transfer channel selection mask data for selecting non-use. 2001, 2002, 2003, 2004
Reference numeral 2101 denotes DMA transfer channel data corresponding to a DMA transfer channel indicating a DMA transfer unit. 200
11, 20021, 20031, 20041, 2101
Reference numeral 1 denotes transfer source address data indicating a data transfer source when performing a DMA transfer. 20012, 2202, 2
0032, 20042, and 21012 are transfer destination address data indicating the data transfer destination when performing the DMA transfer. Although not shown, the DMA transfer control data and the DM
A transfer word number data is also stored in each DMA transfer channel data 200.
1, 2002, 2003, 2004, and 2101.

Here, the meaning of arranging the DMA transfer channel group data in a continuous area on the memory will be described. Arranging the DMA transfer channel group data in a continuous area on the memory means that if only the address of the first DMA transfer channel group is managed, the subsequent DMA transfer channel group can be used.
Since the address of the transfer channel group data can be derived from the size of the transfer channel group data by calculation,
This means that there is no need to manage useless data.

On the other hand, if they are not arranged in a continuous area, it is necessary to manage the addresses of all DMA transfer channel data, which requires many registers and memories. Therefore, they are arranged in the continuous area as described above.

FIG. 2 is a block diagram showing an example of the configuration of the DMA processing device. In FIG. 2, reference numeral 300 denotes a DMA transfer control block.

Reference numeral 301 denotes a DMA transfer channel group head address register for storing the head address of the DMA transfer channel group data on the memory.

Reference numeral 302 denotes D on the memory during DMA transfer processing.
This is a DMA transfer channel temporary register that stores MA transfer channel data.

Numeral 303 denotes a DMA data confirmation register for storing data indicating that DMA transfer channel data is stored in the memory as channel group confirmation data for each DMA transfer channel group.

A DMA transfer channel 304 stores DMA transfer channel group selection mask data for selecting use / non-use of each of a plurality of DMA transfer channel groups set corresponding to a plurality of types of DMA transfer requests. This is a group mask register.

Reference numeral 305 denotes D for storing DMA transfer permission information.
This is an MA transfer enable register.

Reference numeral 306 denotes a control line. 307 is a data bus. 308 is an address bus.

Although not shown in FIG. 2, the number of words to be transferred at one time, a transfer form indicating whether to perform continuous transfer or divided transfer when a plurality of DMA transfers are performed simultaneously, and whether an interrupt should be generated after the transfer is completed The information processing apparatus includes a DMA transfer control register for performing detailed settings of DMA transfer such as interrupt control indicating whether the DMA transfer is performed.

Although not shown in FIG. 2, one or a plurality of DMAs forming one DMA transfer channel group are stored in the memory included in the information processing apparatus.
One or more sets of DMs each defining a transfer channel
DMA transfer channel group data composed of A transfer channel data and DMA transfer channel selection mask data for selecting use / non-use of each of one or a plurality of DMA transfer channels is divided into a plurality of DMA transfer channel groups. DMA transfer channel selection mask data is set in correspondence with each of a plurality of types of DMA transfer requests and becomes a component of the DMA processor.
The DMA transfer channel data includes DMA transfer control data, DMA transfer word number data, DMA transfer source address data, and DMA transfer destination address data.
The MA transfer channel is one DMA transfer unit.

The DMA transfer block 300 described above
Selects the use / non-use of each of the plurality of DMA transfer channel groups according to the DMA transfer channel group selection mask data set respectively corresponding to the plurality of types of DMA transfer requests, and selects the DMA transfer to be used. DMA transfer in which use of each of the plurality of DMA transfer channels is selected according to DMA transfer channel selection mask data set corresponding to each of a plurality of types of DMA transfer requests for each channel group, and the DMA transfer whose use is selected. The DMA transfer process of the DMA transfer channel whose use is selected for each channel group is executed.

FIG. 3 is a block diagram showing an example of an information processing apparatus comprising a DMA processing device, a CPU, two external devices, and a memory. In FIG. 4, 400 is C
PU. Reference numeral 401 denotes an external device. 402 is a memory. 403 is an external device 401-memory 40
A DMA processing device that controls data transfer in place of the CPU 400 when data transfer between the two is requested. 404
Is an address bus. 405 is a data bus.

Reference numeral 406 denotes a CPU from the DMA processing device 403
400 is a data transfer request signal. Reference numeral 407 denotes a data transfer request signal from the external device 401 to the DMA processing device 403. Reference numeral 408 denotes a data transfer acknowledge signal from the CPU 400 to the DMA processing device 403. 4
09 is a data transfer acknowledge signal from the DMA processing device 403 to the external device 401. The memory 402 has DMA transfer channel group data and transfer data.

FIG. 4 is a schematic diagram showing an example in which five types of DMA transfer are sequentially executed by a certain software in the embodiment of the present invention. In FIG. 4, reference numeral 50 denotes a first DMA transfer channel group on the memory, 51 denotes a second DMA transfer channel group on the memory, and 52 denotes a third DMA transfer channel group on the memory. It has DMA transfer channel group data 20, 21, and 22. 53 is DMA
This is a transfer channel group mask register.

Reference numeral 500 denotes mask data for selecting a first DMA transfer channel, and reference numeral 510 denotes mask data for selecting a second DMA transfer channel. These correspond to the mask data 200 and 210 for selecting a DMA transfer channel in FIG.

Reference numeral 501 denotes the external device 401 and the memory 40
A first DMA transfer channel (A) 502 for performing DMA data transfer between the two, an external device 401 and a memory 402
A second DMA transfer channel (B) 513 for transferring DMA data between the external device 401 and the memory 402; a third DMA transfer channel (C) for transferring DMA data between the external device 401 and the memory 402; A fourth DMA transfer channel (D) for performing data transfer, 505 is a fifth DMA transfer channel (E) for performing DMA data transfer between the memory 402 and the external device 401. These are the DMA transfer channel data 2001 and 200 in FIG.
2,2101,2003,2004.

FIG. 4 shows a case where the above-described five types of data transfer are executed by a certain software as follows.

That is, first, the first DMA transfer request 5
06, the first DMA transfer channel (A) 501
DMA transfer by the second DMA transfer channel (B) 5
The DMA transfer is performed sequentially, such as the DMA transfer by 02.

Next, in response to the second DMA transfer request 507, D by the second DMA transfer channel (B) 502
DMA transfer is performed sequentially, such as MA transfer and DMA transfer using the third DMA transfer channel (C) 513.

Next, in response to the third DMA transfer request 508, D by the first DMA transfer channel (A) 501 is set.
MA transfer, DMA transfer by the second DMA transfer channel (B) 502, fourth DMA transfer channel (D) 504
DMA transfer by the fifth DMA transfer channel (E) 5
The DMA transfer is performed sequentially, such as the DMA transfer according to E.05.

The operation of the above-configured DMA processing device will be described below with reference to FIGS. 1, 2, 3 and 4.

To simplify the description, the first DMA transfer request 506 and the second DMA transfer request 507 do not occur at the same time, and the first DMA transfer request 506 and the third DMA transfer request 506 do not occur simultaneously.
A transfer request 508 does not occur at the same time, and the second DM
It is assumed that the A transfer request 507 and the third DMA transfer request 508 do not occur at the same time. The number of transfer blocks is the same, and it is assumed that the DMA processor 403 has a transfer function in which the number of transfer blocks is fixed in advance. In addition,
The number of transfer blocks is a unit of DMA transfer, such as 8 bits (1 byte), 16 bits (1 word), and the like.

(1) First DMA transfer channel (A)
501, second DMA transfer channel (B) 502, third
Each DMA transfer channel (C) 513, the fourth DMA transfer channel (D) 504, and the fifth DMA transfer channel (E) 505 perform DMA transfer.
MA transfer channel data 2001, 2002, 200
3, 2004 and 2101 are set.

At the same time, each DMA transfer channel group data 20, 21, 22 in the DMA data confirmation register 303
In the (DMA transfer channel groups 50, 51, 52), an enable flag is set for bits corresponding to the DMA transfer channel group data 20, 21 in which the DMA transfer channel data is set.

Each DMA transfer channel selection mask data 200 for selecting use / non-use of the DMA transfer channel,
Disable is set to 210 and 220, and the DMA transfer channel group head address register 301 is set to
The start address of the DMA transfer channel group data 20 is set, and the DMA transfer channel group mask register 304 stores all DMA transfer channel group data 2.
Disable is set for 0, 21 and 22.

The start address of the DMA transfer channel group data 20 set in the DMA transfer channel group start address register 301 is used as follows. That is, the DMA transfer channel group head address register 301 stores the D
The head address of the MA transfer channel group data is stored. Based on this address, the storage address of the subsequent DMA transfer channel group data is calculated to access the data.

(2) When the first DMA transfer request 506 occurs, the DMA transfer channel group mask register 304 (the DMA transfer channel group mask register 5
3) As DMA transfer channel group selection mask data, DMA transfer channel group data 20 (D
The enable is set only for the MA transfer channel group data 50), and the DMA transfer channel selection mask data 200 (DMA
The bit pattern of the transfer channel selection mask data 500) is transferred to the DMA transfer channel data 2001, 2002.
(DMA transfer channel data 501 and 502) are enabled, and the DMA transfer enable register 305 is enabled.

When the DMA transfer enable register 305 is set to be enabled, the DMA control block 300
Is the value set in the DMA data confirmation register 303,
The logical AND with the set value of the A transfer channel group mask register 304 is calculated to select the DMA transfer channel group data 20.

Next, the DMA transfer channel data 2001 and 2002 selected and set by the mask data 200 of the selected DMA transfer channel group data 20 are stored in the DMA transfer channel temporary register 302 in the order of arrangement on the memory, and are sequentially stored in the DMA. Perform transfer processing.

The DM for the first DMA transfer request 506
When the A transfer processing is completed, the DMA control block 300
Sets the DMA transfer enable register 305 to disable, clears the set value of the DMA transfer channel group mask register 304, invalidates all DMA transfer channel group data, and waits for the next DMA transfer request.

Note that invalidating the DMA transfer channel group data means invalidating the DMA transfer for which processing has been completed. If the DMA transfer channel group mask register 304 is not cleared, the same DMA transfer will be performed many times.

(3) When the second DMA transfer request 507 occurs, the DMA transfer channel group mask register 304 (the DMA transfer channel group mask register 5
In 3), only the DMA transfer channel group data 20 and 21 (DMA transfer channel groups 50 and 51) are enabled as the DMA transfer channel group selection mask data, and the DMA transfer channel group data 20 is used to select the DMA transfer channel. Mask data 20
0 (DMA transfer channel selection mask data 500) bit pattern
(DMA transfer channel 502) is enabled,
The bit pattern of the DMA transfer channel selection mask data 210 (DMA transfer channel selection mask data 510) of the DMA transfer channel group data 21
A transfer channel data 2101 (DMA transfer channel 5
13), enable is set, and the DMA transfer enable register 305 is set to be enabled.

When the DMA transfer enable register 305 is set to be enabled, the DMA control block 300
Is the value set in the DMA data confirmation register 303,
The logical AND with the set value of the A transfer channel group mask register 304 is calculated to select the DMA transfer channel group data 20 and 21.

Next, the DMA transfer channel data 2002 selected and set by the DMA transfer channel selection mask data 200 of the selected DMA transfer channel group data 20 are stored in the DMA transfer channel temporary register 302 in the order of arrangement on the memory. , And sequentially perform a DMA transfer process.

Subsequently, the DMA transfer channel data 2101 selected and set by the mask data 210 of the selected DMA transfer channel group data 21 is stored in the DMA transfer channel temporary register 302, and DMA transfer processing is performed.

DM for second DMA transfer request 507
When the A transfer processing is completed, the DMA control block 300
Sets the DMA transfer enable register 305 to disable, clears the set value of the DMA transfer channel group mask register 304, invalidates all DMA transfer channel group data, and waits for the next DMA transfer request.

(4) When the third DMA transfer request 508 occurs, the DMA transfer channel group mask register 304 (the DMA transfer channel group mask register 5
3) As DMA transfer channel group selection mask data, DMA transfer channel group data 20 (D
Enable is set only for the MA transfer channel group 50) and the DMA of the DMA transfer channel group data 20 is set.
The bit pattern of the transfer channel selection mask data 200 (the DMA transfer channel selection mask data 500) is changed to the DMA transfer channel data 2001, 2002, 2
003, 2004 (DMA transfer channels 501, 50)
2, 504, 505) and the DMA transfer enable register 305 is enabled.

When the DMA transfer enable register 305 is set to be enabled, the DMA control block 300
Is the value set in the DMA data confirmation register 303,
The logical AND with the set value of the A transfer channel group mask register 304 is calculated to select the DMA transfer channel group data 20.

Next, the DMA transfer channel data 2001, 2002, 20 selected and set by the mask data 200 of the selected DMA transfer channel group data 20.
03, 2004 are stored in the DMA transfer channel temporary register 302 in the order of arrangement on the memory, and DMA transfer processing is sequentially performed.

DM for third DMA transfer request 508
When the A transfer processing is completed, the DMA control block 300
Sets the DMA transfer enable register 305 to disable, clears the set value of the DMA transfer channel group mask register 304, invalidates all DMA transfer channel group data, and waits for the next DMA transfer request.

In the operation example of the above-described DMA processing apparatus, DMA data transfer can be performed using only two DMA transfer channel groups for three DMA transfer requests.
It is possible to reduce the memory size consumed by the MA processing device.

As described above, according to the embodiment of the present invention, the DMA transfer channel group data 20, 21, 22
2 and DMA transfer channel selection mask data 200 and 2 for masking DMA transfer channel data in the DMA transfer channel group data placed on the memory.
Provision of the DMA transfer devices 10 and 220 allows not only a plurality of DMA transfer processes for one DMA transfer request but also a plurality of DMA transfer channel data to be shared among the plurality of DMA transfer requests. Can reduce the memory area used.

Here, the DMA processing method will be described. In this DMA processing method, first, one or a plurality of sets of DMA transfer channel data respectively defining one or a plurality of DMA transfer channels forming one DMA transfer channel group, and one or a plurality of DMA transfer channels are defined. A plurality of DMA transfer channel group data, each of which includes a DMA transfer channel selection mask data for selecting use / non-use, is set in correspondence with a plurality of DMA transfer channel groups.

Next, the DMA transfer channel group selection mask data for selecting use / non-use of each of the plurality of DMA transfer channel groups is set in response to each of the plurality of types of DMA transfer requests. DMA transfer channel selection mask data is set corresponding to each of the DMA transfer requests.

Next, use / non-use of each of the plurality of DMA transfer channel groups is selected according to the DMA transfer channel group selection mask data set corresponding to each of a plurality of types of DMA transfer requests, and use is selected. Multiple types of DMAs for each set of DMA transfer channel groups
The use / non-use of each of the plurality of DMA transfer channels is selected according to the DMA transfer channel selection mask data set corresponding to each transfer request, and the use is selected for each of the DMA transfer channel groups whose use is selected. Execute the DMA transfer process of the selected DMA transfer channel.

[0081]

As described above, according to the DMA processing method of the first aspect of the present invention, each of a plurality of DMA transfer channel groups is used / not used corresponding to a plurality of types of DMA transfer requests. Is set, and a plurality of DMAs corresponding to a plurality of types of DMA transfer requests are set.
By setting DMA transfer channel selection mask data for selecting use / non-use of each transfer channel,
Since not only a plurality of DMA transfer processes can be performed for one DMA transfer request, but also a plurality of DMA transfer channels can be shared among the plurality of DMA transfer requests, a wide variety of types of DM transfer can be performed.
The A transfer setting can be realized with less memory consumption.

Further, according to the DMA processing method of the second aspect of the present invention, it is possible to prevent a DMA transfer channel group having no DMA transfer channel data from being selected, and it is possible to prevent the DMA transfer channel data from being set. Erroneous memory access can be prevented.

According to the DMA processing device of the present invention, the DMA transfer channel group selection mask data for selecting use / non-use of each of the plurality of DMA transfer channel groups is stored. A DMA transfer channel group mask register is provided, and the DMA transfer channel group data to be written into the memory includes a DMA transfer channel selection mask data for selecting use / non-use of each of the plurality of DMA transfer channels. Selects use / non-use of each of the plurality of DMA transfer channel groups in accordance with the DMA transfer channel group selection mask data, and selects a plurality of DMA transfer channel groups in accordance with the DMA transfer channel selection mask data for each of the DMA transfer channel groups selected for use. DMA transfer channel data Since each use / non-use is selected, and the DMA transfer processing of the DMA transfer channel whose use is selected is executed for each of the DMA transfer channel groups whose use is selected, a plurality of DMAs can be assigned to one DMA transfer request. In addition to performing transfer processing, a plurality of DMA transfer channel data can be shared among a plurality of DMA transfer requests, so that a wide variety of DMA transfer settings can be realized with less memory consumption.

Further, according to the DMA processing device of the fourth aspect of the present invention, it is possible to prevent a DMA transfer channel group having no DMA transfer channel data from being selected, and it is possible to prevent the DMA transfer channel data from being set. Erroneous memory access can be prevented.

[Brief description of the drawings]

FIG. 1 is a schematic diagram showing configuration data in a memory used in a DMA processing device according to an embodiment of the present invention.

FIG. 2 is a block diagram illustrating a configuration of a DMA processing device according to the embodiment of the present invention.

FIG. 3 is a block diagram illustrating a configuration of an information processing apparatus according to an embodiment of the present invention.

FIG. 4 is a schematic diagram showing an example of setting of a DMA processing device according to the present invention.

FIG. 5 is a schematic diagram showing an operation example of a conventional DMA processing device.

[Explanation of symbols]

101, 102, 103 DMA transfer channel groups 1011, 1012, 1022, 1023, 1034
1035 DMA transfer channels 104, 105, 106 DMA transfer request 107 DMA transfer channel group selection mask register 20, 21, 22 DMA transfer channel group data 200, 210, 220 Mask data 2001, 2002, 2003, 2004, 2101
DMA transfer channel data 2011, 2001, 20031, 20041, 2
1011 Transfer source address data 2012, 2202, 20032, 20042, 2
1012 Transfer source address data 300 DMA transfer control block 301 DMA transfer channel group head address register 302 DMA transfer channel temporary register 303 DMA transfer data confirmation register 304 DMA transfer channel group mask register 305 DMA transfer enable register 306 Control line 307 Data bus 308 Address Bus 400 CPU 401 External device 402 Memory 403 DMA processor 404 Address bus 405 Data bus 406, 407 Data transfer request signal 408, 409 Data transfer acknowledge signal 501 First DMA transfer channel (A) 502 Second DMA transfer channel ( B) 513 Third DMA transfer channel (C) 504 Fourth DMA transfer channel (D) 505 Fifth D A transfer channel (E) 506 first DMA transfer request 507 second DMA transfer request 508 third DMA transfer request

Claims (4)

[Claims] 1. A DMA transfer channel defined by a set of DMA transfer channel data including DMA transfer control data, DMA transfer word number data, DMA transfer source address data, and DMA transfer destination address data, as a DMA transfer unit. A DMA processing method for performing a transfer, comprising: one or a plurality of sets of DMA transfer channel data respectively defining one or a plurality of DMA transfer channels constituting one DMA transfer channel group; A plurality of DMA transfer channel group data, each of which is composed of a DMA transfer channel selection mask data for selecting use / non-use of a transfer channel, are set corresponding to the plurality of DMA transfer channel groups, and a plurality of types of DMAs are set. Multiple DMA transfer channel groups corresponding to each transfer request DMA transfer channel group selection mask data for selecting use / non-use of each group is set, and the DMA transfer channel selection mask data is set corresponding to each of the plurality of types of DMA transfer requests. The use / non-use of each of the plurality of DMA transfer channel groups is selected according to the DMA transfer channel group selection mask data set corresponding to each of a plurality of types of DMA transfer requests, and the DM selected for use is selected.
A use / non-use of each of the plurality of DMA transfer channels is selected according to the DMA transfer channel selection mask data set corresponding to each of the plurality of types of DMA transfer requests for each A transfer channel group. A DMA processing method comprising: performing a DMA transfer process of a DMA transfer channel whose use is selected for each selected DMA transfer channel group. 2. Data indicating that DMA transfer channel data is set is set as channel group confirmation data for each of a plurality of DMA transfer channel groups, and the channel group confirmation data and the DMA transfer channel group selection mask data are set. 2. The DMA processing method according to claim 1, wherein a DMA transfer channel group is selected by a logical product. 3. A DMA transfer channel defined by a set of DMA transfer channel data consisting of DMA transfer control data, DMA transfer word number data, DMA transfer source address data, and DMA transfer destination address data, as a DMA transfer unit. A DMA processor for performing a transfer, wherein one or a plurality of sets of DMA transfer channel data respectively defining one or a plurality of DMA transfer channels constituting one DMA transfer channel group; DMA transfer channel group data composed of DMA transfer channel selection mask data for selecting use / non-use of each transfer channel is stored corresponding to a plurality of DMA transfer channel groups, and a plurality of types of DMA transfer requests are stored. Corresponding to the DMA transfer channel selection cells. A memory in which data is set, and mask data for selecting a DMA transfer channel group which is set corresponding to each of the plurality of types of DMA transfer requests and selects use / non-use of each of the plurality of DMA transfer channel groups are stored. DMA transfer channel group mask registers to be used, and use / non-use of each of the plurality of DMA transfer channel groups according to the DMA transfer channel group selection mask data set corresponding to each of the plurality of types of DMA transfer requests. DM selected and used
A use / non-use of each of the plurality of DMA transfer channels is selected according to the DMA transfer channel selection mask data set corresponding to each of the plurality of types of DMA transfer requests for each A transfer channel group. A DMA transfer block for performing a DMA transfer process of a DMA transfer channel whose use is selected for each of the selected DMA transfer channel groups. 4. A DMA data confirmation register for storing, as channel group confirmation data, data indicating that DMA transfer channel data is stored in a memory for each of a plurality of DMA transfer channel groups, DMA by logical product of confirmation data and mask data for DMA transfer channel group selection
4. The DMA processing device according to claim 3, wherein a transfer channel group is selected.