JP3322993B2 - Information processing device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a resource (for example, a memory)
DMA (direct memory access) data transfer between
The present invention relates to an information processing apparatus that can be used depending on the system, and particularly has a feature in its DMA transfer method.

[0002]

2. Description of the Related Art In an information processing apparatus using a central processing unit (hereinafter, referred to as a CPU), data storage in a storage device (hereinafter, referred to as a memory) is indispensable. In the block transfer, a DMA transfer method is adopted to reduce the load on the CPU.

[0003] In this specification, the term "information processing apparatus" broadly refers to not only a computer and a word processor but also an apparatus having a CPU.

Next, a general conventional DMA transfer control is described as follows.
A brief description will be given with reference to FIGS. 2, a CPU 1 and a DMA controller (hereinafter, referred to as a DMAC) 2 include a memory space (for example, “00000” to “FFFFF” (hexadecimal notation: H)) of a memory 3 as shown in FIG. The CPU 1 has the same address space, and sets information necessary for DMA transfer, such as a transfer source address, a transfer destination address, and the number of transfer bytes, in the DMAC 2 by the DMAC 2.
When the DMAC 2 is started, the DMAC 2 autonomously reads data from the transfer source address area of the memory 3 and writes the data into the transfer destination address area of the memory 3 by the number of transfer bytes, thereby repeating the DMA transfer of data. Running.

[0005]

However, some information processing apparatuses using a CPU gradually increase the amount of data to be handled and require expansion of a memory space. Moreover, at the time of such expansion, the current CPU and DM
There are devices that require that AC be used continuously.

However, in order to extend the accessible range of each CPU or DMAC, the architecture must be largely changed.
DMAC will be used. This cannot satisfy the latter requirement.

Therefore, even when the memory space is expanded,
Although it is conceivable to attempt to perform DMA transfer control using the conventional DMAC as it is, since the conventional DMAC specifies the memory area of the transfer source and the transfer destination only by the address bus, the existing DMAC and the expanded memory space can be used. Even when a transfer source and a transfer destination are specified by an address at the time of transfer between memories, the existing memory space and the expanded memory space take in addresses as both the transfer source and the transfer destination, that is, the conventional DMAC Cannot specify the transfer destination and transfer source effectively.

[0008] The problem has been described above using the example of expansion. However, a similar problem may be a problem even at the time other than the expansion. For example, a device having a CPU is initially C
A similar problem arises when an attempt is made to provide a memory having a memory space larger than the address space of the PU or DMAC.

For this reason, an information processing apparatus capable of realizing DMA transfer even when the memory space is larger than the address space of the CPU or DMAC, regardless of whether the configuration is based on expansion or the configuration from the beginning, is desired.

[0010]

According to the present invention, an information processing apparatus having a DMAC in addition to a CPU and resources having a memory space is provided as follows.

That is, as a resource, the memory space is CP
A plurality of resources equal to the U and DMAC address spaces are provided, and a resource selection unit is provided for selecting a source resource and a destination resource of the DMA transfer and controlling a read operation and a write operation of the resource. Further, as the DMAC, one having N transfer control blocks in which information necessary for DMA transfer is set from the CPU and operates independently is applied, and DMA transfer between resources and / or DMA transfer with the same resource are applied. One of the transfer control blocks in the DMAC is fixedly assigned to the combination of the transfer source resource and the transfer destination resource. When the DMAC sets information necessary for DMA transfer in one of the internal transfer control blocks and the transfer control block obtains an access right, the DMAC sends the transfer source and the transfer destination to the resource selection means. Are sequentially selected and the DMA transfer is executed.

[0012]

According to the present invention, an information processing apparatus comprises a CPU and a DMA.
In the case where a plurality of resources having a memory space equal to the address space of C are provided, taking into consideration that the transfer source resource and the transfer destination resource of the DMA transfer cannot be specified depending on the address,
A resource selection means is provided so that the resource selection means can select and specify a source resource and a destination resource irrespective of an address, and control the read operation and the write operation of the resource.

Here, the resource selecting means can select and specify the source resource and the destination resource regardless of the address.
As the DMAC, one having N transfer control blocks in which information necessary for DMA transfer is set from the CPU and operates independently is applied, and for DMA transfer between resources and / or DMA transfer using the same resource, the transfer is performed. One of the transfer control blocks in the DMAC is fixedly assigned to the combination of the source resource and the destination resource. That is, D
The MAC sends a CP to one of the internal transfer control blocks.
When the information necessary for the DMA transfer is set from U and the transfer control block obtains the access right, the resource selecting means becomes the transfer source and the transfer destination of the DMA transfer depending on the type of the transfer control block that has obtained the access right. A resource is specified and a selection operation is performed.

[0014]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the information processing apparatus according to the present invention will be described below in detail with reference to the drawings. Here, FIG. 1 shows the overall configuration of this embodiment.

In FIG. 1, an information processing apparatus 10 according to this embodiment includes a CPU 15, two BANK memories (one of them is a BANK0 memory,
The other is called BANK1 memory) 11 and 12, DMA
C13 and a memory selection unit 14.

Since one memory has been added due to the expansion of the memory space, two BANK0 memories 11 and BAN0
The K1 memory 12 may be provided, or two K1 memories may be provided from the beginning.

The CPU 15 and the DMAC 13 are connected to all of an address bus 16, a data bus 17, and a control bus 18. On the other hand, the BANK0 memory 11 and the BANK1 memory 12 are connected to the address bus 16 and the data bus 17, respectively, but are not connected to the control bus 18 but extend from the memory selecting unit 14. Control signal line 20 or 21
It is connected to the. The memory selection unit 14 is a data bus 1
7 and the control bus 18, but not to the address bus 16. Memory selector 14
Is connected to a plurality of control signal lines 19 extending from the DMAC 13, receives a control signal as described later, and extends two pairs of control signal lines 20 and 21 to form a BANK 0 memory. 11 and BANK1 memory 12 and BANK0
The memory 11 and the BANK1 memory 12 can be provided with control signals as described later.

As is apparent from these connection relationships, C
The PU 15 and the DMAC 13 share an address space, and the address space is, for example, “0” as shown in FIG.
0000 "to" FFFFF "(hexadecimal notation: H), that is, the CPU 15 and the DMAC 13 specify and access addresses in a 20-bit address space, while the memory space is shown in FIG. As shown in the figure, the address space is twice as large, half of the memory space is related to the BANK0 memory 11, and the other half is the BANK0 memory.
One memory 12 is involved. That is, each BANK0
Each of the memory 11 and the BANK1 memory 12 has a memory space equal to a 20-bit address space.
A 20-bit address is input from a common address bus 16.

In this embodiment, the DMA transfer of the block data is performed by the BANK0 memory 11 as described later.
And between the BANK 1 memory 12 in both directions.

The data bus 17 includes a CPU 15, a DMAC
13, BANK0 memory 11 and BANK1 memory 12
Have a common data width (for example, 8 bits), and are connected to these resources by the same number of bits. The signal lines of several bits or all bits of the data bus 17 are connected to the memory selection unit 1.
4 is connected to the CPU 15 and the BANK 0 memory 1
1 or the BANK 1 memory 12 is accessed when the B signal transmitted from the CPU 15 through these data signal lines.
ANK type data can be input to the memory selection unit 14.

In this embodiment, the CPU 15
When the NK0 memory 11 or the BANK1 memory 12 is accessed, since the address space is common, the address cannot be accessed simply by placing it on the address bus 16. Therefore, the BANK type data is placed on the data bus 17 in advance, and Given by the memory selection unit 14
As will be described later, a BANK0 memory 11 or a BANK1 memory 12 to be accessed is designated.
It should be noted that the CPU 15 is provided with the BANK0 memory 11 or the BANK
When accessing the K1 memory 12, a control signal is output to the control bus 18 as appropriate.
Since the memory 11 and the BANK 1 memory 12 are not connected to the control bus 18, these control signals are also taken into the memory selecting unit 14 as described later, are appropriately processed, and are sent to the BANK 0 via the pair of control signal lines 20 or 21. Memory 11 or BANK1 memory 12
To be entered.

A control signal supplied from the CPU 15 to the memory selection unit 14 is a read / write signal CPU-R / W * (* is "0") which instructs read and write common to the two BANK memories 11 and 12. Meaning significant)
An address strobe signal (access strobe signal) CPUAS indicating that the CPU 15 is accessing one of the two BANK memories 11 and 12;
This is a control signal LT for instructing to take in ANK type data.

The DMAC 13 of this embodiment employs a type which can perform a plurality of DMA transfers in parallel. Here, assuming that the number of parallel processes is N (in the following description, the number is assumed to be two), the DMAC 13 internally has two transfer control blocks (hereinafter, channel 0 and channel 1) 1
3a and 13b. Each channel 13a, 13
Information b required for DMA transfer, such as a transfer source address, a transfer destination address, and the number of bytes to be transferred, is set by the CPU 15, and one channel b is selected by an internal priority determination circuit to obtain an access right.

The channel number (0 or 1) signal CH0A, CH1A being accessed is output from the DMAC 13 to a control signal line (see reference numeral 19) for each channel number to the memory selection unit 14. DMAC 13
The channel number signals CH0A and CH1A and the BANK0 memory 11 and BA
A read / write signal DMA-R / W * for instructing read and write common to the NK1 memory 12;
Sends an access strobe signal DMAAS indicating that one of the BANK0 memory 11 and the BANK1 memory 12 is being accessed, via the control signal line 19.

Since the DMAC 13 has a plurality of channels, the function of each channel can be arbitrarily determined in the system. In this embodiment, as shown in FIG. 5, the channel 0 is stored in the BANK 0 memory 11 through the BANK 1 memory. 12
Channel 1 from the BANK1 memory 12 to the BANK0.
It has been decided to use it for DMA transfer to the memory 11.

Therefore, when causing the DMA transfer from the BANK 0 memory 11 to the BANK 1 memory 12 to be executed, the CPU 15 sets information necessary for the DMA transfer to the channel 0 (13a).
When the DMA transfer to the ANK0 memory 11 is executed, information necessary for the DMA transfer is set in the channel 1 (13b).

As described above, the memory selection unit 14
The two control signal lines 20 connected to the control signal line 19 from the AC 13 and extending therefrom.
BANK0 memory 11 and BANK1
It is connected to the memory 12. That is, the memory selection unit 1
4 is a DMAC 13 and each BANK 0 memory 11,
It is located between the BANK 1 memories 12.

The memory selecting section 14 mainly has a BANK
In order to eliminate the adverse effects caused by the input of a common address to the 0 memory 11 and the BANK 1 memory 12,
At the time of MA transfer, B
One of the ANK0 memory 11 and the BANK1 memory 12
It is responsible for selecting and accessing the user. That is, the BANK0 memory 11 and the BANK1 memory 1
2 has a memory space equal to the address space of the CPU 15 and the DMAC 13,
The source memory and the destination memory of the transfer cannot be specified, and therefore, a memory selection unit 14 is provided so that the source memory and the destination memory can be selected and specified regardless of the address.

As described above, the BANK0 memory 11 and the BA
Since the memory selection unit 14 is responsible for selecting between the NK1 memories 12, the CPU 15
When the NK1 memory 12 is accessed, the BANK memory 11 or 12 to be accessed by the memory selector 14 is designated.

The memory selector 14 has, for example, the configuration shown in FIG. The memory selection unit 14 stores the BANK register 3
0 and a plurality of logic gates 31 to 46.

The BANK register 30 stores the B
The BANK type data output to the data bus 17 when directly accessing the ANK0 memory 11 or the BANK1 memory 12 is fetched based on the control signal LT for fetching, and the BANK0 indicated by the BANK type data is fetched.
The enable signal # 0EN or # 1EN for the memory 11 or the BANK1 memory 12 is output with significance. The capture control signal LT is, for example, C
It is set in a register provided in the PU 15 or in association with the CPU 15 and is provided through one signal line of the control bus 18.

Memory selector 14 (logic gate groups 31 to 4)
6) are control signals CPUAS and CPU-R / W * supplied from the CPU 15 via some control signal lines of the control bus 18 and the DMAC 13
Provided through a control signal line 19 from CH0
A, CH1A, DMA-R / W *, DMAAS, and BA
Enable signals # 0EN and # 1 from the NK register 30
BANK0 memory 11, BANK1 based on EN
Chip select signals # 0CS, # for the memory 12
1CS and the logic levels of the write enable signals # 0WE and # 1WE.

In the following, the BANK0 memory 11, BAN
Chip select signal # 0C for K1 memory 12
S, # 1CS and write enable signals # 0WE, # 1
A description will be given of the case where WE becomes significant, and the description of the input / output relationship of each logic gate 31,.
It is important when to make the output signal from the memory selection unit 14 significant. For that purpose, what kind of logic gate is used and how it is connected are not limited to those of the embodiment because of a high degree of freedom. .

The chip select signal # 0CS to the BANK0 memory 11 is (2) when both the access strobe signal CPUAS from the CPU 15 and the enable signal # 0EN for the BANK0 memory 11 are significant ("1"). When the access strobe signal DMAAS from the DMAC 13 and the channel 0 number signal CH0A are significant and the read / write signal DMA-R / W * indicates a read, (3) the access strobe signal DMAAS from the DMAC 13 and the channel 1 Number signal CH1A
Is significant and the read / write signal DMA-R / W * indicates a write.

The chip select signal # 1CS to the BANK1 memory 12 is (1) when the access strobe signal CPUAS from the CPU 15 and the enable signal # 1EN for the BANK1 memory 12 are both significant (2)
Access strobe signal DMAAS from DMAC 13
When the channel 1 number signal CH1A is significant and the read / write signal DMA-R / W * indicates writing, (3) the access strobe signal DMAAS and the channel 0 number signal CH0A from the DMAC 13 are significant. This is significant when the read / write signal DMA-R / W * indicates a read operation.

The write enable signal # 0WE to the BANK0 memory 11 is obtained when (1) the access strobe signal CPUAS from the CPU 15 and the enable signal # 1EN for the partner BANK1 memory 12 are significant and
When the read / write signal CPU-R / W * from the CPU 15 is reading, (2) the access strobe signal DMAAS from the DMAC 13 and the channel 1 number signal CH1
A is significant and the read / write signal DMA-R / W *
Is significant when indicates a light.

The write enable signal # 1WE to the BANK1 memory 12 is (1) because the access strobe signal CPUAS from the CPU 15 and the enable signal # 0EN for the partner BANK0 memory 11 are significant.
When the read / write signal CPU-R / W * from the CPU 15 is reading, (2) the access strobe signal DMAAS from the DMAC 13 and the channel 0 number signal CH0
A is significant and the read / write signal DMA-R / W *
Is significant when indicates a light.

Next, from the BANK 0 memory 11,
The DMA transfer operation to one memory 12 will be described with reference to FIG.

When such a DMA transfer is desired, C
Information necessary for a transfer operation, such as a transfer source address, a transfer destination address, and a transfer byte number, is given from the PU 15 to the channel 0 of the DMAC 13 and set. After setting such information, the CPU 15 activates DMA transfer to the channel 0 of the DMAC 13. DMAC 13 is CPU 15
When the transfer start is received from the CPU 15, a bus right acquisition request signal is sent to the CPU 15.

When the DMAC 13 obtains the bus right (at this time, the address strobe signal CPUAS from the CPU 15 does not become significant), it outputs various signals at the timing shown in FIG.

First, the DMAC 13 (channel 0)
The address strobe signal DMAAS and the channel 0 number signal CH0A are made significant to indicate that the channel 0 in the MAC 13 accesses the memory. Next, in order to read data from the transfer source memory, the read / write signal DMA
-R / W * is read and the transfer source address is output to the address bus 16 (A <19,0>). At this time,
The memory selecting unit 14 determines that the reading of the transfer source memory when the channel 0 is accessed is the BANK0 memory 11, and makes the BANK0 memory 11 valid and the BANK1 memory 12 invalid. Select signal # 0CS is made significant, and BANK0
Input to the chip select input terminal of the memory 11.

When the data reading from the BANK 0 memory 11 is completed, the DMAC 13
In order to write data to the K1 memory 11, the read / write signal DMA-R / W * is set to the write display, and the transfer destination address is output to the address bus 16 (A <19, 0>). At this time, the DMAC 13 maintains the state where the address strobe signal DMAAS and the channel 0 number signal CH0A are made significant, and the memory selecting unit 14
Is written to the BANK 1 memory 1 that is the transfer destination
2, the BANK 1 memory 12 is validated,
In order to invalidate the BANK0 memory 11, BANK0
The chip select signal # 1CS to the memory 12 is made significant and input to the chip select input terminal of the BANK1 memory 12. When the DMAC 13 completes the data writing to the BANK 1 memory 11, the address strobe signal D
MAAS, channel 0 number signal CH0A and chip select signal # 1CS are made insignificant, and the transfer cycle is terminated.

By repeating the above-described transfer cycle while sequentially incrementing the address by the set number of transfer bytes, the BANK0 memory 11 transfers the BANK1
The DMA transfer to the memory 12 is completed.

When performing a DMA transfer from the BANK1 memory 12 to the BANK0 memory 11, the CPU 15
The same setting as for channel 0 is performed for channel 1 of C13, and transfer is activated.

As shown in FIG. 8, the DMAC 13 makes the address strobe signal DMAAS and the channel 1 number signal CH1A significant after acquiring the bus right, and reads the address bus 16 (A <19, 0) to read data from the transfer source memory.
>), The source address is output. At this time, the memory selection unit 14 determines that the read memory at the time of accessing the channel 1 is the BANK1 memory 12, makes the chip select signal # 1CS signal significant, and inputs the signal to the chip select input terminal of the BANK1 memory 12.

After the data reading from the BANK 1 memory 12 is completed, the DMAC 13 displays the read / write signal R / W * in order to write the data to the transfer destination memory, and performs the data writing. The unit 14 writes B when the channel 1 accesses
The ANK0 memory 11 is determined, the chip select signal # 0CS signal is made significant, and input to the chip select input terminal of the BANK0 memory 11.

By repeating the above-described transfer cycle while sequentially incrementing the address by the set number of transfer bytes, the BANK 1 memory 12 transfers the BANK 0
The DMA transfer to the memory 11 is completed.

In the above, transfer by channel 0 and
Although the transfer by the channel 1 is described separately, in practice, the transfer by the channel 0 and the transfer by the channel 1 are performed because the channels 0 and 1 acquire the memory access right every cycle by the priority determining circuit in the DMAC 13. Parallel processing is possible.

The operation at the time of access by the CPU 15 is similar to the above operation except that the BANK memory to be accessed is specified regardless of the channel 0 number signal or the channel 1 number signal. Omitted.

According to the above embodiment, the CPU 15 and the DM
Even if the memory space accessible by the AC 13 is twice as large as the address space (for example, due to the expansion of the memory space), the DMA transfer between the BANK memories having the same memory space as the address space divides the channel in the DMAC 13 for each transfer direction. Can be performed by assigning

For example, when the memory space becomes an integral multiple of the address space due to the expansion, such transfer is possible only by adding a simple circuit such as the memory selection unit 14.
Since the memory space can be doubled using the existing CPU 15 and DMAC 13, the system performance is also improved. That is, it is not necessary to use a different CPU or DMAC.

In the above embodiment, the same BA
The DMA transfer between the memory spaces in the NK memory cannot be executed. However, it is possible to easily deal with the DMA transfer by allocating the DMA transfer to another channel and providing a configuration for the channel in the memory selection unit 14. Can be.

In the above embodiment, the CPU 15
And the memory space accessible by the DMAC 13 is twice as large as the address space.
The present invention can be similarly applied even when the memory space accessible by the MAC 13 is three times or more the address space.

Further, in the above embodiment, the case of DMA transfer between memory spaces conscious of memories provided in close proximity to the CPU such as a semiconductor memory has been described, but one or both of the BANK memories may be connected to an external storage device or the like. It may be an input / output device or the like, and is described as “resource” in the claims.

[0055]

As described above, according to the present invention, the DMA
A resource selection means for selecting a transfer source resource and a transfer destination resource and controlling a read operation and a write operation of the resource is provided. Further, as a DMAC, information necessary for DMA transfer is set from a CPU and operates independently. For the DMA transfer between resources and / or the DMA transfer with the same resource, apply any transfer in the DMAC for the combination of the source and destination resources. The control block is fixedly assigned, and the DMAC
Any one of the transfer control blocks in the internal
When the information necessary for the A transfer is set and the transfer control block obtains the access right, the resource selection means is made to sequentially select the transfer source and transfer destination resources to execute the DMA transfer. Memory space is CPU and DMA
Even if a plurality of resources equal to the address space of C are provided, DMA transfer between the resources can be executed.

[Brief description of the drawings]

FIG. 1 is a block diagram illustrating an information processing apparatus according to an embodiment.

FIG. 2 is a block diagram illustrating a conventional information processing apparatus.

FIG. 3 is an explanatory diagram showing a relationship between a conventional address space and a memory space.

FIG. 4 is an explanatory diagram showing a relationship between an address space and a memory space in the embodiment.

FIG. 5 is an explanatory diagram illustrating a relationship between a channel in a DMAC and a transfer direction according to the embodiment;

FIG. 6 is a block diagram illustrating a detailed configuration example of a memory selection unit according to the embodiment;

FIG. 7 is a timing chart showing DMA transfer using channel 0 according to the embodiment.

FIG. 8 is a timing chart showing DMA transfer by channel 1 in the embodiment.

[Explanation of symbols]

10 information processing device, 11 BANK0 memory (resource), 12 BANK1 memory (resource), 13 DMA
C, 13a... Channel 0 (transfer control block), 13b
... channel 1 (transfer control block), 14 ... memory selection unit (resource selection means), 15 ... CPU.

Claims (2)

(57) [Claims] An information processing apparatus having a DMAC in addition to a CPU and a resource having a memory space, wherein a memory space has a plurality of resources equal to the address space of the CPU and the DMAC, Resource selection means for selecting a transfer source resource and a transfer destination resource and controlling a read operation and a write operation of the resource is provided. As the DMAC, information necessary for DMA transfer
A system having N transfer control blocks set independently from the PU and operating independently is applied, and the DM between the above resources is
A transfer and / or DMA transfer with the same resource, the above DM
Any one of the transfer control blocks in the AC is fixedly assigned, and the DMAC sets information necessary for DMA transfer from the CPU in any of the internal transfer control blocks, and the transfer control block has an access right. When you get
An information processing apparatus, wherein the resource selecting means sequentially selects the resources as a transfer source and a transfer destination to execute DMA transfer. 2. The method according to claim 1, wherein when the CPU accesses any one of the resources, the resource selecting means gives the resource type information and the access type information to select a resource to be operated to perform the access. 2. The information processing device according to 1.