JP2003296105A - Data processor - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To improve the efficiency when loading non-placed words on a large number of contiguous addresses. <P>SOLUTION: A selector 8 selects the address of the address signal or the address with 2 added thereto based on the access number. Based on the address of the selected result, two placed words allocated to addresses are read from memories 16 and 17, and one of the two words is stored in a register 20 or 21. Selectors 22 and 23 select two non-placed words not allocated to addresses from the words stored in the register 20 or 21 in the previous access and the two placed words presently read from the memories 16 and 17. <P>COPYRIGHT: (C)2004,JPO

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a data processing device for digital signal processing.

[0002]

2. Description of the Related Art The basic processing of a digital signal processor (DSP), which is a data processing device for performing digital signal processing, is a product-sum operation of coefficients and data. Therefore, a DSP having a memory and a bus for coefficients and data is considered. Another approach is to use a common memory and bus for coefficients and data so that two words can be loaded from the memory at a time, instead of a DSP having multiple memories and buses at an average processing speed. It is possible to achieve almost the same performance.

In the memory of the DSP, one address is assigned to each word, and a plurality of consecutive words are stored at a plurality of consecutive addresses. With a DSP that loads two words from memory at the same time,
It is sufficient to access two consecutive addresses at the same time.

Smaller address (bit indication) assigned to one of two consecutive words
There is no problem when accessing two words at the same time such that is even (that is, the least significant bit is 0). The address of the other word to be loaded at the same time has the number added to that number, but that word can be specified simply by changing the least significant bit to 1. Therefore,
It is possible to employ an efficient method of simultaneously loading two words on two addresses in which higher bits than the least significant bit are common. The method of assigning such a word to an address is hereinafter referred to as "alignment".

However, of two consecutive addresses,
There is a problem in accessing two words where the smaller address (bit representation) assigned to one word is odd (ie the least significant bit is 1).
The address of the other word has a number that is one more than that number, but adding one to the number in the bit representation of an odd number changes not only the least significant bit, but also one or more of the higher bits. There must be. The method of assigning such a word to an address is hereinafter referred to as "non-alignment".

On the other hand, in a general type address bus,
You can only specify one address at a time.

[0007]

Since the conventional data processing apparatus is configured as described above, in order to load two unaligned words at the same time, two addresses having considerably different bit configurations are designated. Therefore, there is a problem that two address buses are required.

Therefore, as for non-aligned two-word loading, a technique is conceivable in which four consecutive words including the non-aligned two words are acquired by two aligned two-word loads. That is, according to this technique, four consecutive words starting from the address (even number) immediately before the designated address are read from the memory by two times of loading, and the necessary two words of them are selected to select the data register. To store.

However, in such a technique, when a large number of unaligned words on a large number of consecutive addresses are to be loaded, two unaligned words must be loaded twice in order to obtain each word. , The throughput increases and the processing time increases. In the end, throughput and processing time are approximately doubled compared to loading aligned words of the same size. This is the same as loading one word at a time and does not take advantage of the two word load instruction.

So that successive words are always aligned
The above problem seems to be solved if it can be stored in memory, but avoids misalignment when word boundaries change dynamically, such as when memory is used as a circular buffer. Sometimes I can't.

The present invention has been made to solve the above problems, and can improve the loading efficiency when loading a large number of unaligned words on a large number of consecutive addresses. The purpose is to obtain a new data processing device.

[0012]

A data processing apparatus according to the present invention has a plurality of addresses designated by binary numbers, and a memory section in which an information portion is stored in association with each address, An address specification part that can specify one address to access in the memory part at a time, and can specify the address obtained by adding or subtracting 2 to the address specified in the previous access in the next access First to add 2 to the address specified by the division
Based on the number of accesses to the adder and memory of
A first selection unit capable of selecting an address designated by the address designation unit or an address obtained as a result of addition by the first addition unit and outputting the value of the selected address;
Based on the value of the address output by the first selection unit, a read unit that reads two aligned information sections from two addresses in the memory section and one of the two information sections read by the read section From the first storage part to store, the information part already stored in the first storage part by the previous access to the memory part, and the two information parts of the alignment currently read by the reading part, And a second selection unit capable of selecting two information parts of alignment.

In the data processing device according to the present invention, the memory section, the first adding section, the first selecting section, the reading section, the first storing section and the second selecting section are provided in a single circuit. And the memory part is the first
Memory and a second memory to which an odd number of addresses are assigned, and the reading unit first writes two information parts corresponding to bits higher than the least significant bit of the input one address. And the second memory.

In the data processing device according to the present invention, when the two non-aligned information parts are loaded from the memory part, the data processing device varies depending on the circuit or software that monitors the identity of the values of the first storage part and the memory. An instruction unit that generates a non-aligned load signal is provided, and the first selection unit is based on the non-aligned load signal 2w, and the result of addition of the address designated by the address designation unit or the first addition unit is obtained. An address is selected and the value of the selected address is output.

In the data processing device according to the present invention, when the two non-aligned information portions are loaded from the memory portion, the second addition portion adds +2 or -2 to the address designated by the address designation portion. A second storage for storing the address of the result added by the second adder, the address already stored in the second storage by a previous access to the memory, and the current address in the addressing unit. A second comparison unit that has already been stored in the first storage unit by a previous access to the memory unit when the comparison result by the comparison unit matches. Two non-aligned information portions are selected from the information portion and two aligned information portions currently read by the reading unit.

In the data processing device according to the present invention, when the two non-aligned information portions are loaded from the memory portion, the data processing device varies depending on the circuit or software that monitors the identity of the values of the first storage portion and the memory. A flag setting unit that sets a flag and a switching unit that switches the second selection unit between valid and invalid based on the flag are provided.

[0017]

BEST MODE FOR CARRYING OUT THE INVENTION An embodiment of the present invention will be described below. Embodiment 1. FIG. 1 shows a digital signal processor which is a data processing device according to the first embodiment of the present invention. In the figure, 30 is an instruction decoder (instruction section, flag setting section), 31 is an address generation section (address designation section),
32 is a memory load control circuit, 33 is a register file, and 34 and 35 are data buses.

The instruction decoder 30 receives an instruction bit string from a central processing unit (not shown) or an external device,
The type of instruction requested by the central processing unit or the external device is determined from the received instruction bit string, and the operation is performed based on the instruction bit string. When the received instruction bit string is a memory access instruction, the address generator 31 supplies various signals to the memory load control circuit 32 based on the memory access instruction.

As will be described later, the memory load control circuit 3
2 has two memories and outputs one or a plurality of words from these memories to one or both of the data buses 34 and 35 based on various signals received from the instruction decoder 30. The instruction decoder 30 monitors outputs on the data buses 34 and 35, selects a word to be loaded, and stores it in the register file 33. The register file 33 is, for example, a general-purpose register. The selected word is stored in the register file 33 in association with its address.

The instruction bit string of the memory access instruction supplied to the instruction decoder 30 specifies, for example, the address of the smaller of the two words to be loaded and the necessity of post-increment or post-decrement.

Address generation unit 31 of instruction decoder 30
Generates an address signal that specifies the address that will be the pointer to load the word.

Further, the instruction decoder 30 determines whether or not non-aligned two-word access must be performed based on the least significant bit of the first address designated by the instruction bit string of the memory access instruction. Specifically, if the least significant bit of the specified first address is 1, then non-aligned 2
Need word access. In this case, the instruction decoder 30 outputs the non-aligned load signal 2w which becomes L (low level) in the first word and H (high level) in the second word.

If the least significant bit of the designated first address is 0, aligned 2 word access may be performed. In this case, the instruction decoder 30 outputs the unaligned load signal 2
Set w to L. Further, when only one address is designated, it is sufficient to access one word, so the instruction decoder 30 sets the non-aligned load signal 2w to L.

For loading more than two consecutive non-aligned words, the digital signal processor is capable of post-increment or post-decrement register indirect addressing. In the post-increment method, when loading a word on three or more consecutive addresses, while loading the word from the memory load control circuit 32, the word at the higher address that should be loaded in the next step is loaded into the memory. It is automatically prepared by the control circuit 32. In the post-decrement method, when loading a word on three or more consecutive addresses, while loading a word from the memory load control circuit 32, the word with a smaller address that should be loaded in the next step is loaded into the memory. Control circuit 32
Automatically prepared by.

If the memory access instruction specifies that post-increment or post-decrement is necessary and non-aligned two-word access is required, the instruction decoder 30 outputs the increment signal inc. Alternatively, the decrement signal dec is set to H. When performing post-increment in non-aligned 2-word access, the instruction decoder 30 sets the increment signal inc to H and the decrement signal dec to L.
To When performing post-decrement in non-aligned 2-word access, the instruction decoder 30 sets the decrement signal dec to H and the increment signal inc to L.

With regard to post-increment or post-decrement type register indirect addressing in non-aligned word loading, this digital signal processor loads two words on consecutive addresses at the same time (in one cycle). It is possible to implement a load mode and a continuous 2-word load mode in which two words on consecutive addresses are continuously (in two cycles) loaded.

The instruction decoder 30 supplies to the memory load control circuit 32 a mode signal mo which specifies either the simultaneous 2-word load mode or the continuous 2-word load mode, depending on the situation. In the simultaneous 2-word load mode, the mode signal mo is H, and in the continuous 2-word load mode, the mode signal mo is L. As will be apparent from the following description, the mode signal mo is stored in the register 20 and the memory 1
6 or a circuit that monitors the coherency between the values of the register 21 and the memory 17 or a flag that fluctuates depending on software (generates an instruction bit string).

In the case of the 1-word load instruction and the aligned 2-word load instruction, the non-aligned load signal 2w, the increment signal inc, the decrement signal dec, and the mode signal mo are all L.

FIG. 2 shows the memory load control circuit 3 in FIG.
2 is shown. In the figure, 1 to 3 are AND gates and 4 to 6
Is an OR gate, 7, 9, 18, 19, 24 are selectors,
8 is a selector (first selection unit), 10 is a register (second selection unit)
Storage unit), 11 is a comparator (comparison unit), and 12 and 13 are A
ND gate (switching unit), 14 adder (second adding unit), 15 adder (first adding unit), 16 memory (memory unit, reading unit, first memory), 17 memory (Memory unit, reading unit, second memory), 20, 2
Reference numeral 1 denotes a register (first storage unit), and 22 and 23 denote selectors (second selection unit).

The AND gate 1 has a non-aligned load signal 2w.
AND the least significant bit of the address signal. That is, when the unaligned load signal 2w is H and the least significant bit of the address signal is H (when trying to access an odd address of the memory), the output of the AND gate 1 becomes H. Otherwise, the output of AND gate 1 will be L. AND
The output of the gate 1 is supplied to the selector 8.

The AND gate 2 has three input terminals, and when all of the increment signal inc, the output of the OR gate 4 and the least significant bit of the address signal are H, A
The output of the ND gate 2 becomes H. Otherwise, AND
The output of the gate 2 becomes L. The output of the AND gate 2 is supplied to the selector 19, the AND gate 12, and the OR gate 6.

The AND gate 3 has three input terminals, and when all of the decrement signal dec, the output of the OR gate 5 and the least significant bit of the address signal are H, A
The output of the ND gate 3 becomes H. Otherwise, AND
The output of the gate 3 becomes L. The output of the AND gate 3 is supplied to the selector 18, the AND gate 13, and the OR gate 6.

The OR gate 4 takes the logical sum of the mode signal mo and the non-aligned load signal 2w. That is, if either or both of the mode signal mo and the non-aligned load signal 2w are H, the output of the OR gate 4 becomes H. If both the mode signal mo and the non-aligned load signal 2w are L, the output of the OR gate 4 becomes L. The output of the OR gate 4 is supplied to the AND gate 2.

The OR gate 5 takes the logical sum of the mode signal mo and the inverted signal of the non-aligned load signal 2w. That is, when the mode signal mo is H and / or the non-aligned load signal 2w is L, the output of the OR gate 5 is H. Mode signal mo is L and non-aligned load signal 2w
Is H, the output of the OR gate 5 is L.
The output of the OR gate 5 is supplied to the AND gate 3.

The OR gate 6 takes the logical sum of the output of the AND gate 3 and the output of the AND gate 2. That is, A
If either or both of the output of the ND gate 3 and the output of the AND gate 2 are H, the output of the OR gate 6 becomes H. If both the output of the AND gate 3 and the output of the AND gate 2 are L, the output of the OR gate 6 is L.

The adder 15 adds +2 to the address signal and supplies the added value to the selector 8.

In the selector 8, the output of the AND gate 1 is H
When, the output of the adder 15 is output, and when the output of the AND gate 1 is L, the address signal is output. The output of the selector 8 is supplied to both the memories 16 and 17. The output of selector 8 specifies the address referenced to load the word from either or both memories 16,17.

The memory 16 stores a word at an even address (the address whose least significant bit is 0 (L)). On the other hand, the memory 17 has an odd address (the least significant bit is 1
The word on the address ((H)) is stored. The addresses in these memories 16 and 17 are identified by the output of the selector 8.

FIG. 3 shows how the addresses are arranged in the memories 16 and 17. In the figure, addr is an odd address, and in the memory 17 for odd addresses, the odd addresses are regularly arranged, and the memory 1 for even addresses is
In No. 6, even addresses are regularly arranged. The odd address addr in the memory 17 is at the same position as the even address addr-1. Odd address ad
The least significant bits of dr and the even address addr-1 are 1 and 0, respectively, but the odd address addr in the same place is
And the even-numbered address addr-1, all the bits higher than the least significant bit are common.

In this embodiment, each of the memories 16 and 17 has a read-out unit (not shown) for reading itself, and the read-out unit outputs the least significant bit from the output of the selector 8. Read the word at the corresponding address by referring to the upper bits. Therefore, two words are read from the two memories 16 and 17 based on one output value of the selector 8. For example, if the output value of the selector 8 is an odd address addr or an even address add
At r-1, two words on the odd address addr and the even address addr-1 surrounded by the dotted line are accessed.

The selector 7 has an increment signal inc.
When is H, it outputs +2 for post-increment,
When the increment signal inc is L, -2 is output for post-decrement. The output of the selector 7 is supplied to the adder 14.

The adder 14 adds the output of the selector 7 and the address signal for post increment or post decrement. The output of the adder 14 is the selector 9
Is supplied to.

The selector 9 supplies the output of the adder 14 to the register 10 when the output of the OR gate 6 is H, and supplies the output of the register 10 to the register 10 again when the output of the OR gate 6 is L. The register 10 holds the output of the selector 9 and supplies the held value to the comparator 11.

The comparator 11 compares the output of the register 10 with the value of the address signal. When the output of the register 10 and the value of the address signal match, the output of the comparator 11 is H
And when they do not match, the output of the comparator 11 is L.

The AND gate 12 has three input terminals, the mode signal mo, the output of the AND gate 2 and the comparator 1.
When all the outputs of 1 are H, the output of the AND gate 12 becomes H. Otherwise, the output of AND gate 12 is L
Becomes The output of the AND gate 12 is supplied to the selector 23.

The AND gate 13 has three input terminals, the mode signal mo, the output of the AND gate 3 and the comparator 1.
When all the outputs of 1 are H, the output of the AND gate 13 becomes H. In other cases, the output of the AND gate 13 is L
Becomes The output of the AND gate 13 is supplied to the selector 22.

When the output of the AND gate 3 is H, the selector 18 outputs the memory 16 (word on even address).
Is supplied to the register 20, and when the output of the AND gate 3 is L, the output of the register 20 is supplied to the register 20 again. The register 20 holds the output of the selector 18 and supplies the held value to the selector 22.

The selector 19 outputs the output of the memory 17 (the word on the odd address) when the output of the AND gate 2 is H.
Is supplied to the register 21, and when the output of the AND gate 2 is L, the output of the register 21 is supplied to the register 21 again. The register 21 holds the output of the selector 19 and supplies the held value to the selector 23.

The selector 22 outputs the output of the register 20 when the output of the AND gate 13 is H, and outputs the output of the memory 16 (word of the corresponding address) when the output of the AND gate 13 is L.

The selector 23 outputs the output of the register 21 when the output of the AND gate 12 is H, and outputs the output of the memory 17 (word of the corresponding address) when the output of the AND gate 12 is L.

The selector 24 outputs the outputs of the selector 22 and the selector 23 as the data signal d1 and the data signal d0, respectively, when the least significant bit of the address signal is H (1 or an odd number). Conversely, when the least significant bit of the address signal is L (0, that is, even number), the selector 2
Reference numeral 4 outputs the outputs of the selector 22 and the selector 23 as a data signal d0 and a data signal d1, respectively.

Next, the operation will be described. When a 1-word load instruction and an aligned 2-word load instruction are received, the instruction decoder 30 (FIG. 1) causes the unaligned load signal 2
w, increment signal inc, decrement signal de
c and the mode signal mo are set to L.

The instruction decoder 3 is connected to the address bus between the instruction decoder 30 and the memory load control circuit 32.
0 sends out an address signal indicating the address corresponding to the required word. In the case of an alignment 2 word load instruction,
An address signal designating only the address of one word (the smaller even address) is transmitted.

In the case of the 1-word load instruction and the aligned 2-word load instruction, since the increment signal inc and the decrement signal dec are L, the memory load control circuit 32 shown in FIG.
The outputs of 12 and 13 and the OR gate 6 are L. Further, since the non-aligned load signal 2w is L and the output of the AND gate 1 is L, the selector 8 supplies the address signal to both the memories 16 and 17. Each of the memories 16 and 17 that has received the address signal from the selector 8 refers to bits other than the least significant bit of the address signal and reads the word of the corresponding address. As a result, two aligned words are read from the two memories 16 and 17.

Since the output of the OR gate 6 is L, the selector 9 supplies the read value from the register 10 to the register 10 again. Since the output of the AND gate 3 is L, the selector 18 supplies the read value from the register 20 to the register 20 again. Further, since the output of the AND gate 2 is L, the selector 19 supplies the read value from the register 21 to the register 21 again. That is, the values of the registers 10, 20, and 21 do not change.

Further, since the output of the AND gate 12 is L, the selector 23 supplies the output from the memory 17 to the selector 24. Since the output of the AND gate 13 is L, the selector 22 supplies the output from the memory 16 to the selector 24.

In the case of the aligned 2-word load instruction, the least significant bit of the address signal on the address bus is L (0, that is, even number). At this time, the selector 24 changes to the selector 22.
And the output of the selector 23 is output as the data signal d0 and the data signal d1, respectively. Therefore, the memory 16 for even addresses and the memory 17 for odd addresses are
2 words read from the data signal d0
And is output as a data signal d1. In this case, the data signal d0 is a word on an even address and the data signal d1 is a word on an odd address.

The instruction decoder 30 shown in FIG. 1 stores both of the data signals d0 and d1 on the data buses 34 and 35 in the register file 33. Therefore, two aligned words are loaded simultaneously. When loading three or more consecutive aligned words, the address generator 31 adds or subtracts 2 to the address signal (the least significant bit is 0) and sends the resulting address signal to the address bus. Then, it may be supplied to the memory load control circuit 32. In this way, a large number of addresses can be efficiently accessed by the increment or decrement (the increment or decrement is 2) inside the instruction decoder 30.

In the one-word load instruction in which an odd address is designated, the least significant bit of the odd address signal on the address bus is H (1), so that the selector 24 outputs the outputs of the selector 22 and the selector 23 to the data signal, respectively. It is output as d1 and the data signal d0. In this case, the data signal d0 is the word on the odd address from the memory 17, and the data signal d1 is the word on the even address from the memory 16. The instruction decoder 30 shown in FIG. 1 stores only the data signal d0 on the data bus 34 in the register file 33. Therefore, one of the two words read from the two memories 16 and 17 is selectively acquired.

On the other hand, in the one-word load instruction in which an even address is designated, the least significant bit of the even address signal on the address bus is L (0), so the selector 24
Outputs the outputs of the selector 22 and the selector 23 as a data signal d0 and a data signal d1, respectively.
In this case, the data signal d0 is the word on the even address from the memory 16 and the data signal d1 is the word on the odd address from the memory 17. The instruction decoder 30 shown in FIG. 1 has a data signal d0 on the data bus 34.
Are stored in the register file 33. That is, in the case of a 1-word load instruction, the word required as the data signal d0 is output regardless of whether it is an odd address or an even address, and the instruction decoder 30 stores the word in the register file 33.

Next, the operation when a non-aligned two-word load instruction without designation of post-increment or post-decrement is received will be described. In this case, the instruction decoder 30 (FIG. 1) sets the increment signal inc, the decrement signal dec and the mode signal mo to L.
The instruction decoder 30 uses the non-aligned load signal 2w to load the non-aligned word. In the first cycle of loading the first word first, the instruction decoder 30
Sets the non-aligned load signal 2w to L, and in the second cycle in which the second word is loaded next, the instruction decoder 30 sets the non-aligned load signal 2w to H.

In addition, in the non-aligned two-word load, the address generator 31 of the instruction decoder 30 addresses the address signal designating the smaller address of the first word of the two non-aligned words. It is sent to the bus and supplied to the memory load control circuit 32. Even in the second cycle, the address generator 31 does not change the address signal. Since it is not aligned, the address signal related to the first word is an odd number (eg addr), and the least significant bit is 1.
(H).

In this case, in the first cycle, the non-aligned load signal 2w, the increment signal inc, the decrement signal dec and the mode signal mo are L.
The memory load control circuit 32 shown in (1) operates similarly to the one-word load instruction. That is, since the non-aligned load signal 2w is L in the first cycle, the output of the AND gate 1 becomes L, and the selector 8 outputs the address signal to the memory 1
Supply to both 6 and 17. Receiving the address signal from the selector 8, each of the memories 16 and 17 refers to bits other than the least significant bit of the address signal and reads the word of the corresponding address (addr-1, addr). As a result, two aligned words are read from the two memories 16 and 17.

Since the least significant bit of the address signal on the address bus is H (1), the selector 24 uses the output of the selector 23 (the word on the odd address addr read from the memory 17) as the data signal d0. And outputs the output of the selector 22 (the word on the even address addr-1 read from the memory 16) to the data signal d.
Output as 1. The instruction decoder 30 shown in FIG.
In the first cycle, of the two aligned words, only the data signal d0 on the data bus 34 (the first word on the odd address addr) is stored in the register file 33.

Next, in the second cycle (load of the second word), the non-aligned load signal 2w becomes H, the address signal on the address bus does not change, and the least significant bit is 1.
Since it is (H), the output of the AND gate 1 becomes H. Therefore, the selector 8 supplies the odd address addr + 2, which is the output of the adder 15, to both the memories 16 and 17.
Each of the memories 16 and 17 that has received the odd address addr + 2 from the selector 8 refers to bits other than the least significant bit of the address signal and reads the word of the corresponding address. As a result, two aligned words from the two memories 16 and 17 (2 on the addresses addr + 1 and addr + 2)
(Word) is read. The second word to be loaded in the second cycle is the even address addr + 1 in the memory 16.
Bits above but above the least significant bit of the even address addr + 1 are the same as those of the odd address addr + 2.

Since the least significant bit of the address signal on the address bus is H (1), the selector 24 uses the output of the selector 23 (the word on the odd address addr + 2 read from the memory 17) as the data signal d0. Then, the output of the selector 22 (the word on the even address addr + 1 read from the memory 16) is output as the data signal d1. The instruction decoder 30 shown in FIG.
In the second cycle, among the two aligned words, the data signal d1 (even address addr +
Only the second word above 1) is stored in the register file 33. As a result, two words on the consecutive odd address addr and even address addr + 1 are loaded in two cycles.

Next, the operation when a non-aligned 2-word load instruction with post-increment designation is received will be described. In this case, the instruction decoder 30 (FIG. 1) sets the increment signal inc to H and decrements the signal d.
Let ec be L.

When loading the first two words, a continuous two-word load mode of loading two words in two cycles is carried out. Therefore, the instruction decoder 30 sets the mode signal mo to L.

The instruction decoder 30 also uses the unaligned load signal 2w. Similarly to the above, in the first cycle in which the first word is loaded first, the instruction decoder 30 sets the non-aligned load signal 2w to L, and in the second cycle in which the second word is loaded next, the instruction decoder 30 does not The alignment load signal 2w is set to H. In the subsequent cycles, the instruction decoder 30 sets the non-aligned load signal 2w to H.

In addition, in the non-aligned two-word load, the address generation unit 31 of the instruction decoder 30 addresses the address signal designating the smaller one of the first word of the two non-aligned words. It is sent to the bus and supplied to the memory load control circuit 32. Even in the second cycle, the address generator 31 does not change the address signal.

In this case, since the non-aligned load signal 2w is L in the first cycle, the output of the AND gate 1 becomes L in the memory load control circuit 32 shown in FIG. The address signal is supplied to both the memories 16 and 17. Each of the memories 16 and 17 that have received the address signal from the selector 8 refers to bits other than the least significant bit of the address signal, and applies the corresponding address (addr
Read the word (-1, addr). As a result, two aligned words are read from the two memories 16 and 17.

Since the mode signal mo and the decrement signal dec are L, the AND gates 2, 3, 1
2 and 13 and the outputs of the OR gates 4 and 6 become L and 1
In the same operation as the case of the word load instruction, the first word on the address addr is output as the data signal d0, and the word on the address addr-1 is output as the data signal d1. Instruction decoder 3 shown in FIG.
0 stores only the data signal d0 on the data bus 34 in the register file 33 in the first cycle.

Next, in the second cycle (loading of the second word), the non-aligned load signal 2w becomes H,
The outputs of OR gate 4, AND gate 2 and OR gate 6 change to H. In addition, the increment signal inc is H
Therefore, the selector 7 outputs +2 for the post increment and the selector 9 outputs the output value ad of the adder 14.
dr + 2 is supplied. Since the output of the OR gate 6 is H, the selector 9 sets the output value of the adder 14 to addr + 2.
Are stored in the register 10.

In the second cycle, the non-aligned load signal 2w becomes H, the address signal on the address bus does not change, and the least significant bit is 1 (H). Therefore, the output of the AND gate 1 becomes H. . Therefore, the selector 8 outputs the odd address addr + 2 output from the adder 15 to the memory 1
Supply to both 6 and 17. Each of the memories 16 and 17 receiving the odd address addr + 2 from the selector 8
By referring to bits other than the least significant bit of the address signal, the word of the corresponding address is read. As a result, two aligned words (address add
2 words on r + 1 and addr + 2) are read.

As described above, since the output of the AND gate 2 is H, the selector 19 stores the word on the odd address addr + 2 output from the memory 17 in the register 21. On the other hand, when the decrement signal dec is L and AN
Since the output of the D gate 3 remains L, the selector 18 supplies the read value from the register 20 to the register 20 again. Therefore, the value of the register 20 does not change.

Since the mode signal mo is L, AN
Since the outputs of the D gate 12 and the AND gate 13 are L, the outputs from the selectors 22 and 23 are the outputs of the memories 16 and 17, respectively. Since it is non-aligned access,
The least significant bit of the address signal on the address bus is H (1
That is, since it is an odd number, the selector 24 outputs the output of the selector 22 (the word at the even address addr + 1) and the output of the selector 23 (the word at the odd address addr + 2) as the data signal d1 and the data signal d0, respectively. The instruction decoder 30 shown in FIG.
Stores only the data signal d1 on the data bus 35 in the register file 33 in the second cycle. As a result, two words on the consecutive odd address addr and even address addr + 1 are loaded in two cycles.

At the end of the second cycle, the value held in the register 21 is updated to the word on the address addr + 2, and the value held in the register 10 is changed to the odd address addr.
It has been updated to +2.

After the end of the second cycle, the instruction decoder 30
Implements a simultaneous two-word load mode that loads two words in one cycle. Therefore, the instruction decoder 30 sets the mode signal mo to H. After the end of the second cycle, the instruction decoder 30 sets the non-aligned load signal 2w to H. The increment signal inc remains H and the decrement signal dec remains L. Then, the instruction decoder 30 sends an address signal indicating the odd address addr + 2 to the address bus and supplies it to the memory load control circuit 32.

Since the mode signal mo and the increment signal inc are H, in the memory load control circuit 32 of FIG. 2, the OR gate 4, the AND gate 2 and the OR gate 4 are connected.
The output of the gate 6 becomes H. Therefore, the selector 9 causes the register 10 to hold the output value addr + 4 of the adder 14.

Since the non-aligned load signal 2w is H, A
The output of the ND gate 1 becomes H, and the selector 8 supplies the output value addr + 4 of the adder 15 to both the memories 16 and 17. Receiving the output value addr + 4 from the selector 8, each of the memories 16 and 17 refers to a bit other than the least significant bit of the address signal, and applies the corresponding address (add
Read the word at r + 3, addr + 4).

Further, the register 1 supplied to the comparator 11
The output of 0 is the already stored addr + 2, which is equal to the value indicated by the address signal on the address bus, so that the output of the comparator 11 becomes H. However, since the decrement signal dec is L, the outputs of the AND gate 3 and the AND gate 13 remain L. On the other hand, since the mode signal mo, the output of the AND gate 2 and the output of the comparator 11 are H, the output of the AND gate 12 is H.

Therefore, the outputs of the selectors 22 and 23 are the output of the memory 16 (word at address addr + 3) and the word at address addr + 2 stored in the register 21, respectively. Since the least significant bit of the address signal on the address bus is H (1), the selector 2
4 outputs the word at address addr + 2 as the data signal d0 and the word at address addr + 3 as the data signal d1. The instruction decoder 30 shown in FIG.
Stores both of the data signals d0 and d1 on the data buses 34 and 35 in the register file 33. Therefore, two unaligned words can be loaded in one cycle.

As described above, since the output of the AND gate 3 is L, the selector 18 supplies the read value from the register 20 to the register 20 again. On the other hand, since the output of the AND gate 2 is H, the selector 19 supplies the output of the memory 17 (word on the address addr + 4) to the register 21. Therefore, the value of register 20 does not change, and register 2
The value of 1 is updated to the word on address addr + 4.

At the end of this third cycle, register 2
The held value of 1 is updated to the word on the address addr + 4, and the held value of the register 10 is the odd address addr.
It has been updated to dr + 4.

In the next cycle, the odd address addr
+4 is indicated by an address signal on the address bus. Addresses (addr + 5, addr) from memories 16 and 17
+6) word is read, but the selector 24 uses the word on the address addr + 4 as the data signal d0,
The word on the address addr + 5 is output as the data signal d1. The instruction decoder 30 shown in FIG. 1 stores both of the data signals d0 and d1 on the data buses 34 and 35 in the register file 33.

At the end of this fourth cycle, register 2
The held value of 1 is updated to the word on the address addr + 6, and the held value of the register 10 is the odd address addr.
It has been updated to dr + 6. Therefore, the instruction decoder 30
An internal increment of 2 (the increment is 2) allows efficient access to multiple addresses. As described above, two unaligned words can be efficiently loaded simultaneously.

Next, the operation when a non-aligned two-word load instruction with post decrement designation is received will be described. In this case, the instruction decoder 30 (FIG. 1) sets the decrement signal dec to H and increments the increment signal in
Let c be L.

When loading the first two words, a continuous two-word load mode of loading two words in two cycles is carried out. Therefore, the instruction decoder 30 sets the mode signal mo to L.

The instruction decoder 30 also uses the non-aligned load signal 2w. Similarly to the above, in the first cycle in which the first word is loaded first, the instruction decoder 30 sets the non-aligned load signal 2w to L, and in the second cycle in which the second word is loaded next, the instruction decoder 30 does not The alignment load signal 2w is set to H. In the subsequent cycles, the instruction decoder 30 sets the non-aligned load signal 2w to L.

In addition, in the non-aligned two-word load, the address generator 31 of the instruction decoder 30 addresses the address signal designating the smaller one of the first words of the two non-aligned words. It is sent to the bus and supplied to the memory load control circuit 32. Even in the second cycle, the address generator 31 does not change the address signal.

In this case, since the non-aligned load signal 2w, the mode signal mo and the increment signal inc are L in the first cycle, the memory load control circuit 32 shown in FIG. 2, AN
The outputs of the D gate 12 and the AND gate 13 become L. Further, since the mode signal mo is L, the output of the OR gate 5 becomes H, and since the decrement signal dec is H, the outputs of the AND gate 3 and the OR gate 6 become H.

Further, since the increment signal inc is L, the selector 7 is -2 for post-decrement.
And the output value of the adder 14 becomes addr-2.
Since the output of the OR gate 6 is H as described above, the selector 9 causes the register 10 to output the output value addr-2 of the adder 14.
To be stored.

In the first cycle, since the non-aligned load signal 2w is L, the output of the AND gate 1 becomes L in the memory load control circuit 32 shown in FIG.
The selector 8 supplies the address signal to both the memories 16 and 17. Each of the memories 16 and 17 that have received the address signal from the selector 8 refers to bits other than the least significant bit of the address signal, and applies the corresponding address (addr-
(1, addr) word is read. As a result, two aligned words are read from the two memories 16 and 17.

Since the output of the AND gate 2 is L as described above, the selector 19 supplies the read value from the register 21 to the register 21 again. Therefore, the value of the register 21 does not change. On the other hand, since the output of the AND gate 3 is H, the selector 18 stores the word on the even address addr−1 output from the memory 16 in the register 20.

Since the mode signal mo is L, AN
Since the outputs of the D gate 12 and the AND gate 13 are L, the outputs from the selectors 22 and 23 are the outputs of the memories 16 and 17, respectively. Since it is non-aligned access,
The least significant bit of the address signal on the address bus is H (1
That is, since it is an odd number, the selector 24 outputs the output of the selector 22 (word on the even address addr-1) and the output of the selector 23 (word on the odd address addr) to the data signal d1 and the data signal d0, respectively.
Output as. The instruction decoder 30 shown in FIG.
In the first cycle, the data signal d0 on the data bus 34
Are stored in the register file 33.

Next, in the second cycle (loading of the second word), the non-aligned load signal 2w becomes H,
The outputs of AND gate 1 and OR gate 4 change to H, and the outputs of OR gate 5 and AND gate 3 change to L. Since the increment signal inc is L, AN
The output of D gate 2 remains L. Therefore, the outputs of the OR gate 6, the AND gate 12, and the AND gate 13 are L.

In the second cycle, the non-aligned load signal 2w becomes H, the address signal on the address bus does not change, and the least significant bit is 1 (H). Therefore, the output of the AND gate 1 becomes H. . Therefore, the selector 8 outputs the odd address addr + 2 output from the adder 15 to the memory 1
Supply to both 6 and 17. Each of the memories 16 and 17 receiving the odd address addr + 2 from the selector 8
By referring to bits other than the least significant bit of the address signal, the word of the corresponding address is read. As a result, two aligned words (address add
2 words on r + 1 and addr + 2) are read.

As described above, since the outputs of the OR gate 6 and the AND gates 3 and 2 are L, the values of the registers 10, 20 and 21 are not changed by the selectors 9, 18 and 19. Moreover, since the outputs of the AND gates 12 and 13 are L,
The outputs of the selectors 22 and 23 are the memory 16 respectively.
And 17 outputs. Since it is non-aligned access,
Since the access is non-aligned access, the least significant bit of the address signal on the address bus is H (1 or an odd number), so that the selector 24 outputs the selector 22 (the word on the even address addr + 1) and the output of the selector 23. (Word on odd address addr + 2) is output as data signal d1 and data signal d0, respectively. The instruction decoder 30 shown in FIG.
Only the data signal d1 on the data bus 35 is stored in the register file 33. As a result, two words on the consecutive odd address addr and even address addr + 1 are loaded in two cycles.

At the end of the first cycle and the end of the second cycle, the value held in register 20 is an even address ad.
The word on dr-1 has been updated, and the value held in register 10 has been updated to odd address addr-2.

After the end of the second cycle, the instruction decoder 30
Implements a simultaneous two-word load mode that loads two words in one cycle. Therefore, the instruction decoder 30 sets the mode signal mo to H. After the end of the second cycle, the instruction decoder 30 sets the non-aligned load signal 2w to L. The decrement signal dec remains H and the increment signal inc remains L. Then, the instruction decoder 30 sends an address signal indicating the odd address addr-2 to the address bus and supplies it to the memory load control circuit 32.

Mode signal mo, increment signal in
Since c is H, the memory load control circuit 3 of FIG.
2, the OR gate 5, the AND gate 3, and the OR gate 6
Output becomes H. Therefore, the selector 9 causes the register 10 to hold the output value addr-4 of the adder 14.

Since the non-aligned load signal 2w is L, A
The output of the ND gate 1 becomes L, and the selector 8 supplies the address value addr-2 indicated by the address signal on the address bus to both the memories 16 and 17. Receiving the output value addr-2 from the selector 8, each of the memories 16 and 17 refers to a bit other than the least significant bit of the address signal to find the corresponding address (addr-3, addr-2).
Read the word.

In addition, the register 1 supplied to the comparator 11
The output of 0 is the already stored addr-2, which is equal to the value indicated by the address signal on the address bus, so the output of the comparator 11 becomes H. However, since the increment signal inc is L, the outputs of the AND gate 2 and the AND gate 12 remain L. on the other hand,
Mode signal mo, output of AND gate 3 and comparator 1
Since the output of 1 is H, the output of the AND gate 13 is H
Becomes

Therefore, the outputs of the selectors 22 and 23 are the addresses add stored in the register 20, respectively.
The word on r-1 and the output of memory 17 (address a
The word on ddr-2). Since the least significant bit of the address signal on the address bus is H (1), the selector 2
4 outputs the word on address addr-2 as the data signal d0 and the word on address addr-1 as the data signal d1. The instruction decoder 30 shown in FIG.
Stores both of the data signals d0 and d1 on the data buses 34 and 35 in the register file 33. Therefore, two unaligned words can be loaded in one cycle.

As described above, since the output of the AND gate 2 is L, the selector 19 supplies the read value from the register 21 to the register 21 again. On the other hand, since the output of the AND gate 3 is H, the selector 18 supplies the output of the memory 16 (word on the address addr-3) to the register 20. Therefore, the value of register 21 does not change, and register 2
The value of 0 is updated to the word at address addr-3.

At the end of this third cycle, register 2
The held value of 0 is updated to the word on the address addr-3, and the held value of the register 10 is the odd address addr-3.
It has been updated to dr-4.

In the next cycle, the odd address addr
-4 is indicated by the address signal on the address bus. From the memories 16 and 17, addresses (addr-5, addr
-4) word is read, but the selector 24 uses the word on the address addr-4 as the data signal d0,
The word at the address addr-3 is output as the data signal d1. The instruction decoder 30 shown in FIG. 1 stores both of the data signals d0 and d1 on the data buses 34 and 35 in the register file 33.

At the end of this fourth cycle, register 2
The held value of 1 is updated to the word on the address addr-5, and the held value of the register 10 is the odd address addr-5.
It has been updated to dr-6. Therefore, the instruction decoder 30
The decrement (decrement is 2) inside of allows efficient access to many addresses. As described above,
Two non-aligned words can be loaded efficiently at the same time.

As described above, according to the first embodiment, when the consecutive non-aligned words are loaded by the register indirect addressing of the post-increment or post-decrement method, the contents of the memory and the register 2 are stored.
In the case where the coherency of 0 and 21 is maintained,
By setting the mode signal mo to H, non-aligned 2-word loading which normally takes 2 cycles can be performed in 1 cycle. Also, it is not necessary to specify each address in order to load two unaligned words. Therefore, when loading a large number of non-aligned words on a large number of consecutive addresses, it is possible to improve the loading efficiency.

Since a large number of parts are provided in a single circuit and the circuit operates properly and automatically in response to various signals, automatic operation of the circuit is possible even with simple control. It is possible to efficiently load two non-aligned words simultaneously. Further, the memory unit includes a first memory 16 to which even addresses are assigned and a second memory 17 to which odd addresses are assigned,
Since the two words corresponding to the bits higher than the least significant bit of one input address are read from the memories 16 and 17, respectively, the words can be efficiently read from the memories 16 and 17, Even if the reading method is not changed, the selectors 22 and 23 automatically select two non-aligned words in cooperation with each other, so that the control method does not have to be complicated.

Further, in this embodiment, the non-aligned 2
When loading one word from memory, a non-aligned load signal that fluctuates based on the number of times the memory is accessed.
The instruction decoder 30 generates w, and the non-aligned load signal 2w
Based on the above, the selector 8 selects the address designated by the address generator 31 or the address resulting from the addition by the adder 15, and outputs the value of the selected address. Therefore, the selector 8 can reliably and automatically select an address according to the number of times of access, and it is possible to automatically read two properly aligned words based on the value of the address output by the selector 8. Is.

Further, in this embodiment, when two unaligned words are loaded, the selector 7 for adding +2 or −2 to the address designated by the address generator 31 and the selector 7 for adding are added. The register 10 for storing the resulting address, the comparator 11 for comparing the address already stored in the register 10 by the previous access, and the address currently designated by the address generator 31 are provided, and the comparison by the comparator 11 is performed. Selector 2 when the results match
2 and 23 cooperate to select two unaligned words from the words already stored in the register 20 or the register 21 in the previous access and the two words of the aligned read currently read. . Therefore, based on the comparison result by the comparator 11, the selectors 22 and 23 can appropriately process the word already stored in the register 20 or the register 21 and the currently read two words of the alignment. is there.

Further, according to this embodiment, a circuit or software (instruction bit string) for monitoring the coherency of the values of the register 20 and the memory 16 or the register 21 and the memory 17 when two unaligned words are loaded. And a flag setting unit that sets a flag (mode signal) that fluctuates according to the flag, and that switches the selectors 22 and 23 between valid and invalid based on the flag.
Gates 12 and 13 are provided. Therefore, when loading two unaligned words, register 20 and memory 1
6, or the selectors 22 and 23 can be appropriately switched to valid or invalid according to a circuit or software (which generates an instruction bit string) that monitors the coherency between the values of the register 21 and the memory 17.

In the above-described embodiment, the single instruction decoder 30 generates all of the address signal, the mode signal mo, the unaligned load signal 2w, the increment signal inc and the decrement signal dec, and stores them in the memory. It is supplied to the load control circuit 32. However, these signals may be generated by a plurality of devices or supplied to the memory load control circuit 32 from a plurality of devices. For example, the flag or mode signal mo may be stored in a special register and supplied to the memory load control circuit 32 from the special register. In this case, the setting and clearing of the mode signal mo in the register may be performed by the instruction decoder 30 or another device under the control of software, or may be performed based on the operation of another circuit.

Further, in the above-described embodiment, the two data buses 34 and 35 for outputting the data signals d0 and d1 from the memory load control circuit 32 are provided, but the data signals d0 and d1 can be identified. Thus, only one data bus may be provided.

As described above, the loaded word is stored in the register file 33 such as a general-purpose register. However, without intending to limit the present invention to the embodiment, the loaded word may be stored in another type of storage device, for example, a data memory.

[0117]

As described above, according to the present invention, the address designating unit is based on the first adding unit for adding 2 to the address designated by the address designating unit and the number of accesses to the memory unit. Output by the first selection unit capable of selecting the address specified by or the address resulting from the addition by the first addition unit and outputting the value of the selected address, and the first selection unit. Based on the value of the read address, the reading unit that reads out two aligned information portions from the two addresses in the memory unit, and the reading unit that reads 2
A first storage for storing one of the two information parts; an information part already stored in the first storage by a previous access to the memory part; and an alignment currently read by the reading part. Since it is configured as a data processing device having a second selection section capable of selecting two non-aligned information sections from the information section, a large number of non-aligned sections on a number of consecutive addresses are arranged. When loading a fixed word, it is possible to improve the loading efficiency.

According to the present invention, the memory section, the first adding section, the first selecting section, the reading section, the first storing section and the second selecting section are provided in a single circuit, and the memory The section has a first memory assigned an even number of addresses,
The reading unit is provided with a second memory to which an odd number of addresses is assigned, and the reading unit stores two information portions corresponding to bits higher than the least significant bit of one input address in the first memory and the first information. Since it is configured to read from each of the two memories, even with simple control, it is possible to efficiently load two non-aligned words simultaneously by the automatic operation of the circuit. In addition, the information portion can be efficiently read from the first memory and the second memory, and the second selection unit automatically performs two non-alignment operations without changing the reading method. Since the information part is selected, there is an effect that the control method does not have to be complicated.

According to the present invention, when the two non-aligned information portions are loaded from the memory unit, the non-alignment that varies depending on the circuit or software that monitors the identity of the values in the first storage unit and the memory. A first selection unit based on the non-aligned load signal.
Since the address designated by the address designating unit or the address obtained as the result of addition by the first adding unit is selected and the value of the selected address is outputted, it can be performed reliably and automatically according to the number of accesses. First, the first selection unit can select the address, and the reading unit can automatically read the two properly aligned information portions based on the value of the address output by the first selection unit. There are some effects.

According to the present invention, when the two non-aligned information portions are loaded from the memory portion, the second addition portion for adding +2 or -2 to the address designated by the address designation portion, The second storage unit that stores the address of the result added by the second addition unit, the address that has already been stored in the second storage unit by the previous access to the memory unit, and the address currently designated by the address designation unit. A comparing unit that compares the address with the address, and when the comparison result by the comparing unit matches, the second
The selection unit of the non-alignment 2 from the information portion already stored in the first storage unit by the previous access to the memory unit and the two information portions of the alignment currently read by the reading unit.
Since the two information parts are configured to be selected, the second selection part, based on the comparison result by the comparison part, the information part already stored in the first storage part and the alignment currently read by the reading part. It is possible to appropriately process the two information parts of the storage device.

According to the present invention, when two non-aligned information portions are loaded from the memory unit, a circuit that monitors the sameness of the values in the first storage unit and the memory or a flag that varies depending on software is set. Since it is configured to include a flag setting unit for switching and a switching unit for switching the second selection unit between valid and invalid based on the flag, access is performed when two unaligned information portions are loaded from the memory unit. According to the number of times, there is an effect that the second selection unit can be appropriately switched to valid or invalid.

[Brief description of drawings]

FIG. 1 is a block diagram showing a digital signal processor which is a data processing device according to a first embodiment of the present invention.

FIG. 2 is a circuit diagram showing details of a memory load control circuit in FIG.

FIG. 3 is a schematic diagram showing the concept of address allocation to the memory in FIG.

[Explanation of symbols]

1-3 AND gates, 4-6 OR gates, 7, 9,
18, 19, 24 selectors, 8 selectors (first selection unit), 10 registers (second storage unit), 11 comparators (comparison unit), 12, 13 AND gates (switching unit),
14 adder (second adding section), 15 adder (first adding section), 16 memory (memory section, reading section, first
Memory, 17 memory (memory unit, reading unit, second memory), 20, 21 registers (first storage unit), 22, 23 selector (second selection unit), 30
Instruction decoder (instruction section, flag setting section), 31 address generation section (address designation section), 32 memory load control circuit, 33 register file, 34, 35 data buses.

Claims (5)

[Claims] 1. A memory unit having a plurality of addresses designated by a binary number and storing an information part in association with each address, and an address to be accessed in the memory unit, one at a time. An address designation unit that can be designated and that can add or subtract 2 to the address designated in the previous access and that can be designated in the next access; and add 2 to the address designated by the address designation unit Based on the number of accesses to the first adding unit and the memory unit, the address designated by the address designating unit or the address resulting from the addition by the first adding unit is selected and selected. A first selection unit capable of outputting an address value; and an arrangement from two addresses in the memory unit based on the address value output by the first selection unit. A reading unit that reads two information portions, a first storage unit that stores one of the two information portions read by the reading unit, and a first storage unit that has been accessed by a previous access to the memory unit. From the already stored information part and the two information parts of the alignment that are currently read by the reading unit, the non-alignment of 2
And a second selection unit capable of selecting one information section. 2. A memory section, a first adding section, a first selecting section, a reading section, a first storing section, and a second selecting section are provided in a single circuit, and the memory section comprises: First assigned an even address
Memory and a second memory to which an odd number of addresses are assigned, and the reading unit stores two information parts corresponding to bits higher than the least significant bit of one input address. The data processing device according to claim 1, wherein the data is read from each of the first memory and the second memory. 3. When loading two non-aligned information portions from a memory unit, a non-aligned load signal that fluctuates by a circuit or software that monitors the identity of the values of the first storage unit and the memory is generated. And a first selecting unit selects an address designated by the address designating unit or an address resulting from addition by the first adding unit based on the non-aligned load signal 2w, 2. The value of the selected address is output.
Alternatively, the data processing device according to claim 2. 4. A second adder unit for adding +2 or −2 to the address designated by the address designation unit when the two non-aligned information portions are loaded from the memory unit, and the second addition unit. A second storage unit for storing an address of a result added by the unit, an address already stored in the second storage unit by a previous access to the memory unit, and an address currently designated by the address designating unit. And a second comparison unit that compares the comparison result of the comparison unit with each other, the second selection unit stores the information portion already stored in the first storage unit by the previous access to the memory unit. And the two information parts of the alignment that are currently read by the reading unit,
4. The data processing device according to claim 1, wherein one information part is selected. 5. A flag setting unit for setting a flag that is changed by a circuit or software that monitors the sameness of the values of the first storage unit and the memory when the two non-aligned information portions are loaded from the memory unit. 5. The data processing device according to claim 4, further comprising: a switching unit that switches the second selection unit between valid and invalid based on the flag.