JP2001256104A - Information processor - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide an information processor capable of being applied even to a general purpose bus system, reducing the processing loads of a CPU, improving the using efficiency of a bus and effectively accessing access non-continuous addresses. SOLUTION: In a conversion table 14, the actual addresses of registers in a register group 9 are made to correspond to continuous rearrangement addresses. Whether or not the DMA transferred address inside an address buffer 12 is the rearrangement address is judged in a high-order address decoder 13, and when it is the rearrangement address, the conversion table 14 is referred to and the actual address of the register made to correspond to the address is outputted. The actual address is converted to a register selection signal in an address decoder 15 and the register in the register group 9 selected by the register selection signal is accessed. When DMA transfer is performed to the continuous rearrangement addresses, even the non-continuous registers can be continuously accessed.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an information processing apparatus which receives an address and data from the outside and transfers data according to the address.

[0002]

2. Description of the Related Art In recent years, as the degree of integration of semiconductor devices has increased, the functions mounted on one device have also increased.
Accordingly, the number of internal registers and the like tends to increase. Generally, a device is designed for each internal functional module. Therefore, a plurality of internal registers are usually assigned addresses collectively for each function. FIG. 6 is an explanatory diagram of an example of an address map of an internal register of the device. In the example shown in FIG. 6, I / O, D
I / O for controlling each function such as MA
Register groups such as a control register group, a DMA control register group,... Are provided. And
A continuous address area is assigned to a register group for each function. If you use a device,
Necessary settings are made by software for a plurality of registers necessary for operating the device. Thus, the device can perform a predetermined operation.

However, the registers that must be set to operate the device are not necessarily all registers, and there are also registers whose setting order is defined. Therefore, for example, register 1 and register 4 are set, register 3 is set twice, register 5 is set, and so on.
As described above, there is a case where setting must be performed for discrete addresses which are discrete. Conventionally, when setting is performed on registers arranged at such discontinuous addresses, each setting is performed one by one using a CPU.

FIG. 7 is a block diagram showing an example of a system configuration including a conventional information processing apparatus. In the figure, 1 is CP
U, 2 is a memory, 3 is a host bus, 4 is a bus bridge,
Reference numeral 7 denotes a system bus, 8 denotes an information processing device, and 9 denotes a register group. The CPU 1 and the memory 2 are connected to a host bus 3, and an information processing device 8 is connected to a system bus 7 via a bus bridge 4.

In a system having such a configuration, generally, devices requiring high speed, such as the CPU 1 and the memory 2, are connected to the host bus 3 having a high operating frequency, and peripheral devices such as the information processing device 8 are not used. It is connected to a system bus 7 having a low operating frequency. The information processing device 8 has a register group 9 for performing various settings. Unless these register groups 9 are set, the information processing device 8 cannot perform a desired operation.

As in the prior art, an access such as reading or writing to the register group 9 of the information processing device 8 or the like connected to the low-speed system bus 7 using the CPU 1 requires the processing occupation time of the CPU 1. Becomes longer.
Therefore, the processing capabilities of the CPU 1 and the host bus 3 are reduced. In addition, for example, as the number of registers that need to be set every time in a certain processing cycle increases, the load on the CPU 1 increases, leading to a decrease in throughput and a decrease in bus use efficiency, and the effects thereof cannot be ignored. .

As a method of solving this problem, there is a method of increasing the operating frequency of the system bus 7 first. System bus 7
By increasing the operating frequency of the
The occupation time of the CPU 1 when accessing the above device is reduced. However, at the same time, there is a problem of mounting noise such as crosstalk, which makes it difficult to improve.

As another improvement method, use of burst transfer or DMA (direct memory access) transfer is known. The burst transfer is a transfer method in which, in data reading and writing, one head address is designated to continuously access addresses subsequent to that address. FIG. 8 is an explanatory diagram of an example of an access cycle by the CPU and an access cycle by the burst transfer. In the figure, 'A' is an address phase,
'D' indicates a data phase. As shown in FIG. 8A, the normal access cycle of the CPU 1
Outputs one address and one corresponding data to the host bus 3. Then, the output address and data are output to the system bus 7 via the bus bridge 4, and one data corresponding to one address is output to the information processing device 8. Such an access cycle is repeated.

In the burst transfer, the master (in this case, C
PU1) merely designates the start address, and the slave (target) side fetches data while automatically incrementing the address to access the data. As shown in FIG. 8B, the CPU 1 outputs the head address and the following four data. Also when the data is output to the system bus 7 via the bus bridge 4, one head address and four data are continuously output. For example, the information processing device 8 that receives the data receives the head address and stores four data in consecutive addresses from that address.

As can be seen by comparing FIGS. 8A and 8B, since a plurality of address phases are omitted in the burst transfer, the bus can be used more efficiently in the burst transfer even with the same number of data transfers. . Recently, devices capable of burst transfer have been increasing for speeding up. However, this burst transfer is effective only for continuous addresses, and when addresses are not continuous, the burst transfer method itself cannot be used.

[0011] DMA transfer is a method of performing transfer without the intervention of a CPU. FIG. 9 is a block diagram showing an example of a system using the conventional DMA transfer, and FIG. 10 is a flowchart showing an example of the same operation. FIG.
FIG. 3 is an explanatory diagram of an example of a bus cycle when DMA transfer is used. In the figure, the same parts as those in FIG. 6 are denoted by the same reference numerals. 6 is a DMA controller, 41 is a transfer source address register, 42 is a transfer destination address register, 43 is a transfer size register, 44 is a transfer source storage area, and 45 and 4
7 is a transfer area, and 46 is a transfer destination storage area. In this example, the transfer source storage area 44 connected to the host bus 3
Is transferred to a transfer area 47 in a transfer destination storage area 46 connected to the system bus 7.

The DMA controller 6 has a transfer source address register 41, a transfer destination address register 42, and a transfer size register 43. The transfer source address register 41 stores a transfer area 45 in the transfer source storage area 44.
Holds the address of The transfer destination address register 4
2 holds the address of the transfer area 47 in the transfer destination storage area 46. Further, the transfer size register 43 holds the amount of data to be transferred.

First, the CPU 1 sets the start address of the transfer area 45 in the transfer source storage area 44 in the transfer source address register 41 provided in the DMA controller 6 in S101. In S102, the start address of the transfer area 47 in the transfer destination storage area 46 is set in the transfer destination address register 42. Further, S103
In, the transfer data amount to be transferred is set in the transfer size register 43. After the setting of the data in the three registers is completed, when the DMA controller 6 is activated in S104, the DMA controller 6 starts the transfer. When the data is transferred in S105, it is determined in S106 whether or not the transfer has been completed by the transfer data amount set in the transfer size register 43. If the transfer data amount has not reached the set transfer data amount, the address is incremented. Returning to S105, the data transfer is repeated. When the transfer amount set in the transfer size register 43 has been transferred, the DMA transfer ends.

By the above operation, the bus cycle becomes as shown in FIG. That is, first, after an access by setting to a register in the DMA controller 6 by the CPU 1 (here, three accesses for setting data to three registers) occurs, the DMA controller 6 transfers data one by one. Will be As described above, by using the DMA transfer, the data transfer is performed by the DMA controller 6, so that the load on the CPU 1 is reduced correspondingly, and the CPU 1 can perform other processing.

There is also a method called a DMA burst transfer method in which burst transfer and DMA transfer are combined. FIG. 12 is an explanatory diagram of an example of a bus cycle in the DMA burst transfer method. After setting in the DMA controller 6 by the CPU 1, in this example, four data are successively transferred following one address. With this method, the load on the CPU 1 is reduced, and the bus use efficiency is improved.

In such a DMA transfer or a DMA burst transfer, transfer is sequentially performed from a designated head address, so that it is very effective to transfer a large amount of data in a continuous address area to a continuous address area. . However, if the address is discontinuous and the amount of transfer at one time is small, the DMA at the boundary where the address is discontinuous is used.
The operation is completed, and the setting to the register of the DMA controller and the restart processing must be performed for each boundary.
FIG. 13 is a flowchart showing an example of an operation when performing a DMA transfer to a discontinuous area in an example of a conventional system using the DMA transfer. The same parts as those in FIG. 10 are denoted by the same reference numerals. The transfer data amount set in the transfer size register 43 in 103 is the data amount of a portion where addresses are continuous among the data to be transferred. In S106, it is determined whether or not the transfer of the continuous data has been completed. It will be determined. When the data transfer is completed for the transfer area where the addresses are continuous, S1
At 11, it is determined whether the transfer has been completed for all the transfer areas. If an untransferred area remains, S
Return to 101. In this case, in order to perform the transfer for the next transfer area, the transfer source address, the transfer destination address, and the data amount in which the addresses are continuous must be set again. Therefore, if there are many boundaries where addresses are discontinuous, the setting by the CPU 1 is redone each time, and even if DMA is used, the effect is not sufficiently exhibited.

In order to solve the above-mentioned problem of the conventional DMA transfer, for example, Japanese Patent Application Laid-Open No. 7-6116 discloses a DMA control circuit for efficiently performing a DMA transfer to an area where addresses are discontinuous. It is shown. FIG. 14 is a block diagram showing another example of a system using the conventional DMA transfer, and FIG. 15 is a flowchart showing an example of the same operation. In the figure, the same parts as those in FIG. 9 and the steps performing the same operations as in FIG. 10 are denoted by the same reference numerals. 42
-1 to 42-n are transfer destination address registers;
47-n is a transfer area. In this configuration, the start addresses of the transfer areas 47-1 to n in the plurality of discontinuous transfer destination storage areas 46 are set in the transfer destination address registers 42-1 to n provided in the DMA controller 6. It is something to keep.

As shown in FIG. 15, the operation in this configuration is as follows. After the transfer source address is set in the transfer source address register 41 in S101, the transfer area 47-in the transfer destination storage area 46 is set in S102-1 to S102-n. The head addresses 1 to n are sequentially set in the transfer destination address registers 42-1 to 42-n. Further, after setting the transfer data amount in S103,
At 104, the DMA is started. Thus, the DMA transfer in S105 is performed without stopping the DMA until the transfer data amount is reached.

As described above, according to the configuration shown in FIG.
Even in a DMA transfer to a discontinuous area, a plurality of transfer destination addresses can be set first, so that a transfer can be performed without stopping the DMA transfer operation even at a discontinuous boundary between transfer destination addresses. However, it is necessary to start after setting all the transfer destination addresses, and there is a problem that setting overhead in the CPU 1 is large. Also, the DMA controller 6
The number of transfer destination address registers that can be provided in the CPU is limited, and when the discontinuous area becomes large, it is necessary to reset and restart the CPU via the CPU 1 as well. Further, there is a problem that a special DMA controller is required and the DMA controller is not general-purpose.

All of the above-mentioned techniques are effective for discontinuous areas having a certain size, and are used for transferring data of discontinuous addresses such as registers in byte units or word units. Has no effect at all.

As another technique, for example, Japanese Patent Laid-Open No.
Japanese Patent No. 60750 discloses a DMA transfer method capable of performing a DMA transfer even if the addresses of a transfer source and a transfer destination are discontinuous. FIG. 16 is a block diagram showing still another example of the system using the conventional DMA transfer. In the figure, 51 is an MPU, 52 is a CPU,
53 is a DMA controller, 54 is a ROM, 55 is RA
M and 56 are address converters, 57 is a selector circuit, 58
Is an internal bus, 59 is a common bus, 60 to 62 are memories, 6
Reference numerals 3 and 64 are conversion tables. The main control unit is a CPU 5
2 and a DMA controller 53 (denoted as DMAC), an MPU 51, a ROM 54, a RAM 55, an address converter 56, and a selector circuit 57, which are interconnected by an internal bus 58.

In the ROM 54 as a table storage,
Conversion tables 63 and 64 are stored at least. The conversion table 63 stores a first transfer pattern for converting continuous transfer destination addresses supplied by the DMA controller 53 into discontinuous real addresses for accessing the memories 60 to 62. The conversion table 64 stores continuous transfer source addresses supplied from the DMA controller 53 in a plurality of memories 60 to 62.
Is stored in a second transfer pattern for converting a non-consecutive real address to be accessed.

The address conversion unit 56 uses a single conversion table 63 or 64 set from the ROM 54 to
The transfer destination address and the transfer source address supplied from the DMA controller 53 are converted into real addresses. When the CPU 52 accesses the memories 60 to 62, the selector circuit 57 supplies the address output from the CPU 52 supplied from the internal bus 58 to the common bus 59, and supplies the real address supplied from the address conversion unit 56 during DMA transfer. Switch to supply to common bus 59.

With these configurations, when a continuous address is output from the DMA controller 53, the address is converted into a real address by the address conversion unit 56. Therefore, even if the real address is discontinuous, for example, DMA transfer is performed. be able to.

However, even if this method is used,
A special hardware configuration such as the main control unit in FIG. 16 is required and cannot be applied to, for example, a general-purpose bus system. In addition, if the device configuration connected to the bus is different, the conversion table must be rewritten. further,
Since the addresses output on the common bus 59 are discontinuous addresses, it is not possible to apply the burst transfer technique to the devices on the common bus 59, and there is a problem that the bus use efficiency is low.

[0026]

SUMMARY OF THE INVENTION The present invention has been made in view of the above-mentioned circumstances, and can be applied to a general-purpose bus system. It is an object of the present invention to provide an information processing apparatus capable of improving efficiency and effectively accessing discontinuous addresses.

[0027]

According to the present invention, the address management means associates the real addresses of the storage means with a plurality of consecutive relocation addresses different from the real addresses of the storage means such as registers. Managing. Then, the storage unit is sequentially accessed by a real address corresponding to a relocation address received from the outside or a real address corresponding to a relocation address continuous from the received relocation address. Thus, for example, when a continuous relocation address is received by DMA transfer or the like, the storage unit can be accessed even with a discontinuous address as a real address. Also, when performing burst transfer, real addresses corresponding to successive relocation addresses are sequentially accessed from the received relocation addresses.
Even though the relocation addresses are continuous, the associated real addresses may be discontinuous, and the storage means of the discontinuous addresses can be accessed even during burst transfer.

With such a configuration, even when accessing a register having a discontinuous address in a unit of, for example, one byte or one word, the register may be associated with a continuous relocation address in the order of access. As a result, even a discontinuous real address can be handled by a continuous relocation address, and DMA transfer and burst transfer can be performed.
It is clear that such a DMA transfer or burst transfer reduces the processing load on the CPU and improves the bus use efficiency. Note that when performing DMA transfer or burst transfer, the DMA controller and the bus system may be left as they are, so that their versatility is not impaired.

The correspondence between the reallocation address and the real address managed by the address management means can be managed by, for example, a look-up table. Further, it is possible to provide an address decoder for converting a real address into a selection signal for selecting any of the plurality of storage units, and to access the actual storage unit using the selection signal. Further, such conversion from the relocation address to the selection signal can be performed by a plurality of decoding means.
The setting of the correspondence between the reallocation address and the real address using the look-up table and the setting of the reallocation address corresponding to the selection signal output from the decoding means can be configured to be externally performed.

[0030]

FIG. 1 is a block diagram showing an example of a system including a first embodiment of an information processing apparatus according to the present invention. In the figure, the same parts as those in FIG. 7 are denoted by the same reference numerals. 5 is a line buffer, 6 is a DMA controller, 11 is a data buffer, 12 is an address buffer,
13 is an upper address decoder, 14 is a conversion table, 1
5 is an address decoder. In the system shown in FIG. 1, a CPU 1 and a memory 2 are connected to a host bus 3, and an information processing device 8 is connected from the host bus 3 to a system bus 7 via a bus bridge 4. Here, the bus bridge 4 is connected to a DMA controller 6 (DMAC).
) And a line buffer 5.

The information processing device 8 includes a data buffer 11 and an address buffer 12, an upper address decoder 13, a conversion table 14, an address decoder 15, and a register group 9 which constitute address management means. The data buffer 11 holds data sent via the system bus 7 or holds data read from the register group 9. The address buffer 12
Holds the address sent via the system bus 7.

The upper address decoder 13 decodes the upper bits of the address transferred through the system bus 7 and stored in the address buffer 12, and determines whether the address is a real address or a relocation address. In this example, as will be described later, it is assumed that the real address and the relocation address are mapped to different address spaces in which the upper bits of the address are different.

The conversion table 14 holds a relocation address and a real address in association with each other. In this example, it is constituted by a look-up table (LUT), and can be dynamically rewritten by access from the CPU 1, for example. FIG. 2 is an explanatory diagram of an example of the conversion table. 'H' in the figure indicates a hexadecimal number. Here, the number of registers in the register group 9 is shown as eight. Of course, the number of registers is arbitrary. As described above, the real address and the relocation address are mapped to different address spaces in which the upper bits of the address are different, and can be mapped, for example, as shown in FIG. In this example, the address whose fifth digit is “0” in hexadecimal is the real address, and the address which is “1” is the relocation address. Of course, the mapping in both address spaces can be determined arbitrarily. Each register in the register group 9 is assigned to a real address. In this example, each register has a data length of 4 bytes,
A real address is assigned to each register for every four addresses.

One of the registers of the register group 9 can be associated with the relocation address. At this time, for example, the registers can be arranged according to the order in which the software accesses the registers. For example, registers can be rearranged in the order of access, such as accessing register 1 after accessing register 2, accessing register 2 again, and then accessing register 7. The example shown in FIG. 2A shows an example in which registers are rearranged so as to realize this order.
The registers are rearranged in the order of register 1, register 2, register 7,... The order of the registers to be relocated is arbitrary, as in this example, and the same register can be relocated to a different relocation address.

In order to realize the register arrangement in the relocation address space in FIG.
A correspondence table as shown in FIG. In this correspondence table, the relocation address and the real address of the register relocated to the address are registered as a pair. The conversion table 14 implements this correspondence table.
For example, it can be configured by an LUT or an associative memory that outputs a real address with a relocation address as an input.

By using such a conversion table 14, software can use a relocation address and, if a continuous relocation address is accessed, access to a register assigned to a discontinuous real address. Can be. For example, in the example shown in FIG. 2, if the access is made sequentially from the relocation address' 10000h ', the real addresses'00004h','00000h','000
.. real addresses such as 04h ',' 00018h ',... Are output, and the registers are accessed in the order of register 2, register 1, register 2, register 7,. By accessing consecutive relocation addresses in this way, any register can be accessed,
For example, registers can be accessed in an arbitrary order by DMA transfer or burst transfer.

The address decoder 15 converts the conversion table 1
4 converted to the real address or the system bus 7
And decodes the address selected by the upper address decoder 13 out of the addresses transferred through the address buffer 12 and stored in the address buffer 12, and outputs a register selection signal. The register in the register group 9 is selected by the register selection signal, and the data in the data buffer 11 can be written to the selected register or the data can be read from the selected register to the data buffer 11. If the registers in the register group 9 can be accessed with the real addresses unchanged, the conversion to the register selection signal by the address decoder 15 is unnecessary, and the real addresses converted by the conversion table 14 or Any of the addresses transferred via the system bus 7 and stored in the address buffer 12 may be selected and output according to an instruction from the upper address decoder 13.

Next, the operation of the first embodiment of the information processing apparatus of the present invention when data is written to the register group 9 using DMA transfer will be described. The CPU 1 writes data necessary for register setting in a certain continuous area in the memory 2 as a transfer source in the register setting order. Thereafter, similarly to the operation described with reference to FIG.
The start address of the data transfer source memory 2 is set for the controller 6, the start address of the transfer destination relocation address is set, and the transfer size is set. Then, by activating the DMA controller 6, the DMA transfer is activated.

After the start of the DMA transfer, first the DM transfer
The A controller 6 issues a read cycle of the host bus 3 to the memory 2 and fetches data into the line buffer 5 of the bus bridge 4. Thereafter, the DMA controller 6 generates a write cycle of the system bus 7 and enters an operation of transferring data in the line buffer 5 to a register of the information processing device 8.

In the information processing device 8, data and addresses transferred by a write cycle of the system bus 7 are stored in an internal data buffer 11 and an address buffer 12.
To hold. The upper address decoder 13 determines whether the transferred address is a real address area or a relocation address area based on the upper bits of the address held in the address buffer 12. If the address is in the relocation address area, the real address associated with the address is output to the internal address bus by referring to the conversion table 14. If the transferred address is an address in the real address area, the transferred address is output to the internal address bus without referring to the conversion table 14.

The address output to the internal address bus is decoded by the address decoder 15 and a register selection signal is output. The data held in the data buffer 11 is written to the register in the register group 9 selected by the register selection signal.

These series of operations are repeated by the amount of transfer data set in the DMA controller 6 without the intervention of the CPU 1, and writing to the register is performed continuously. Of course, the DMA controller 6 also only performs a normal DMA transfer operation. The bus cycle when performing the above-described DMA transfer is the same as that in FIG. 11 described above.

When the same setting is performed on the register again, the DMA controller 6 needs to be reset and activated. Further, when changing the set value, only the value stored at a predetermined address in the memory 2 needs to be changed, and the CPU 1 does not directly access the register. Therefore, the CPU 1 can operate efficiently.

FIG. 3 is an explanatory diagram of a specific example of an operation when data is written to the register group 9 using DMA transfer in the first embodiment of the information processing apparatus of the present invention. Here, it is assumed that the content shown in FIG. 2B is stored in the conversion table 14. The CPU 1 is configured as shown in FIG.
As shown in (1), data is stored in the memory 2 in the order of register access. In this example, the registers are accessed in the order of the register 2, the register 1, the register 2, the register 7,..., And the data to be written at each access is stored in the memory 2 in the access order.

Then, for the DMA controller 6,
The start address of the data shown in FIG. 3A is set as the transfer source address, the relocation address '10000h' is set as the transfer destination address, the transfer data amount is set, and activation is performed. Then, the DMA controller 6 operates to transfer data to continuous addresses in the relocation address space as shown in FIG. However, in practice, the relocation address is converted into a real address by the conversion table 14 in the information processing device 8, and the corresponding register is selected. Therefore, FIG.
3C, an access to the register occurs and data is written. In this example, as desired, the registers are accessed in the order of register 2, register 1, register 2, register 7,..., And data is written.

Next, the operation of the first embodiment of the information processing apparatus according to the present invention when data is written to the register group 9 using burst transfer will be described. The burst transfer is a method in which, in reading and writing data, one head address is designated to continuously access addresses subsequent to that address. here,
It is assumed that the DMA controller 6 and the information processing device 8 have a burst transfer function. In the information processing device 8,
To realize the burst transfer function, the address buffer 1
2 has a function of automatically updating the address in 2. For example, when performing data transfer in units of 4 bytes per word, it is assumed that a function of incrementing the address in the address buffer 12 by 4 for each data transfer is provided.

The CPU 1 writes data necessary for register setting in a certain continuous area in the memory 2 serving as a transfer source in the register setting order. Thereafter, as in the operation described with reference to FIG. 10, the start address of the memory 2 serving as the data transfer source is set for the DMA controller 6, and
Set the start address of the relocation address to be the transfer destination,
Set the transfer size. Then, the DMA controller 6
, The DMA transfer is activated.

After the DMA transfer is started, first the DM transfer
The A controller 6 issues a burst read cycle of the host bus 3 to the memory 2 and fetches data of a burst size into the line buffer 5 of the bus bridge 4.
Thereafter, the DMA controller 6 generates a burst write cycle of the system bus 7 and enters an operation of transferring data in the line buffer 5 to a register of the information processing device 8.

In the information processing device 8, the start address and the first data are held in the internal address buffer 12 and data buffer 11 by the burst write cycle of the system bus 7. Then, based on the upper bits of the address stored in the address buffer 12, the upper address decoder 13 determines whether the address is in the real address area or in the relocation address area. If the address stored in the address buffer 12 is an address in the relocation address area, the real address associated with the relocation address is output to the internal address bus with reference to the conversion table 14. If the transferred address is an address in the real address area, the transferred address is output to the internal address bus without referring to the conversion table 14.

The address output to the internal address bus is decoded by the address decoder 15 and a register selection signal is output. The data held in the data buffer 11 is written to the register in the register group 9 selected by the register selection signal.

Thereafter, the address of the address buffer 12 is updated. For example, when performing data transfer in units of one word and four bytes, the address of the address buffer 12 is incremented by four. Further, the next write data is fetched into the data buffer 11, and the same operation is repeated by a pipeline method. In this way, for the data of the burst size, the data can be written to the register of the real address corresponding to the relocation address while updating the address of the address buffer 12.

When transferring data larger than the burst size, the DMA controller 6 only needs to transfer the first address of the transfer destination of the next data to be burst-transferred and transfer the data of the burst size again. In this manner, data transfer for each burst size can be repeatedly performed.

These series of operations are repeated by the amount of transfer data set in the DMA controller 6 without the intervention of the CPU 1, and writing to the registers in the register group 9 is performed. Of course, the DMA controller 6
Also performs only the normal DMA burst transfer operation.
The bus cycle when performing the above-described DMA transfer is the same as that in FIG.

When the same setting is again performed on the register, the DMA controller 6 may be reset and activated. When changing the set value, only the value stored at a predetermined address in the memory 2 needs to be changed. Therefore, the CPU 1 does not directly access the register, and can operate the CPU 1 efficiently. In addition, by using the relocation address, even if the register address that needs to be accessed is discontinuous, it can be handled with a continuous address, so that burst transfer can be used,
The bus can be used efficiently.

FIG. 4 is a block diagram showing an example of a system including an information processing apparatus according to a second embodiment of the present invention. In the figure, the same parts as those in FIG. 21 is a decoding unit, and 22 is a decoding block. In the second embodiment, as the address management means, instead of the LUT format conversion table 14 and the address decoder 15 in the first embodiment described above,
An example in which a decoding unit 21 is provided is shown.

In the system shown in FIG. 4, the CPU 1 is connected to the host bus 3 similarly to the system shown in FIG.
And a memory 2, and an information processing device 8 is connected from the host bus 3 to the system bus 7 via the bus bridge 4. Here, the bus bridge 4 is a DMA
A controller 6 (denoted as DMAC) and a line buffer 5 are provided.

The information processing device 8 includes a data buffer 11 and an address buffer 12, a decoding unit 21 constituting address management means, and a register group 9. The data buffer 11 holds data sent via the system bus 7 or holds data read from the register group 9. The address buffer 12
Holds the address sent via the system bus 7.

The decoding section 21 has a decoding block 22 corresponding to each register in the register group 9. FIG. 5 is a block diagram illustrating a configuration example of a decoding block. In the figure, 31 is a real address decoder, 3
2 is a relocation address decoder. The decode block 22 includes one real address decoder 31 and one or more rearranged address decoders 32. If no relocation address is required, the relocation address decoder 32 may be omitted. The number of relocation address decoders 32 depends on the number of times of access to the corresponding register when setting the register. That is, when the same register is accessed m times by the relocation address at the time of register setting, m relocation address decoders 32 are provided. The real address decoder 31 and the rearranged address decoder 32 in one decoding block 22 output a register selection signal for selecting a register corresponding to the decoding block 22. Therefore, if the real address decoder 31 or any of the relocation address decoders 32 determines that the decoded address is associated with the corresponding register, the register selection signal for selecting the corresponding register Is output. With such a decoding block 22, a real address and one or a plurality of relocation addresses are managed for one register, and a register selection signal is generated.

The decoding section 21 has such decoding blocks 22 as many as the number of registers. In the second embodiment, the real address and the relocation address are managed by the decoding unit 21. This decoding unit 21
Thus, each register in the register group 9 can be accessed with a real address and a continuous relocation address.

The decoding section 21 may be fixed or rewritable. Further, in the case of a changeable configuration, for example, a plurality of decode blocks 22 may be prepared and switched by register setting or the like.

Next, the operation of an example of a system including the information processing apparatus according to the second embodiment of the present invention will be described. Here, a description will be given assuming that the real address map and the relocation address map of the register group 9 in the information processing device 8 are the same as those in the example shown in FIG.

First, an example of the operation when data is written to a register using DMA transfer will be described. Note that the process from setting to activation of the DMA controller 6 is the same as in the first embodiment, and a description thereof will be omitted. DM
After the start-up A, the DMA controller 6 issues a read cycle of the host bus 3 to the memory and takes in the data into the line buffer 5 of the bus bridge 4. After that, DMA
The controller 6 generates a write cycle of the system bus 7 and transfers the data in the line buffer 5 to the information processing device 8.
The operation to transfer to the register is started.

In the information processing device 8, addresses and data are held in the internal address buffer 12 and data buffer 11 by a write cycle of the system bus 7. Based on the address held in the address buffer 12, the decoding unit 21 decodes the real address or the relocated address, and generates a register selection signal. That is, the address held in the address buffer 12 is input to each of the decode blocks 22 in the decode unit 21 and supplied to the real address decoder 31 and one or a plurality of rearranged address decoders 32 in each of the decode blocks 22. . Then, a register selection signal for a corresponding register is output from the decoding block 22 in which the decoded real address decoder 31 or the relocation address decoder 32 exists. Then, the data held in the data buffer 11 is written to the register selected by the register selection signal.

These series of operations are repeated by the amount of transfer data set in the DMA controller 6 without the intervention of the CPU 1, and writing to the register is performed continuously. Of course, the DMA controller 6 also has a normal D
Only the operation of MA transfer is performed. The bus cycle when performing the above-described DMA transfer is the same as that in FIG. 11 described above.

When the same setting is performed on the register again, the DMA controller 6 may be reset and the DMA controller 6 may be started. Further, when changing the set value, only the value stored at a predetermined address in the memory 2 needs to be changed, and the CPU 1 does not directly access the register. Therefore, the CPU 1 can operate efficiently.

Next, an example of the operation when the burst transfer is used will be described. Here, it is assumed that the DMA controller 6 and the information processing device 8 have a burst transfer function. The information processing device 8 has a function of automatically updating the address in the address buffer 12 in order to realize the burst transfer function. For example, when performing data transfer in units of 4 bytes per word, it is assumed that a function of incrementing the address in the address buffer 12 by 4 for each data transfer is provided. When this burst transfer is performed, the process from setting to activation of the DMA controller 6 is the same as that in the first embodiment, and a description thereof will be omitted.

After the DMA is started, the DMA controller 6 issues a burst read cycle of the host bus 3 to the memory 2 and fetches data of the data burst size into the line buffer 5 of the bus bridge 4. After that, DMA
The controller 6 generates a burst write cycle of the system bus 7 and starts an operation of transferring the data to a register of the information processing device 8.

In the information processing device 8, the start address and the first data are stored in the internal address buffer 12 and the data buffer 1 by the burst write cycle of the system bus 7.
Hold at 1. Then, the address held in the address register 12 is decoded by the decoding unit 21. This decoding operation is the same as in the case of the DMA transfer. A register selection signal for a corresponding register is output from the decode block 22 in which the real address decoder 31 or the rearranged address decoder 32 which can decode the address held in the address buffer 12 exists.
Then, the data held in the data buffer 11 is written to the register selected by the register selection signal.

Thereafter, the address of the address buffer 12 is updated. For example, when performing data transfer in units of one word and four bytes, the address of the address buffer 12 is incremented by four. Further, the next write data is fetched into the data buffer 11, and the same operation is repeated by a pipeline method. In this manner, for the data of the burst size, the data can be written to the register of the real address (register selection signal) corresponding to the relocation address while updating the address of the address buffer 12.

When transferring data larger than the burst size, the DMA controller 6 only needs to transfer the first address of the transfer destination of the next data to be burst-transferred and transfer the data of the burst size again. In this manner, data transfer for each burst size can be repeatedly performed.

These series of operations are repeated by the amount of transfer data set in the DMA controller 6 without the intervention of the CPU 1, and writing to the registers in the register group 9 is performed. Of course, the DMA controller 6
Also performs only the normal DMA burst transfer operation.
The bus cycle when performing the above-described DMA transfer is the same as that in FIG.

When the same setting is performed on the register again, the DMA controller 6 needs to be reset and activated. When changing the set value, only the value stored at a predetermined address in the memory 2 needs to be changed. Therefore, the CPU 1 does not directly access the register, and can operate the CPU 1 efficiently. In addition, by using the relocation address, even if the register address that needs to be accessed is discontinuous, it can be handled with a continuous address, so that burst transfer can be used,
The bus can be used efficiently.

In each of the above-described embodiments, the case where data is written to the register group 9 is described as an operation example. However, when data is read from the register group 9, access can be similarly performed. Of course, data read out by burst transfer or DMA transfer using the relocation address can be transferred to the outside.

In each of the above embodiments, the register group 9 is actually accessed by the register selection signal. However, the present invention is not limited to this. Good.

In each of the above embodiments, the register group 9 is shown as a plurality of storage means, but the present invention is not limited to this. The plurality of storage means may include a storage area that can be individually accessed by a plurality of addresses (or selection signals), and is not limited to a register, and may be configured by a storage device such as a DRAM or an SRAM. Is also good. In such a case, the plurality of storage means may be one entity, or may be integrated into one chip together with other units, and the configuration is arbitrary.

[0076]

As is apparent from the above description, according to the present invention, by providing an address management means having an address conversion table (and an address decoder) or a decoding unit on the information processing apparatus side, the rearranged address can be obtained. The address of the storage means in the information processing apparatus can be rearranged so that the addresses are continuous in the order of register setting performed by software. This makes it possible to access the registers arranged at discrete addresses with continuous addresses, and to operate the CPU and bus efficiently. Further, such an address management unit can be easily added to the information processing apparatus, and a circuit change and an increase in circuit resources can be suppressed. In addition, since only a change is made to the information processing device connected to the bus, it is also necessary to introduce a general-purpose bus system or a system using a DMA controller without changing the conventional bus system or DMA controller. Can be.

Further, since the address of the internal storage means can be rearranged by the address management means in accordance with the order of register setting performed by software or the like, a special DMA controller or the like is not required. In such a system, a transfer method such as burst transfer or DMA transfer can be used. For example, if you use burst transfer,
Since the bus overhead is reduced, the bus can be used efficiently. If DMA transfer is used, C
Since the PU does not need to be interposed, the load on the CPU is reduced. Further, by using the DMA burst transfer, it is possible to improve the bus use efficiency and reduce the load on the CPU. Also, if DMA transfer is used, for example, when setting a register, the CPU only needs to access a memory available for the cache.
The CPU can operate at high speed, and the occupation time of the CPU can be reduced.

As described above, the present invention can be realized without changing the conventional bus system, and
And the bus utilization efficiency can be improved.

[Brief description of the drawings]

FIG. 1 is a block diagram illustrating an example of a system including an information processing apparatus according to a first embodiment of the present invention.

FIG. 2 is an explanatory diagram of an example of a conversion table.

FIG. 3 is an explanatory diagram of a specific example of an operation when writing data to a register group 9 using DMA transfer in the first embodiment of the information processing apparatus of the present invention.

FIG. 4 is a block diagram showing an example of a system including an information processing apparatus according to a second embodiment of the present invention.

FIG. 5 is a block diagram illustrating a configuration example of a decoding block.

FIG. 6 is an explanatory diagram of an example of an address map of an internal register of a device.

FIG. 7 is a block diagram illustrating an example of a system configuration including a conventional information processing apparatus.

FIG. 8 is an explanatory diagram of an example of an access cycle by a CPU and an access cycle by burst transfer.

FIG. 9 is a block diagram illustrating an example of a system using a conventional DMA transfer.

FIG. 10 is a flowchart illustrating an example of an operation in an example of a conventional system using DMA transfer.

FIG. 11 is an explanatory diagram of an example of a bus cycle when DMA transfer is used.

FIG. 12 is an explanatory diagram of an example of a bus cycle in a DMA burst transfer method.

FIG. 13 is a flowchart showing an example of an operation when performing a DMA transfer to a discontinuous area in an example of a conventional system using a DMA transfer.

FIG. 14 is a block diagram showing another example of a system using the conventional DMA transfer.

FIG. 15 is a flowchart showing an example of an operation in another example of the system using the conventional DMA transfer.

FIG. 16 is a block diagram showing still another example of a system using the conventional DMA transfer.

[Explanation of symbols]

DESCRIPTION OF SYMBOLS 1 ... CPU, 2 ... memory, 3 ... host bus, 4 ... bus bridge, 5 ... line buffer, 6 ... DMA controller, 7 ... system bus, 8 ... information processing apparatus, 9 ... register group, 11 ... data buffer, 12 ... Address buffer, 13 upper address decoder, 14 conversion table, 15 address decoder, 21 decoding unit, 22
... Decode block, 31 ... Real address decoder, 32
... Relocation address decoder, 41 ... Transfer source address register, 42, 42-1 to 42-n ... Transfer destination address register, 43 ... Transfer size register, 44 ... Transfer source storage area, 45, 47, 47-1 to 47 −n: transfer area, 46
... Transfer destination storage area, 51 ... MPU, 52 ... CPU, 53
... DMA controller, 54 ... ROM, 55 ... RAM,
56 ... address converter, 57 ... selector circuit, 58 ... internal bus, 59 ... common bus, 60-62 ... memory, 63,
64 conversion table.

 ────────────────────────────────────────────────── ─── Continuing on the front page (72) Inventor Kazuhito Konno 2274 Hongo, Ebina-shi, Kanagawa Prefecture F-Xerox Co., Ltd. F-term (reference) 5B060 AB04 AB09 AB17 5B061 DD01 FF05 RR02 RR03

Claims (8)

[Claims] 1. An information processing apparatus for receiving an address from outside and performing data transfer, comprising: a plurality of storage units each having a real address and capable of storing data received from outside;
A real address corresponding to a reallocation address received from the outside or a reallocation address received is managed by associating a real address of the storage means with a plurality of continuous reallocation addresses different from the real address of the storage means. An information processing apparatus comprising address management means for sequentially accessing real addresses corresponding to successive relocation addresses from the first address. 2. The information processing apparatus according to claim 1, wherein said address management means has a look-up table in which said reallocation address is associated with said real address. 3. The address management means includes an address decoder for converting the real address into a selection signal for selecting one of the plurality of storage means, and accessing the storage means using the selection signal. The information processing apparatus according to claim 1, wherein the information processing apparatus performs the processing. 4. The apparatus according to claim 1, wherein said address management means is configured to be able to externally set a correspondence between said relocation address and said real address. An information processing apparatus according to claim 1. 5. The address management means includes a plurality of decoding means for receiving the relocation address as input and outputting a selection signal for selecting one of the plurality of storage means, and corresponding to the real address. 2. The storage unit is accessed by using the selection signal.
An information processing apparatus according to claim 1. 6. The information processing apparatus according to claim 5, wherein the address management unit is configured to be able to externally set the relocation address corresponding to the selection signal. 7. A data transfer to and from the outside is carried out continuously by burst transfer, and when receiving a relocation address as an address of burst transfer, the address management means starts from the relocation address. 7. The data transfer method according to claim 1, wherein real addresses associated with successive relocation addresses are sequentially accessed to transfer data to and from said storage means.
The information processing device according to item. 8. The data transfer with the outside is performed continuously by DMA transfer, and when the address management means receives a relocation address as a DMA transfer address, the address management means responds to the relocation address. 8. The information processing apparatus according to claim 1, wherein an access is made to the assigned real address, and data transfer with the storage unit is performed.