JPH05189360A - Data transfer and storage system - Google Patents

Abstract

PURPOSE:To shorten time for access and time for waiting for a bus and a memory with competition by transferring/storing data by compressing it every time of burst transfer operation on a bus. CONSTITUTION:The system is provided with data compression means 1-3, 2-3 and data extension means 1-4, 2-4, which can compress/extend data every time of burst transfer operation in the case of burst transfer in a bus between processors 1, 2 and a memory 3 so as to transfer data between the processors 1, 2 and the memory 3. In this case, the system is also provided with a compression data transfer requirement signal and a compressing data response signal selecting the presence/absence of data compression at the time of burst transfer and a bit storing the presence/absence of the compression of data stored in the memory 3.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a data transfer system between a processor and a memory in an information processing apparatus and a data storage system in the memory.

[0002]

2. Description of the Related Art Conventionally, in transferring data between a processor and a memory, one word of data is often transferred in one transfer cycle. In this case, there is no need for data compression for each transfer cycle. Further, even in the case of burst transfer in which data transfer of a plurality of words is performed in one transfer cycle, data compression is not performed for each transfer cycle.

[0003]

In recent years, with the high integration and high speed of ICs, the operating speed of the processor has been remarkably improved, and the difference in operating speed from the memory has been increasing. Therefore, in order to supply a large amount of data to the processor at high speed, it is necessary to read and write more data in one memory access, and burst transfer is performed in which data transfer of multiple words is performed in one transfer cycle. It is necessary. For example, 4 in one burst transfer cycle
When there is word data transfer and data is supplied every clock based on the clock used by the processor, the memory must read four words and sequentially transfer every clock. However, in general, a memory requires a time of several clocks or more for one access, and therefore, in order to supply data for each clock, it is necessary to read four words of data simultaneously by one memory access. .. As for the amount of hardware constituting the memory, in contrast to the memory configuration of single word access, it is necessary to prepare a memory for four words in the case of burst transfer, and there is a problem that the physical quantity becomes large. Next, when the data transfer interval is widened and the data is supplied every several clocks, the amount of hardware can be reduced as compared with the case where the data transfer is performed every one clock, but one data transfer cycle is for memory and data transfer. There was a problem that the time to occupy the bus would be long. In the case of a multiprocessor configuration in which multiple processors use the same bus for memory access, the time during which one processor performs a data transfer cycle to the memory is Will be waiting until you can use. That is, there is a problem that the waiting time becomes longer as the data transfer cycle becomes longer.

[0004]

A data transfer and storage system of the present invention has a processor and a memory in an information processing apparatus, and in data transfer between the processor and the memory, a plurality of words of data are transferred in one transfer operation. When performing burst transfer that can be transferred, a data compression unit and a data expansion unit that can compress and expand data for each burst transfer operation are provided between the processor and the system bus, and a special data transfer cycle is activated for data compression and expansion. Rather, data compression is performed during the burst transfer write cycle of the processor, and data decompression is performed during the burst transfer read cycle, so that one burst transfer operation is performed on the system bus during data transfer between the processor and memory. It occupies a short time. In the data transfer method according to another invention of the present invention, in the above-mentioned one, in the data transfer in the burst transfer operation between the processor and the memory, there is provided a selection means for selecting the presence / absence of data compression, By compressing and transferring only data having a compression effect, the data transfer overhead due to compression and decompression is reduced. A data transfer method according to yet another invention of the present invention is the burst invention according to the second invention, further comprising storage means for storing the presence or absence of compression of the data stored in the memory used in the data transfer method. Even if the data to be transferred is compressed data, writing and reading are performed without decompression, so that the time required for one-time data writing and reading is shortened when the data is compressed.

[0005]

In the present invention, data is compressed and transferred and stored for each burst transfer operation on the bus, and the presence or absence of data compression is selected.

[0006]

FIG. 1 is a block diagram showing an embodiment of the present invention. In FIG. 1, 1 and 2 are processors, 3 is memory, and 4 is 10 ports. These processors 1, 2,
The 10 ports 4 and the memory 3 are connected to the system bus 5, and the processors 1 and 2 access the memories 3, 10 ports 4 and the like through the system bus 5. In addition,
The processor 1 and the processor 2 operate independently, and the memory 3 can be arbitrarily accessed.

The processor 1 includes a microprocessor 1-1 for processing data, a local bus 1-2 which is a bus unique to the microprocessor 1-1, and a data compression section 1-3 for compressing write data. , A data decompression unit 1-4 for decompressing read data, and a data selector 1-5 for switching between compressed data and normal data.
, A bus buffer 1-6 that connects the system bus 5 and the data selector 1-5, and a bus control unit 1-7 that controls access to the system bus 5 by the microprocessor 1-1.
And a compression instruction signal 1-8 for instructing data compression by the microprocessor 1-1 and a compression completion signal 1-9 for indicating success or failure of compression.

The processor 2 includes a microprocessor 2-1 for processing data, a local bus 2-2 which is a bus unique to the microprocessor 2-1, a data compression section 2-3 for compressing write data, and a read operation. A data decompression unit 2-4 for decompressing data, a data selector 2-5 for switching between compressed data and normal data, a bus buffer 2-6 for connecting the system bus 5 and the data selector 2-5, and a microprocessor. 2-1 is a bus control unit 2-7 for controlling access to the system bus 5, a compression instruction signal 2-8 for instructing the microprocessor 2-1 to compress data, and a compression completion signal 2 for indicating success or failure of compression. -9, and has the same configuration as the processor 1.

The memory 3 includes a storage element 3-1 and a storage element 3-.
2 has a two-bank (BANK) configuration, and the read data generation unit 3-4 performs error check and correction of the data read from the storage element 3-1 or the storage element 3-2 and outputs the data to the system bus 5 and the compressed data. Read signal 3-
The presence or absence of data compression is output to 7, and the write data generation unit 3
-5 adds the compressed data storage signal 3-6 output from the memory control section 3-3 to the data received from the system bus 5 to generate a check bit for error detection, and stores the storage element 3-1 or the storage element 3-. 2, and the memory control unit 3-3 performs these controls. The storage format of the storage element 3-1 and the storage element 3-2 is an explanatory diagram showing a configuration example of one word stored in the memory. As shown in FIG. 2, one word has 40 bits, and the storage data 312 has 32 bits. The bit, the compressed data storage flag 311 is 1 bit, and the check bit 310 is 7 bits wide.

The data compressing unit 1-3, the data decompressing unit 1-4, the data compressing unit 2-3, and the data decompressing unit 2-4 in the processors 1 and 2 are capable of compressing and expanding data for each burst transfer operation. In the data transfer between the processors 1 and 2 and the memory 3, when the burst transfer capable of transferring the data of a plurality of words is performed in the data transfer between the processors 1 and 2, the data compressing means and the data decompressing means are constituted. Between the processor and the system bus, data compression is performed during the write cycle of burst transfer of the processor and data is not read during the read cycle of burst transfer without activating a special data transfer cycle for data compression and decompression. Once when performing data transfer between the processor and memory by performing decompression Burst transfer operation is configured to shorten the time to occupy the system bus.

Further, the data selector 1-5 and the data selector 2-5 in the processors 1 and 2 constitute selection means for selecting the presence / absence of data compression at the time of data transfer, and the burst transfer operation between the processor and the memory is performed. In the data transfer, the above-mentioned selecting means is provided so that only the data having a compression effect is compressed and transferred, thereby reducing the data transfer overhead due to the compression and expansion. Further, the storage elements 3-1 and 3-2 in the memory 3 constitute storage means for storing the presence / absence of compression of the data stored in the memory used in the data transfer method, and the burst transfer data may be compressed data. By performing writing and reading without decompression, the time required for one-time data writing and data reading is shortened when the data is compressed.

FIGS. 3 to 6 are time charts provided for explaining the operation of FIG. 1, and FIG. 3 is a time chart for reading data that has not been compressed according to the present invention from the memory. 4 is a time chart in the case of reading the data compressed by the present invention from the memory, FIG. 5 is a time chart in the case of writing the data in the memory without the data compression according to the present invention, and FIG. 6 is the present invention. 6 is a time chart when data is compressed and written in a memory.

The operation of the embodiment shown in FIG. 1 will be described below with reference to FIGS. The processor 1 and the processor 2 have the same function and the same operation. Therefore, the operation will be described below for the processor 1 unless otherwise specified. Microprocessor 1 in processor 1
-1 is 4 words, one word per clock in one access
Burst transfer is performed so that the data can be read and written once, and accordingly, the system bus 5 and the memory 3 also perform burst transfer. Then, the data compression unit 1-3, assuming that the 4-word data transferred in the burst transfer is α, β, γ, and δ in order,
When α and β are equal and γ and δ are equal, αc = α =
β and βc = γ = δ, α and β are represented by αc, and γ and δ
Is represented by βc to output αc and βc to the data selector 1-5, and when α ≠ β or γ ≠ δ, α,
The β, γ, and δ are sequentially output to the data selector 1-5. If the two-word data transferred in the compressed data transfer are set as αc and βc in this order, the data decompression unit 1-4 sets αc and β.
Data of 4 words, α, β, γ, and δ are restored from c and output to the microprocessor 1-1.

Next, the actual operation will be described. First, the memory 3 of the processor 1 when data compression is not performed
The operation of reading data from will be described. FIG. 3 is a time chart in this case. From address A, α, β,
This is the case of reading γ and δ. Microprocessor 1
-1 indicates the address A by burst transfer from the address A,
The data at address A + 1, address A + 2, and address A + 3 are read. First, the microprocessor 1-1 is the local bus 1
-2 outputs the address A and outputs an access request to the bus control unit 1-7. The bus control unit 1-7 constantly monitors the state of the system bus 5, and when the processor 2 is not using the system bus 5, issues an access request to the memory 3 and outputs the address A to the system bus 5. Then
The memory 3 receives a read request from the address A from the system bus 5. As a result, the memory control unit 3-3
Reads the content αm of address A from the storage element 3-1 and passes it to the read data generation unit 3-4. Next, the data generator 3-4 performs error check and correction of αm, generates read data α and presence / absence of compression, outputs the generated read data α to the system bus 5, and outputs the compressed data read signal 3- 7 is set to "L" to notify the memory control unit 3-3 that the read data is not compressed. As a result, the memory control unit 3-3 sets the data response signal 5-1 to "L" and the compressed data response signal 5-2 to "H", and A +
The content βm at address 1 is read from the storage element 3-2, and A +
The content γm at address 2 is read from the storage element 3-1 and A +
The content δm at address 3 is read from the storage element 3-2, and the read data generation unit 3-4 sets it as β, γ, δ and the system bus 5
Output to. At this time, the bus control unit 1-7 sequentially fetches the data α, β, γ, δ from the system bus 5 because the data response signal 5-1 of the system bus 5 is “L”.
Since the compressed data response signal 5-2 at this time is "H", it is directly supplied from the bus buffer 1-6 to the microprocessor 1-1 through the read data data selector 1-5 and the local bus 1-2. In this case, the system bus 5 consumes 9 clocks to read 4-word data, the microprocessor 1-1 consumes 10 clocks, and the memory 3 consumes 9 clocks. The above is the read operation when the compression is not performed.

Next, a data read operation from the memory 3 of the processor 1 when the data compression is performed will be described. FIG. 4 is a time chart in this case, and shows a case where α, β, γ, and δ are read from the address A. The microprocessor 1-1 performs the burst transfer from the address A to the addresses A, A + 1, A + 2, A
Read the data at address +3. First, the microprocessor 1-1 outputs the address A to the local bus 1-2 and makes an access request to the bus control unit 1-7. The bus control unit 1-7 constantly monitors the state of the system bus 5. When the processor 2 is not using the system bus 5, the bus controller 1-7 makes an access request to the memory 3 and sends an address A address to the system bus 5. The memory 3 receives the read request from the address A from the system bus 5.
As a result, the memory control section 3-3 causes the memory element 3-1
The content αm of the address is read and the read data generation unit 3-4
Pass to. The read data generation unit 3-4 performs error check and correction of αm, generates read data αc and presence / absence of compression, outputs the generated read data αc to the system bus 5, and outputs the compressed data read signal 3-7. It is set to "H" and the memory control unit 3-3 is notified that the read data is compressed. Then, the memory controller 3-3 sets the data response signal 5-1 to "L" and the compressed data response signal 5-2 to "L", reads the content βm at address A + 1 from the storage element 3-2, Read data generator 3-
4 is set to βc, which is output to the system bus 5. This completes the read operation of the memory 3. At this time, the bus control unit 1-7
Means that the data response signal 5-1 of the system bus 5 is "L", so that the data .alpha.c and .beta.c are sequentially fetched from the system bus 5, and the compressed data response signal 5-2 at this time is "L" and is read. The data is supplied to the data decompression unit 1-4 through the data selector 1-5, and the data decompression unit 1-4 restores αc, βc to α, β, γ, δ and sequentially supplies them to the microprocessor 1-1. in this case,
The system bus 5 consumes 5 clocks to read 4-word data, the microprocessor 1-1 consumes 9 clocks, and the memory 3 consumes 5 clocks. The above is the read operation when the compression is performed.

Next, a data write operation from the processor 1 to the memory 3 when data compression is not performed will be described. FIG. 5 is a time chart in this case, where α, β, γ, and δ are written from the address A. The microprocessor 1-1 performs the burst transfer from the address A to the addresses A, A + 1, A + 2, A
The data α, β, γ, δ at the +3 address is output. First, the microprocessor 1-1 outputs the address A to the local bus 1-2, sets the compression instruction signal 1-8 to "H",
An access request for writing data without compression is issued to the bus control unit 1-7. From the bus controller 1-7 microprocessor 1-1, address A and write data α, β,
When γ and δ are stored in the data buffer 1-6 and the system bus 5 is not used by the processor 2, the memory 3
Access request to the system bus 5, the address A is output to the system bus 5, the compressed data supply signal 5-3 is set to “H”,
Output the data α. After that, each time the data response signal 5-1 becomes “L”, the next data β, γ, δ is sequentially output. Next, the memory 3 receives the address A from the system bus 5.
Receiving write request from address, data response signal 5-
1 is set to "L", and since the compressed data supply signal 5-3 is "H", the four-word data α, β, γ, δ are fetched into the write data generator 3-5, and the compressed data storage signal 3-6 is stored. A check bit is generated together with the value to generate write data αm, βm, γm, δm. Memory control unit 3-
3 writes to the storage element 3-1 and the storage element 3-2 twice each. In this case, it takes 7 clocks by the system bus 5 to write 4 words of data, and the microprocessor 1
-1 consumes 5 clocks, and the memory 3 consumes 9 clocks.
The above is the write operation when compression is not performed.

Next, a data write operation from the processor 1 to the memory 3 when data compression is performed will be described. FIG. 6 is a time chart in this case, where α, β, γ, and δ are written from the address A.
The microprocessor 1-1 performs the burst transfer from the address A to the addresses A, A + 1, A + 2, A + 3.
Outputs data α, β, γ, δ to the address. First, the microprocessor 1-1 outputs the address A to the local bus 1-2, sets the compression instruction signal 1-8 to "L", and issues an access request for compressing and writing data to the bus control unit 1-.
Go to 7. The bus control unit 1-7 receives from the microprocessor 1-1 the address A and the write data α, β,
γ and δ are stored in the data buffer 1-6, and the data compression unit 1
The write data α, β, γ, and δ are stored in -3, and whether or not the data compression is possible is determined. If the data compression is possible, the data compression is performed, the compression completion signal 1-9 is set to "L", and the data compression availability is determined. If it is determined that compression is impossible, the compression completion signal 1-9 is set to "H".
To Then, the bus control unit 1-7 outputs the data stored in the data buffer 1-6 when the value of the compression completion signal 1-9 is "H", and operates in the same manner as when the data is not compressed. Next, if the value of the compression completion signal 1-9 is "L", the bus control unit 1-7 sends the data αc and βc compressed by the data compression unit 1-3 to the data buffer 1-6.
, The memory 3 is requested to access, the address A is output to the system bus 5, and the compressed data supply signal 5-
3 is set to “L”, and the data αc is output. After that, when the data response signal 5-1 becomes "L", the next data βc is output. Then, the memory 3 receives the write request from the address A from the system bus 5, and receives the data response signal 5
-1 is set to "L" and the compressed data supply signal 5-3 is set to "L"
Therefore, two words of data αc and βc are fetched into the write data generator 3-5, a check bit is generated together with the value of the compressed data storage signal 3-6, and the write data α is written.
m and βm are generated. The memory control unit 3-3 is the storage element 3
-1, writing to the storage element 3-2 is performed once.
In this case, to write 4 words of data, the system bus 5 consumes 3 clocks, the microprocessor 1-1 consumes 5 clocks, and the memory 3 consumes 5 clocks. The above is the write operation when compression is performed. Needless to say, the same advantages can be obtained by using a method other than those described above as the data compression method.

[0018]

As described above, according to the present invention, data is compressed and transferred and stored for each burst transfer operation on the bus, and the presence or absence of data compression can be selected. There is an effect that data can be transferred at high speed without increasing the amount too much. By compressing and writing the data, the access time seen from the processor does not change much, but the access time of the system bus and the memory can be reduced. This has the effect of reducing bus and memory latency due to contention of other processors, since when each processor connects to a common bus, the time taken for each processor to occupy the bus and memory is reduced. .. Also, since data compression can be selected, the compression efficiency is low, and the part that frequently reads and writes is saved in the memory without performing compression processing, so that data is expanded once when a partial write occurs. Therefore, there is no need to add write data and re-compress, and it is not necessary to always compress.

[Brief description of drawings]

FIG. 1 is a block diagram showing an embodiment of the present invention.

FIG. 2 is an explanatory diagram showing a configuration example of one word stored in a memory of FIG.

FIG. 3 is a time chart for reading data, which has not been subjected to data compression, from the memory, which is used for explaining the operation of FIG. 1.

FIG. 4 is a time chart for reading the data, which has been subjected to data compression, from the memory, which is used to explain the operation of FIG.

5 is a time chart for writing data in a memory without performing data compression, which is used for explaining the operation of FIG. 1. FIG.

FIG. 6 is a time chart in the case of performing data compression and writing the data in the memory, which is used for explaining the operation of FIG.

[Explanation of symbols]

 1 Processor 1-1 Microprocessor 1-3 Data Compressor 1-4 Data Decompressor 1-5 Data Selector 1-6 Bus Buffer 1-7 Bus Controller 2 Processor 2-1 Microprocessor 2-3 Data Compressor 2- 4 data decompression unit 2-5 data selector 2-6 bus buffer 2-7 bus control unit 3 memory 3-1 and 3-2 storage element 3-3 memory control unit 3-4 read data generation unit 3-5 write data generation Department

Claims (3)

[Claims] 1. An information processing apparatus, comprising a processor and a memory, and performing a burst transfer capable of transferring a plurality of words of data in one transfer operation in data transfer between the processor and the memory. Data compression means and data decompression means capable of decompressing the data are provided between the processor and the system bus, and the data compression is performed during the write cycle of the burst transfer of the processor without activating a special data transfer cycle for the data compression and decompression. By performing data decompression during the read cycle of burst transfer, the time taken for one burst transfer operation to occupy the system bus during data transfer between the processor and memory is shortened. Data transfer method. 2. The data transfer method according to claim 1, further comprising a selection means for selecting whether or not to perform data compression when performing data transfer in a data transfer in a burst transfer operation between a processor and a memory. A data transfer method characterized by reducing the overhead of data transfer due to compression and expansion by compressing and transferring only certain data. 3. The data transfer method according to claim 2, further comprising storage means for storing whether or not data stored in a memory used in this data transfer method is compressed, and the burst transfer data is compressed data. A data storage method characterized in that by performing writing and reading without decompression, the time required for one-time data writing and data reading is shortened when the data is compressed.