JP2002318779A - Device, and access method for its register - Google Patents

Abstract

PROBLEM TO BE SOLVED: To lighten the load of processing for access on a configuration register of a PCI device and to make the processing fast. SOLUTION: The device 10 which is provided for an information processor and operates under the control of the information processor is equipped with a plurality of configuration registers 10 as registers for processing initial settings and a plurality of memory mapped IO registers 2020 as registers used for normal operation. In the address space of the memory mapped IO registers 20, the address space of the configuration registers 10 is prescribed, and the addresses of the configuration registers 10 prescribed in the address space of the memory mapped IO register 20 are specified to access the configuration registers 10.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a device such as a PCI device, and more particularly to a device for efficiently accessing various registers in the device and a method of accessing the registers.

[0002]

2. Description of the Related Art In a device device which is a peripheral device of an information processing apparatus such as a personal computer, a register for performing initialization processing may be provided separately from a register used in a normal operation. For example, PCI (Peripheral C
omponent Interconnect Bus) device, the configuration register mainly related to the initial setting,
It has a memory-mapped IO register used during normal operation.

[0003]

As described above, the conventional device such as a PCI device has the following problems.

Conventionally, a register for initial setting and a register for normal operation are respectively set in different spaces, and it is necessary to realize a plurality (two) of different access means by software or the like.

For example, in the case of a PCI device, it is necessary to access a configuration register, which is a register for initial setting, in order to collect data from an external PCI bus in debugging or the like when a failure occurs.

However, access to the configuration register, which is a register for initial setting, from the PCI bus is different from the case of the memory-mapped IO register used during normal operation, and the fixed address CONFIG_ADDR is used.
Since it is necessary to access the ESS register and the CONFIG_DATA register, in the unit dump or log dump program, it is necessary to read the contents of the configuration register by a special method different from the normal method in addition to the continuous reading of the memory mapped IO register. .

Further, the PCI device is characterized by high-speed data reading via a PCI bus by burst access to continuous addresses. However, when reading a configuration register which is a register for initial setting, a normal operation is performed. There is a problem that the burst access cannot be performed because it is different from the memory mapped IO register for time.

An object of the present invention is to solve the above-mentioned drawbacks of the prior art, to efficiently access registers for initialization and the like which are not used during normal operation, to reduce the load on the device and to increase the processing speed. It is an object of the present invention to provide a device for realizing the generalization and a method of accessing the register.

[0009]

According to a first aspect of the present invention, there is provided a device device provided in an information processing apparatus and operating under the control of the information processing apparatus. A plurality of initial setting registers, and a plurality of operating registers which are registers used during normal operation, and within the address space of the operating register, the address space of the initial setting register is defined, and the address of the operating register is defined. An address of the initialization register specified in a space is designated to access the initialization register.

As a result, the device of the present invention realizes access to the register for the initial setting in the same manner as the reading of the register used during normal operation.

[0011] According to a second aspect of the present invention, the information processing apparatus is a PCI device for connecting to a PCI bus.

According to a third aspect of the present invention, the device is characterized in that the initial setting register is a configuration register and the operation register is a memory mapped IO register.

According to a fourth aspect of the present invention, the memory-mapped IO register includes a memory-mapped IO register data selector for selecting a register to be accessed, and the memory-mapped IO register data selector includes: It is connected to the initial setting register 10, defines the address space of the initial setting register in the address space of the operation register, and accesses the initial setting register 10 via the address space of the operation register. .

According to a fifth aspect of the present invention, there is provided a method for accessing a register provided in the device of the device which is provided in the information processing apparatus and operates under the control of the information processing apparatus. A plurality of initial setting registers, which are registers for performing initial setting processing, and a plurality of operating registers, which are registers used during normal operation, include an address space of the initial setting register in an address space of the operating register. And accessing the initial setting register by designating the address of the initial setting register specified in the address space of the operation register.

According to a sixth aspect of the present invention, in the access method, the device device is a PCI device for connecting the information processing device to a PCI bus.

[0016]

Embodiments of the present invention will be described below in detail with reference to the drawings.

According to the present invention, in a device device such as a PCI device, an address space of a special register for initial setting is newly defined in an address space of a register used in a normal operation, so that the initial setting is performed. The contents of the register are accessed from the address space of the register during normal operation.

The device of the present invention will be described below with reference to an embodiment using a PCI device. FIG. 1 is a block diagram showing a configuration of a PCI device according to one embodiment of the present invention.

Referring to FIG. 1, a PCI device 100 according to the present embodiment includes a plurality of configuration registers 10 as registers for initial setting and a plurality of memory-mapped IO registers 20 as registers used in normal operation. It has.

The PCI device 100 includes means for accessing the plurality of configuration registers 10 assigned to the configuration space, such as writing and reading, and a plurality of memory maps assigned to the memory mapped IO space. A means for performing access such as writing and reading to the IO register 20 is provided.

In the present embodiment, in order to refer to the contents of a certain configuration register 10, as shown in FIG.
0 is connected to the memory-mapped IO register data selector 23 to define the unique address of the configuration space in the unique memory-mapped IO space, thereby allowing the contents of the connected configuration register 10 to be memory-mapped. Reference from an address in the IO space is realized.

The operation of this embodiment will be described below.

The PCI device 100 includes a configuration command decoder 11 for decoding commands from the PCI bus 200 and a configuration address decoder 12 for writing to each configuration register 10 allocated to the configuration space. Prepare. Then, a write command is accepted, and data is written to the specified address.

The PCI device 100 decodes a command from the PCI bus 200 to read out each of the configuration registers 10 allocated to the configuration space. The configuration command decoder 11, the configuration address decoder 12, A configuration register data selector 13 is provided. Then, the read command is accepted, and the data at the specified address is read.

Also, the PCI device 100 stores each memory-mapped IO assigned to the memory-mapped IO space.
A memory-mapped IO command decoder 21 and a memory-mapped IO address decoder 22 for decoding a command from the PCI bus 200 are provided for writing to the register 20. Then, a write command is accepted, and data is written to the specified address.

The PCI device 100 reads data from each memory-mapped IO register 20 assigned to the memory-mapped IO space by using a PCI bus 20.
It includes a memory mapped IO command decoder 21, a memory mapped IO address decoder 22, and a memory mapped IO register data selector 23 for decoding commands from 0. Then, the read command is accepted, and the data at the specified address is read.

The PCI device of this embodiment connects the output of the configuration register 10 to the memory-mapped IO register data selector 23, and defines a unique address of the configuration space in a unique memory-mapped IO space. .

Thus, the PCI device of the present embodiment specifies the access to the configuration register 10 by the address of the configuration space defined in the memory-mapped IO space. Can be referenced from a unique address in the memory-mapped IO space.

As described above, according to the PCI device of this embodiment, the memory mapped I
Using the same method as that for reading the O register, the contents of the configuration register for initial setting can be read.

Further, in the above embodiment, the device of the present invention has been described by taking the PCI device as an example. However, the device of the present invention is not limited to the PCI device. Similarly, in other device devices including a plurality of types of registers such as a register for initial setting and a register during normal operation,
Access to a register according to the invention can be implemented.

Although the present invention has been described with reference to the preferred embodiments and examples, the present invention is not necessarily limited to the above-described embodiments and examples, and various modifications may be made within the scope of the technical idea. Modifications can be made.

[0032]

As described above, according to the device of the present invention, the contents of the register for initial setting can be read using the same method as that for reading the register used during normal operation. This eliminates the need for a device driver, which was conventionally required for accessing the registers for initial settings, and eliminates the trouble of creating such a complicated program, and the processing time for unit dumps and log dumps. Can be shortened.

[Brief description of the drawings]

FIG. 1 is a block diagram illustrating a configuration of a PCI device according to an embodiment of the present invention.

[Explanation of symbols]

 Reference Signs List 100 PCI device 10 Configuration register 11 Configuration command decoder 12 Configuration address decoder 13 Configuration register data selector 20 Memory mapped IO register 23 Memory mapped IO register data selector 21 Memory mapped IO command decoder 22 Memory mapped IO address Decoder 200 PCI bus

Claims (6)

[Claims] 1. A device provided in an information processing apparatus and operated under the control of the information processing apparatus, comprising: a plurality of initialization registers which are registers for performing initialization processing; and a register used in a normal operation. Comprising a plurality of operation registers, in the address space of the operation register, defining the address space of the initialization register, specifying the address of the initialization register defined in the address space of the operation register, A device device for accessing the initialization register. 2. The device device according to claim 1, wherein the information processing device is a PCI device for connecting to a PCI bus. 3. The device according to claim 2, wherein the initial setting register is a configuration register, and the operation register is a memory-mapped IO register. 4. The memory-mapped IO register includes a memory-mapped IO register data selector for selecting a register to be accessed. The memory-mapped IO register data selector is connected to each of the initial setting registers 10, 4. The device device according to claim 3, wherein an address space of the initialization register is defined in an address space of an operation register, and the initialization register 10 is accessed via an address space of the operation register. 5. A register access method for a device provided in an information processing apparatus and operating under the control of the information processing apparatus, wherein the device includes a register for performing an initialization process. A plurality of initial setting registers, and a plurality of operating registers which are registers used during normal operation, and within the address space of the operating register, the address space of the initial setting register is defined, and the address of the operating register is defined. An access method, wherein an address of the initialization register specified in a space is designated to access the initialization register. 6. The access method according to claim 5, wherein the device device is a PCI device for the information processing device to connect to a PCI bus.