JPS6113628B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a memory specification method in a multiprocessing system when processors each having a different data bit configuration share the memory.

In a multiprocessing system, when each processor shares memory, that is, when a memory shared system is used, the data bit configuration of each processor may be different. For example, an 8-bit processor that processes data in units of 8 bits processes data exchange with peripheral equipment, and a 16-bit processor that processes data in units of 16 bits processes the main routine. In this way, for example, when an 8-bit processor and a 16-bit processor are used, the bit configuration and access contents of the shared memory are set according to one of the processors. For example, when using a shared memory with a 16-bit configuration, access contents are generally set centering around an 8-bit processor, and the contents shown in Figure 1a,
As shown in b, data such as character data A, B, . . . and control data are alternately written in the lower 8 bits at every other address. However, if the lower 8 bits of the shared memory are used in this way, the upper 8 bits of the shared memory are wasted. Furthermore, if we focus on a 16-bit processor and write character data to the lower 8 bits of the 16-bit shared memory and control data to the upper 8 bits, if the address data of the 8-bit processor is not converted, the upper bits of the shared memory will be written. There is a problem that the configuration cannot be accessed and the configuration becomes complicated. Furthermore, if the shared memory is configured as 8 bits, it is possible to eliminate wasted memory capacity, but there is a drawback that processing by a 16 bit processor becomes slower.

The present invention has been made in view of the above points, and an object of the present invention is to provide a memory specification method that can effectively utilize shared memory without reducing the processing speed of a processing device.

An embodiment of the present invention will be described below with reference to the drawings. In Figure 2, 1 has a data bit configuration of 8.
The data bit configuration of bit processors A and 2 is
This is a 16-bit processor B. The processor A1 and processor B2 are controlled by a processor controller 3.
Start and stop commands are sent from the processor controller 3 to 1 and B2. Furthermore, a signal indicating that the process is being executed is sent from the processors A1 and B2 to the processor controller 3. An 8-bit dedicated memory 5 and an 8-bit shared memory 6a are connected to the processor A1 and the processor controller 3 via an 8-bit A data bus 4a, and an 8-bit shared memory 6a is connected via a bidirectional gate G. A bit shared memory 6b is connected. In addition, the processor B2 and processor controller 3 include
A 16-bit exclusive memory 8 is connected via a 16-bit B data bus 7a, and the shared memories 6a and 6b are also connected. The memory 5, 6a,
As 6b and 8, RAM (random access memory) is used. The processor A1 is equipped with an address bus 4b that outputs, for example, 16-bit address data _AA0 to _AA15 , and the address data _AA0 to _AA7 are sent to the exclusive memory 5.
Address data AA ₁ to AA ₈ are sent to the shared memories 6a, 6b and the processor controller 3. In addition, address data AA ₉ to _{AA 15} output from processor A1 are used as control data for operation commands A-
It is sent to the decoder 9 together with VLD. This decoder 9 includes output lines 9a to 9c, and the signal output from the output line 9a is sent to the dedicated memory 5 as a chip select signal CS. Also,
The signal output from the output line 9b of the decoder 9 is input to AND circuits 10 and 11, and the signal output from the output line 9c is sent to the processor controller 3 as a status signal. Also, address data A ₀ output from processor A1
is input to the AND circuit 11 and also to the AND circuit 10 via the inverter 12. The output of the AND circuit 10 is sent to the shared memory 6a as a chip select signal CS via an OR circuit 12, and the output of the AND circuit 11 is sent to the shared memory 6b via an OR circuit 13 as a chip select signal CS. In addition, the read/write command R/W output from processor _A1 is the operation command A-
It is input together with VLD to an AND circuit 14, and the output of this AND circuit 14 is sent to the exclusive memory 5 and also to the shared memories 6a and 6b via OR circuits 15 and 19, respectively. On the other hand, processor B
2 includes 16-bit address data BA ₀ -BA ₁₅ , and the address data BA ₀ -BA ₇ are sent to the shared memories 6a, 6b, the dedicated memory 8, and the processor controller 3 via the address bus 7b. Further, the address data BA ₈ to _{BA 15} outputted from the processor B2 are sent to the decoder 16 as control data together with the operation command B-VLD. This decoder 16 is equipped with output lines 16a to 16c, and the signal outputted from the output line 16a is used as a chip select signal CS by the OR circuits 12 and 16c.
3 to the shared memories 6a, 6b, and also to the bidirectional gate G via the inverter 17 as a gate control signal. This bidirectional gate G closes the gate when the control signal is “0”,
The gate is opened when the control signal is "1". Also, the output line 16b of the decoder 16
The signal output from
The signal output from the processor controller 3 is sent to the processor controller 3 as a status signal. Furthermore, the read/write command R/
W is the AND circuit 18 along with the operation command B-VLD.
Further, it is sent to the shared memory 6b via the OR circuit 19, and also sent to the shared memory 6a via the OR circuit 15. Further, the read/write command output from the AND circuit 18 is sent to the exclusive memory 8.

Next, the operation of the present invention configured as described above will be explained. For example, the 16-bit occupied memory 8 has a third
As shown in Figure a, character data A, B, C, . . . are written in the lower 8 bits, and control data is written in the upper 8 bits. This control data is for the character data written in the lower bits, and if the character data is to be displayed on a display device, it indicates the characteristics of the character such as protect, blink, new music, graphics, etc. There is. Shared memories 6a and 6b correspond to lower bits and upper bits of exclusive memory 8, character data is written in shared memory 6a, and control data is written in shared memory 6b. Furthermore, 8-bit characters and control data are alternately written into the 8-bit exclusive memory 5 at every other address.

Therefore, processor A1 and processor B2
Starts from Proset Salon Trolla 3/
The operation is controlled by a stop command. For example, if the processor A1 starts executing a process in response to a start command from the processor controller 3, the processor A1
1 sends an execution signal to the processor controller 3 as shown in FIG. 4a. Also, from processor A1, while processing is being executed,
As shown in FIG. 4, the operation command A-VLD is output, and the use of the A data bus 4a and the A address bus 4b for the processor A1 is guaranteed as shown in FIG. 4e. Therefore, when processor A1 uses exclusive memory 5, address data AA ₉ to
Using AA ₁₅ , it outputs control data specifying the occupied memory 5 and also outputs an operation command A-VLD, which is input to the decoder 9. The decoder 9 decodes the control data and outputs a "1" signal from the output line 9a to select and designate the occupied memory 5. Further, the processor A1 outputs a read/write command R/W and inputs it to the AND circuit 14 together with the operation command A-VLD. Read/write command R/
When W is "0", it is read, and when it is "1", it is write, and the output of the AND circuit 14 specifies reading or writing of the exclusive memory 5. Further, the processor A1 outputs address data _AA0 to _AA7 via the A address bus 4b to designate an address in the exclusive memory 5. In the case of reading, the occupied memory 5 is read according to the specified address.
The contents of are sent to the processor A via the A data bus 4a.
1, and in the case of writing, the data output from the processor A1 to the A data bus 4a is written into the exclusive memory 5. and processor A
1 stops sending the execution signal to the processor controller 3 when the access to the exclusive memory 5 is completed. This causes the processor controller 3 to proceed to the next control operation.

In addition, the processor A1 uses the shared memories 6a and 6b.
If using , address data AA ₉ ~ _{AA 15}
control data specifying the shared memories 6a and 6b is output. This control data is decoded by the decoder 9, and a "1" signal is output from the output line 9b of the decoder 9. The output signal of this decoder 9 is input to AND circuits 10 and 11, and the output of one of the AND circuits 10 and 11 becomes "1" depending on the address data AA ₀ output from the processor A1, and the shared memories 6a and 6b One of them is selected and specified. That is, when address data AA ₀ is "0", the output of the inverter 12 is "1", so the output of the AND circuit 10 is "1",
Shared memory 6a is selected and address data AA ₀
is “1”, the output of AND circuit 11 is “1”
Thus, the shared memory 6b is selected and specified. When using the shared memories 6a and 6b, the processor A1 specifies addresses using address data AA ₁ to AA ₈ , and switches address data AA ₀ between "0" and "1" for the same address. By this, the shared memories 6a and 6b are alternately selected and designated. That is, when processor A1 uses shared memories 6a and 6b, character data and control data are accessed alternately as shown in FIG. 3b. When the processor A1 is accessing the shared memories 6a and 6b, the decoder 9
The processor controller 3 prohibits the processor 2 from accessing the shared memories 6a and 6b in response to the status signal output from the output line 9c. Therefore, at this time, output line 1 of the decoder 16
The signal output from 6a is “0” and inverter 1
The output of 7 is "1", and the gate of the bidirectional gate is open. That is, when the processor A1 uses the shared memories 6a and 6b, it occupies the shared memories 6a and 6b as shown in FIG. 4g.

On the other hand, when the processor B2 executes a processing operation in accordance with a command from the processor controller 3, it outputs an execution signal shown in FIG. 4b and an operation command B-VLD shown in FIG. 4d. This ensures the use of B data bus 7a and B address bus b for processor B2, as shown in FIG. 4f. Then, processor B2 uses the occupied memory 8.
When using the address data _BA8 to _BA15 , control data for using the exclusive memory 8 is output. Based on this control data, a "1" signal is output from the output line 16b of the decoder 16 to select and designate the dedicated memory 8, and access to the dedicated memory 8 is performed in the same manner as in the case of the processor A1.

In addition, the processor B2 uses the shared memories 6a and 6b.
When using the shared memories 6a and 6b, address data _BA8 to _BA15 are used. At this time, a "1" signal is output from the output line 16a of the decoder 16, and is sent to the shared memories 6a, 6b via the OR circuits 12, 13 to designate the selection. That is, processor B2 uses shared memory 6.
When accessing a and 6b, shared memory 6
a and 6b are selected and specified at the same time. When a "1" signal is output from the output line 16a of the decoder 16, the output of the inverter 17 becomes "0", the gate of the bidirectional gate G is closed, and the A data bus 4a is disconnected from the shared memory 6b. It can be done. Also,
The processor controller 3 prohibits access of the processor A1 to the shared memories 6a and 6b by the status signal outputted from the output line 16c of the decoder 16. As a result, processor B2 occupies the shared memories 6a and 6b as shown in FIG. 4g. Processor B2 then outputs address data _BA0 to _BA7 to B address bus 7b to designate the addresses of shared memories 6a and 6b. At this time, the processor B2 outputs a read/write command R/W, and data is read or written to the specified address. That is, when the processor B2 accesses, the shared memories 6a and 6b are accessed simultaneously as described above, and as shown in FIG.
Control data is read or written to.

In the above embodiment, the shared memory is accessed by 8-bit and 16-bit processors 1 and 2, but it goes without saying that the same implementation is possible even when processors with other bit configurations are used.

In addition, although the above embodiment shows the case where the shared memory is divided into two parts, when the shared memory is further divided into a large number of parts and accessed by a processing device with a large number of data bits, all or a plurality of the divided shared memories can be accessed simultaneously. You may also do so.

Furthermore, other than the processor, for example, a channel controller for direct memory access can also be implemented in the same manner as in the embodiment.

As described above, according to the present invention, when shared memory is accessed using processing devices with different data bit configurations in a multiprocessing system, the shared memory is divided according to the processing device with fewer data bits. However, when a processing device with a small number of data bits accesses, it specifies and accesses the divided shared memory individually, and when a processing device with a large number of data bits accesses, it accesses all or multiple divided shared memories at the same time. , it can be used efficiently without reducing processing speed.

[Brief explanation of drawings]

Figure 1 shows the conventional memory specification method, Figure 2 shows the conventional memory specification method.
The figure is a circuit configuration diagram showing one embodiment of the present invention, FIGS. 3a and 3b are diagrams showing access states of the shared memory in the same embodiment, and FIG. 4 is a time chart for explaining the operation of the same embodiment. It is. 1, 2...Processor, 5, 8...Occupied memory, 6
a, 6b...shared memory, 4a, 7a...data bus, 4b, 7b...address bus.

Claims (1)

[Scope of Claims] 1. In a multiprocessing system in which a shared memory is accessed using processing devices each having a different data bit configuration, means for dividing the shared memory in correspondence with processing devices having a small number of data bit configurations; When a processing device with a small number of data bits accesses the memory, there is a means to individually select and specify divided shared memory to access it, and when a processing device with a large data bit structure accesses the memory, there is a means to access all or multiple pieces of shared memory at the same time. A memory specification method characterized by comprising the following. 2. When a processing device with a small data bit configuration accesses the memory, the lower address line is used to select and designate the shared memory.
Memory method described in section.