JP3203007B2 - I / O address conversion method for virtual machines - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an I / O address conversion method for a virtual computer for maintaining compatibility of a program between different models having a plurality of different architectures in a personal computer, a workstation or the like.
The present invention relates to virtual machine hardware and a virtual machine monitor program that is control software for the hardware.

[0002]

2. Description of the Related Art In an information processing apparatus such as a personal computer (hereinafter abbreviated as a personal computer), a number of architectures exist as a result of each manufacturer expressing its uniqueness. Here, the architecture is a memory map, I /
O map, LSI used, OS function,
Refers to a BIOS function or the like. Since the configuration of these hardware and software differs between models, there is no compatibility between application software developed for each model. For this reason, the user must purchase a new device that runs the application software that he or she wants to use, or modify or port the application software to operate on a device that the user already owns.

In order to solve such a problem, on a specific model (called a base machine), another model (called a target machine) having an architecture different from that of this model.
Attempts to maintain compatibility with have been made on large computers since ancient times as so-called virtual machines. Furthermore, due to advances in LSI technology and the like, in recent years, it has been applied to the level of personal computers.

In order to realize a virtual machine on a personal computer, it is necessary to emulate at least an OS and a BIOS function call. Regarding this, Japanese Patent Application Laid-Open No. 61-184463 discloses a method of emulating a system call using a privileged instruction.

[0005] In a personal computer, application software directly accesses a display control unit in order to perform the processing at high speed. Therefore, regarding the display control unit, it is necessary to emulate the hardware of the target machine by some method. Regarding this, a method of emulating the display control unit of the target machine using the display control unit of the base machine is described in, for example, Nikkei Byte Magazine, 1987, published by Nikkei BP.
It is discussed in the January issue, pages 140-150. A method for emulating I / O by software is disclosed in Japanese Patent Application Laid-Open No. 62-279431.

Further, with respect to a display function that requires high speed, a method that eliminates the need for emulation by software by providing hardware for both a display control unit for a target machine and a display control unit for a base machine has been proposed. This is proposed in Japanese Patent Application No. 1-166631. In this application, a method is disclosed in which, when a memory area and an I / O area occupied by a display control unit of a target machine overlap with those of a base machine, they are arranged in a non-overlapping area by address conversion. For example, as shown in the I / O physical map of FIG.
It is assumed that a DMA controller of the base machine is mapped to an address area up to DFH, and an I / O of a display control unit of the base machine is mapped to address areas from 03B0H to 03DFH. On the other hand, the I / O of the original display control unit of the target machine is set to the address 00.
It is assumed that the value is C0H to 00DFH. In this case, the I / O address of the target machine display controller overlaps with the I / O address of the DMA controller. Therefore, as indicated by the broken line, the target machine display control unit is changed from the free space 01C0H to 01D
It maps to the area up to FH. In the target mode in which the application software for the target machine is operated, when the software makes an I / O access to the display control unit from 00C0H to 00DFH, the address is converted from an address from 01C0H to 01DFH to display the display hardware of the target machine. To access. As an example of the address conversion, an example of conversion by hardware and an example of conversion by software using a trap function of the CPU are disclosed.

[0007]

The above-described virtual machine realizing method is excellent in that the most important display can be realized at high speed with ease of use. However, when the free I / O address area of the base machine is smaller than the size of the I / O address area occupied by the display I / O address of the target machine, the display I / O of the target machine is reduced.
A situation arises in which an I / O address to which a unit can be allocated cannot be secured. Further, even if the I / O address can be secured, if the free I / O address of the base machine changes depending on the optional I / O adapter used by the user, the I / O address and the target machine There is a possibility that the I / O address assigned to the display I / O section of FIG.

An object of the present invention is to provide a virtual machine having target machine display hardware in which I / O addresses of the target machine display hardware can be allocated in correspondence with free I / O addresses of the base machine. An object of the present invention is to provide a / O address conversion method.

Another object of the present invention is to provide an I / O address conversion system capable of reducing an address area occupied by I / O addresses of the target machine display hardware.

[0010]

In order to achieve the above object, an I / O address conversion method for a virtual machine according to the present invention provides a virtual machine for operating an application program for a target machine on a base machine. And a second display control hardware which is a display control unit of a target machine emulated by a virtual machine monitor program, wherein the first display control hardware is a second display control hardware. Is selectively assigned to any one of the plurality of I / O address areas of the base machine, and the I / O address of the display control unit of the target machine viewed from the application program for the target machine is stored in the allocated free address area. To convert to I / O address It is. As an address conversion method for converting an I / O address of the display control unit of the target machine viewed from the application program for the target machine into an I / O address in the allocated free address area, preferably, I / O
A first address conversion method for obtaining an I / O address by adding / subtracting or multiplying / dividing a constant value to an address, and using data written in an index register assigned to a predetermined I / O address as an I / O address. At least one of the second address conversion methods is adopted.

When both the first and second address translation methods are employed, a means for inhibiting at least one address translation is provided.

Another I / O address conversion method according to the present invention is a virtual machine which runs an application program for a target machine on a base machine.
PU, first display control hardware as a display control unit of a base machine, second display control hardware as a display control unit of a target machine emulated by a virtual machine monitor program, base machine mode and target A mode switching means for switching between a machine mode and a second or first display control hardware.
Address allocating means for selectively allocating to the I / O addresses of the first and second I / O addresses, and an address for accessing the second display control hardware from the CPU in the target machine mode to the first or second I / O addresses. Address converting means for converting, and an I / O for switching selection operations of the address converting means and the address allocating means.
O map switching means.

Still another I / O address conversion method according to the present invention is a virtual machine for operating an application program for a target machine on a base machine, comprising: a first display control hardware which is a display control unit of the base machine; A second display control hardware which is a display control unit of a target machine emulated by a virtual machine monitor program, and mode switching means for switching between a base machine mode and a target machine mode;
An address generating means for generating a predetermined address; and an index register assigned to the predetermined address, wherein the predetermined address is stored when the display controller in the target machine accesses the original I / O address. An index value is selected and written into the index register, and the display control unit of the target machine is accessed using the index value.

[0014] The predetermined address of the address generating means may be variable.

In the present invention, the I / O address can be assigned to another I / O unit such as a communication control unit instead of the display control unit.

[0016]

In the virtual machine having the target machine display hardware provided on the base machine, the I / O address allocation of the target machine display hardware is made variable so that the user can obtain the free I / O address of the base machine. Even if it changes depending on the optional I / O adapter to be used, the operation is performed to allocate the I / O of the target machine display hardware to a free I / O address area. Thus, a virtual machine can be realized regardless of the optional I / O adapter used by the user.

According to the method of converting the I / O address of the display hardware of the target machine by the index method, an index register for designating the index and a data register for accessing the data are prepared. A unique index value is assigned to each of the many display I / Os. After setting the index value of the display I / O to be accessed in the index register, by accessing the data register, the I / O of the target machine display hardware can be accessed. That is, according to this method, it can be realized by occupying only two I / O addresses for the index register and the data register. If the available I / O address of the base machine is small, the I / O address of the display hardware of the target machine is converted by adding, subtracting, or multiplying / dividing a constant value including 0 to the original I / O address of the target machine. By prohibiting the address conversion system assigned to the I / O address and using the index-based address conversion system, it is possible to avoid collision with the I / O of the base machine.

When the I / O address of the display hardware of the target machine is assigned to the I / O address by the indexing method, the I / O address of the target machine is used.
By using, as an index value, a value obtained by adding, subtracting, or multiplying or dividing a constant value including 0 in an address, conversion from an original I / O address of the target machine to an index value becomes easy. Thereby, the conversion hardware or the conversion software can be simplified.

More specifically, in the address conversion method of the index system, when it is detected that the access address of the CPU is the display I / O address inherent in the target machine, first, the CPU address is converted to the I / O address of the index register. And the CPU data is converted to the display I
The value is converted to the index value assigned to / O and the first access is performed. Next, the CPU address is converted into an I / O address of the data register, and
The second access is performed using the data of. In this way, the access to the display I / O address inherent in the target machine can be converted into the access of the index system only by the hardware, and the speed can be increased as compared with the conversion by software.

[0020]

Embodiments of the present invention will be described below in detail.

FIG. 1 shows the configuration of a personal computer constituting a virtual machine as one embodiment of the present invention. In the figure, 1 is C
PU, 22 is a CPU address bus, 23 is a CPU data bus, 2 is an address bus, 3 is a data bus, 4 is a base machine display control unit, 5 is a target machine display control unit,
6 is a selector for selecting a display signal according to the operation mode and sending it to the CRT 8, 7 is a mode register for setting the operation mode of the virtual machine monitor, 9 is an address converter for performing address conversion by hardware, and 10 is a mode register 7. A mode signal which is a set value, 11 is a DMA controller, 12
Is a memory, 15 is an I / O map switching register for selecting an I / O map, 16 is an I / O map switching signal which is a set value of the I / O map switching register 15, and 17 is a user-arbitrarily built-in signal. An optional I / O adapter that can be used. The virtual machine monitor 13 and the application software 14 are located on the memory 12. The display control unit includes, for example, a CRT controller, a frame memory (image memory), and the like. Although the base machine display control unit 4 and the target machine display control unit 5 are shown separately, the parts that can be used in common can be shared.

When the application software 14 is for a target machine, the selector 6 selects a display signal from the base machine display control unit 4 in accordance with the set value of the mode register 7 set by the virtual machine monitor 13 and the address converter. 9 is CP without address conversion
The value of the U address bus 22 is output to the address bus 2 as it is.

When the application software 14 is for a base machine, the selector 6 selects a display signal from the target machine display control unit 5 according to the set value of the mode register 7 set by the virtual machine monitor 13 and an address converter. 9 performs address conversion on the value of the CPU address 22 and outputs the result to the address bus 2.

FIG. 3 shows an example of an I / O map according to this embodiment. (A) is a physical map in which the DMA controller 11 of the base machine stores data in the address area 100 from 00C0H to 00DFH.
Display I / Os (display control units) of the base machine display control unit 4 are mapped to address areas up to H, respectively. The application software 14 for the base machine is created depending on this I / O map. On the other hand, the display I / O of the target machine is originally 00C0.
If this is mapped to the address area from H to 00DFH, if this is connected to the base machine of the present example, I / O addresses will overlap with the DMA controller 11. Therefore, the display control unit of the target machine is changed to address areas 101 from 01C0H to 01DFH, which are empty areas on the base machine, and 02C.
It can be selectively mapped to any of the address areas 102 from 0H to 02DFH. FIG.
When using the optional I / O adapter 17 shown in (1), an address area that does not overlap with the I / O address of the optional I / O adapter 17 is selected from these two types of address areas. This selection is made by changing the set value of the I / O map switching register 15. 3B and 3C will be described later.

FIG. 8 shows a configuration of a part related to the present invention of the target machine display control unit 5 for selectively assigning the target machine display control unit 5 to one of the address area 101 and the address area 102. Normally, the display control unit includes a decoder 5 for decoding an I / O address.
3 and various display control registers 56 to 58 selected by the decode output of the decoder 53. Here, the decoder 53 performs I / O from 1C0H to 1DFH.
The address shall be decoded. In contrast to this configuration, in the present embodiment, when the map switching signal 16 from the I / O map switching register 15 (FIG. 1) is inactive ("0"), there are no bits A8 and A9 of the I / O address bus. Exclusive OR gates 54 and 55 are provided which function to invert both bits simultaneously when active ("1") without any change. by this,
The target machine display control unit 5 selectively includes 1C0
H to 1DFH, 2C0H
2DFH to the second address area are selectably allocated. That is, when the map switching signal 16 is “0”, the target machine display control unit 5
, And when the map switching signal 16 is “1”, it is assigned to the second address area. In this embodiment, any one of the two address areas is selectively assigned. However, it is also possible to selectively assign any one of three or more addresses.

FIG. 4 shows an example of the configuration of the address converter 9. Although the address converter 9 operates by partially adding or subtracting an address by manipulating some bits of the address bus, the address can be converted by multiplication / division. Address decoder 20, AND gate 1
9, 25, 26, an inverter 27, and exclusive OR gates 28, 29. CPU1 changes from 00C0H to 00D
Consider a case where an address within the range up to FH is accessed. Address decoder 20 decodes the address and activates decode signal 21. If the operation mode of the virtual machine monitor 13 is the base machine mode, the mode signal 10 from the mode register 7 is inactive (“0” in this example), and the address translation enable signal 24 is inactive. The A9 inverted signal 31 and the A8 inverted signal 32 of the AND gates 25 and 26 are both inactive ("0"). Therefore, in the base machine mode, the address from the CPU 1 is output to the address bus 2 without any conversion. That is, in the above example, the access by this address is to the DMA controller of the base machine.

When the target machine mode is selected, the mode signal 10 of the mode register 7 is active ("1"). At this time, when the decode signal 21 becomes active as described above, the address conversion enable signal 24 becomes active ("1"). Further, at this time, if the I / O map switching register 15 is set to select the address area 101 from 01C0H to 01DFH (in this example, the setting value is “0”), the I / O map switching signal 16 becomes inactive ("0"). As a result, the A9 inverted signal 31 output from the AND gate 25 becomes inactive (“0”), and the operation of the inverter 27 causes the AND gate 2
The A8 inversion signal 32 output from 6 is active ("1")
Becomes Therefore, of the addresses output by the CPU 1,
Only the ninth bit CA8 is inverted and output to the address bus 2. As a result, I / O shown in FIG.
In the O map, the address area 100 from 00C0H to 00DFH and the address area 101 from 01C0H to 01DFH are exchanged with each other and viewed from application software (on the CPU address bus 22).
The logical I / O map is as shown in FIG. However, in the physical I / O map on the I / O address bus 2, the address area 101 from 01C0H to 01DFH in FIG. The address on the I / O address bus 2 is led to the target machine display controller 5 shown in FIG. Now, since the I / O map switching signal 16 is "0", the I / O address is directly input to the decoder 53, and the decoder 53 decodes the I / O addresses from 1C0H to 1DFH and outputs a plurality of decoded outputs. Activate one of

Returning to FIG. 4, if the I / O map switching register 15 is set to select the address area 102 from 02C0H to 02DFH (in this example, when the set value is "1"), The / O map switching signal 16 becomes active. In this case, contrary to the above operation, the A9 inverted signal 31 output from the AND gate 25 becomes active, and the A8 inverted signal 32 output from the AND gate 26 becomes inactive. Therefore, of the addresses output by the CPU 1, only CA9 is inverted and output to the address bus 2. As a result, the logical I / O map viewed from the application software is as shown in FIG. In the target machine display control unit 5 of FIG.
Since the map switching signal 16 is "1", both the bits A8 and A9 of the I / O address bus 2 are inverted and the decoder 5
3 is input. Therefore, 0 on the I / O address bus 2
The addresses from 2C0H to 02DFH are converted to I / O addresses from 1C0H to 1DFH,
3 activates one of the plurality of decode outputs.

As described above, the target machine display control section 5 is selectively allocated to a plurality of I / O address areas, and the I / O map is switched according to the position of the free area of the I / O address of the base machine. By setting the register 16, one of the I / O address areas can be selected. At the same time, according to the setting of the I / O switching register 16, the conversion content for converting the address from the CPU 1 is switched, and the CPU address is converted to an address in the selected I / O address area. In the present embodiment, an example of address translation by hardware has been described.
Address translation using software exception processing can also be performed.

Next, another embodiment of the present invention will be described. FIG. 5A is an example of the I / O map in the present embodiment. The feature of the present embodiment is that in the first embodiment, 01
Address area from C0H to 01DFH or 02
The target machine display control unit 5, which has been mapped to the address area from C0H to 02DFH,
And the data register of 0201H is accessed. Here, as the index value used for this access, the lower 8 bits of the addresses from 00C0H to 00DFH which are the original addresses of the target machine display control unit, that is, C0H to D0H are used as they are. FIG. 5B shows the index map. The index value to be used may be determined by other methods, but the method of the present embodiment is superior in that the address conversion performed by software or hardware is facilitated.

FIG. 6 is an example in which the address converter 9 for realizing the I / O map shown in FIG. 5 is constituted by hardware. 34, 35, 36 and 37 are selectors, 33
Is an access control circuit, 39 is a CPU command signal indicating an access operation of the CPU, 40 is a command signal output to each I / O, 41 is a CPU ready signal for notifying the CPU 1 of completion of access, and 42 is an access of each I / O. Ready signal for notifying the completion of. 51 is an address 02
00H, an address generator 52 for generating an address 02
An address generator for generating 01H. These address generators 51 and 52 may be a fixed pattern of high and low level potential, but to a variable, the variable setting means such as a DIP switch or a register and a Mochiiruko it can.

FIG. 9 shows a configuration of a relevant portion of the target machine display control unit 5 suitable for the address converter 9 of FIG. In the figure, 90 is an I / O register write control circuit, 9
1, 92 are addresses 200H and 201H, respectively.
Decoder, 93 is an index register,
Reference numeral 94 denotes a decoder, and reference numerals 95 to 97 denote display control register groups corresponding to the data registers to which the address 201H is assigned.

In FIG. 6, when the CPU 1 accesses any address from 00C0H to 00DFH, the address decoder 20 decodes the address and activates the decode signal 21. If the operation mode of the virtual machine monitor 13 is the target machine mode, since the mode signal 10 is active, the address translation enable signal 24 is also active. At this time, the selector 36 and the selector 37
The outputs of the selector 34 and the selector 35 are selected, respectively. When the address conversion enable signal 24 is active, the access control circuit 33 performs an operation as shown in the time chart of FIG. Here, CPU1 is 00C
This shows a case where an access for writing 55H data to an address of 0H is made. The initial state of the second cycle signal 38 is inactive, the selector 34 selects the lower 8 bits of the CPU address bus 22, that is, C0H, and the selector 35 selects the I / O assigned to the index register 93.
O address, that is, 0200H is selected. Depending on the states of the selector 36 and the selector 37 described above, C
0H is on data bus 3 and 0200H is on address bus 2
Respectively. When the CPU command signal 39 becomes active, the access control circuit 33 issues a command 4
0 is set to active, and waits until the ready signal 42 from the target machine display control unit 5 becomes active. The target machine display control unit 5 writes the data C0H on the data bus 3 into the index register 93 in response to the decode output of the decoder 91. Therefore, when the ready signal 42 output from the I / O register write control circuit 90 is activated, the access control circuit 33 activates the second cycle signal 38. In response, selector 3
4 selects the value of the CPU data bus 23, that is, 55H, and the selector 35 selects I / O assigned to the data register.
It operates to select the O address, that is, 0201H. In this state, the command 40 is made active again, and waits until the ready signal 42 from the target machine display control unit 5 becomes active. In the target machine display control unit 5, the decode output of the decoder 92 receiving 0201H becomes active, the decoder 94 is enabled, and the contents of the index register 93 are decoded. This decoded output is supplied to the I / O register write control circuit 90.
And a logical product of the write clock output from the display control registers 95-97. In this example,
Data 55H is written to the display control register corresponding to C0H which is the content of the index register 93. Subsequently, when the target machine display control unit 5 activates the ready signal 42, the access control circuit 33 deactivates the second cycle signal 38 and
The ready signal 41 is activated to complete the access.

By the operation described above, an address different from the original I / O address in the target machine is
Moreover, I / O placed on the index format map is
Software can access using the same address as the original I / O address. Moreover, only two addresses are occupied on the base machine. The decoding contents of the decoders 91 and 92 as addresses to be assigned to the target machine display control unit 5 in FIG. 9 can be switched, and the address generators 51 and 52 in the address converter in FIG. The setting address can be variably set. With this configuration, the occupation of the I / O address of the base machine can be minimized, and the I / O address can be moved. In the present embodiment, the index register and the data register are assigned to different addresses. However, the index register and the data register may be set to the same address and toggle each time the access is made. If another I / O of the base machine has an I / O in the index format, the empty index area may be used.

The address conversion according to the second embodiment and the address conversion according to the first embodiment can be used in combination. In that case, a means for inhibiting any one of the address conversions is provided. Prohibition of address translation can be performed by disabling the decoder.

In the above-described embodiment, the I / O of the display unit has been described. However, similarly to the display control unit, the present invention can be applied to the communication I / O whose execution speed is important in the virtual machine. it can. Of course, the numerical value of the I / O address may be a value other than the above.

[0037]

According to the present invention, since the translation address can be changed according to the free address of the base machine, the I / O of the target machine can be changed even when the free address changes due to the use of an optional I / O adapter or the like.
Can be used.

Further, in the present invention, a plurality of I / Os of the target machine can be accessed from the same index register and data register as I / Os in the form of an index on the physical map. The I / O address area occupied by this can be greatly reduced.

Further, in the address conversion method according to the present invention, since the reduction of the I / O address area can be realized by hardware, there is an effect that the performance is not reduced at all.

[Brief description of the drawings]

FIG. 1 is a configuration diagram showing a first embodiment of the present invention.

FIG. 2 is a diagram illustrating an example of an I / O map in a conventional virtual machine.

FIG. 3 is a diagram illustrating an example of an I / O map according to the first embodiment of the present invention.

FIG. 4 is a diagram showing an address converter according to the first embodiment of the present invention.

FIG. 5 is a diagram illustrating an example of an I / O map according to a second embodiment of the present invention.

FIG. 6 is a diagram illustrating an example of an address converter according to a second embodiment of the present invention.

FIG. 7 is a time chart illustrating an operation of the address converter according to the second embodiment of the present invention.

FIG. 8 is a diagram illustrating an example of a target machine display control unit according to the first embodiment of the present invention.

FIG. 9 is a diagram illustrating an example of a target machine display control unit according to a second embodiment of the present invention.

[Explanation of symbols]

1 CPU, 2 address bus, 3 data bus, 4
Base machine display controller, 5 target machine display controller, 6 selector, 7 mode register, 9 address converter, 10 mode signal, 11 DMA controller, 12 memory, 13 virtual machine monitor, 14 ... Application software, 15 ... I / O map switching register, 16 ... I / O map switching signal, 17 ... I / O
Adapter, 19: AND gate, 20: address decoder, 21: decode signal, 22: CPU address bus,
23: CPU data bus, 24: Address conversion enable signal, 25: AND gate, 26: AND gate, 2
7 inverter, 28 EOR gate, 29 EOR gate, 30 I / O map switching signal, 31 A9 inverted signal, 32 A8 inverted signal, 33 access control circuit, 3
4 selector, 35 selector, 36 selector, 37
... selector, 38 ... second cycle signal, 39 ... CPU command signal, 40 ... command signal, 41 ... CPU ready signal, 42 ... ready signal, 90 ... index register write control circuit, 93 ... index register.

──────────────────────────────────────────────────続 き Continuing on the front page (72) Inventor Yukihiro Seki 292 Yoshida-cho, Totsuka-ku, Yokohama-shi, Kanagawa Prefecture Within Hitachi, Ltd. Microelectronics Equipment Development Laboratory (72) Inventor Yoshihiro Hayashi 7-1-1 Higashi Narashino, Narashino City, Chiba Prefecture No. 1 Inside the Narashino Plant, Hitachi, Ltd. (72) Inventor Masami Yamagishi 292, Yoshida-cho, Totsuka-ku, Yokohama-shi, Kanagawa Prefecture Inside the Micro-Electronics Equipment Development Laboratory, Hitachi, Ltd. (72) Toshio Tanaka, Totsuka, Yokohama-shi, Kanagawa Prefecture 292 Yoshida-cho, Ward Hitachi, Ltd. Microelectronics Device Development Laboratory (72) Inventor Masayuki Nagaoka 292 Yoshida-cho, Totsuka-ku, Yokohama-shi, Kanagawa Prefecture Hitachi, Ltd. Microelectronics Device Development Laboratory (72) Invention Susumu Onodera 292 Yoshida-cho, Totsuka-ku, Yokohama-shi, Kanagawa Prefecture Inside Hitachi Image Information System Co., Ltd. JP-A-3-33937 (JP, A) JP-A-2-195462 (JP, A) (58) Fields investigated (Int. Cl. ⁷ , DB name) G06F 13/10-13/14

Claims (1)

(57) [Claims] 1. A virtual machine operating an application program for a target machine on a base machine, comprising: first display control hardware as a display control unit of the base machine; and a target machine emulated by a virtual machine monitor program. Second display control hardware, which is a display control unit, wherein the second display control hardware is selectively allocated to any one of a plurality of I / O address areas of the base machine, and I of the display control unit of the target machine viewed from the application program
The I / O address is converted into an I / O address in the allocated free address area, and the I / O address of the display control unit of the target machine viewed from the application program for the target machine is assigned to the allocated free address. A first address conversion method for obtaining an I / O address by adding / subtracting or multiplying / dividing a constant value to / from the I / O address of the display control unit as an address conversion method for converting to an I / O address in an area; The present invention is characterized by adopting both of the second address conversion systems in which data written in an index register allocated to a predetermined I / O address is used as an I / O address, and providing means for inhibiting at least one address conversion. I / O address conversion method of a virtual machine.