JPH0969072A - Memory mapped i/o control circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To enable a machine of different architecture to freely use an I/O mapped I/O register supported only for specific machine architecture. SOLUTION: When a CPU 3 accesses a memory mapped I/O, a memory mapped address MA is passed to an address comparison part 12. The address comparison 12 compares the memory mapped address MA with a base address BA and outputs a select signal SEL when they match each other. An address mapping table 13 passes an address conversion system obtained by searching a table indicated with a table select address TA to an address conversion part 14, generates a memory I/O select signal MIS, and informs a controller 2 of which of the memory mapped I/O area and an I/O mapped I/O area the table select address TA is in. The address conversion part 14 passes a converted address CA to the controller 2 according to the address conversion system.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a memory-mapped I / O control circuit, and more particularly to a memory-mapped I / O register and I / O according to an input memory address.
The present invention relates to a memory mapped I / O control circuit having a function of accessing any of the mapped I / O registers.

[0002]

2. Description of the Related Art Conventionally, an I / O in which a CPU (Central Processing Unit) composed of one semiconductor chip is installed around the CPU
As a method for accessing a device (external input / output device), I
/ O mapped I / O access method and memory mapped I
The / O access method is known. I / O Mapped I
The I / O access method is the I / O device number (address) generated by an input / output command from the CPU, and the I / O
CPU and I / O using write and read signals to device
It exchanges data with the device and is visible when accessing from the I / O space (in the I / O device).
The / O register is called an I / O mapped I / O register. On the other hand, the memory-mapped I / O access method assigns the address of the I / O device to a part of the address area originally prepared for the main memory, and writes and reads instructions to the main memory, operation instructions, etc. The data is exchanged between the CPU and the I / O device by using the address to the main memory and the write and read signals to and from the main memory, which are seen when accessing from the memory space. I / O registers (in the I / O device) are called memory-mapped I / O registers. A feature of the memory-mapped I / O access method is that it is possible to specify an I / O device as well as a main memory by using operands such as general arithmetic logic operation instructions and transfer instructions.

By the way, this kind of I / O mapped I / O
I / O that has a fixed address (device number) and is dependent only on a specific machine architecture, despite being mass-produced in the register and expected to reduce costs
There are many types of mapped I / O registers (general-purpose chips). However, the memory space cannot directly access the I / O register, and the I / O address space cannot directly access the memory address space. As means for address translation, for example, a management unit having an address translation table is provided, as described in JP-A-2-287645, JP-A-64-84353 and the like.

[0004]

However, the prior art described in the above publication merely performs a virtual memory operation for converting a logical address into a physical address, and although conversion on a memory map is possible, There was no mechanism for automatically switching from the memory address space to the I / O address space depending on the address. For this reason,
As described above, general-purpose I / O mapped I / O registers that depend only on a specific machine architecture cannot be used on machines of different architectures.
Inconvenience had occurred.

The present invention has been made in view of the above circumstances, and allows general-purpose I / O mapped I / O registers that depend only on a specific machine architecture to be used freely even on machines of different architectures. It is an object of the present invention to provide a memory-mapped I / O control circuit according to the present invention.

[0006]

In order to solve the above-mentioned problems, the present invention according to claim 1 responds to a memory-mapped I / O access from a central processing unit, with a memory-mapped I / O register and an I / O. A memory mapped I / O control circuit for controlling a peripheral device having a mapped I / O register, wherein a base address register holding a base address in advance and a second memory address range supplied from a central processing unit. , The memory address range is compared with a first memory address range based on the base address, and if they are the same, an address comparing section which outputs a select signal and a third memory which is input from the central processing unit. I / O mapped I / O in the memory address range
An address mapping table that stores mapping information indicating whether or not an address of an area is assigned and a translation address or an address translation method of the third memory address range, and the address mapping table for the third memory address range. I / O mapped I on the table
If it is previously defined as the I / O area, the memory address input from the central processing unit is converted into the I / O mapped I / O register of the peripheral device according to the conversion address of the address mapping table or the address conversion method. And an address conversion unit for converting the address into the I / O address of the above.

According to the second aspect of the invention, in response to the memory mapped I / O access from the central processing unit,
Memory mapped I / O register and I / O mapped I /
A memory-mapped I / O control circuit for controlling a peripheral device having an O register, the base address register holding a base address in advance, and the second memory address range supplied from the central processing unit, the memory. An address comparison unit that compares the address range with a first memory address range based on the base address and outputs a select signal if the same, and a third memory address range input from the central processing unit I / O
An address mapping table storing mapping information indicating whether or not an address of the mapped I / O area is assigned, and a translation address or an address translation method of the third memory address range, and the third memory address range In the above address mapping table
If it is defined in advance as an I / O mapped I / O area, the memory address input from the central processing unit is mapped to the I / O mapped I / O of the peripheral device according to the conversion address of the address mapping table or the address conversion method. It is also defined that the third memory address range is translated into an I / O address of an I / O register, and the third memory address range is a memory-mapped I / O area or an I / O-mapped I / O area on the address mapping table. If not, it is characterized by comprising an address conversion unit for directly outputting the memory address input from the central processing unit without performing address conversion.

According to the third aspect of the invention, in response to the memory mapped I / O access from the central processing unit,
Memory mapped I / O register and I / O mapped I /
A memory-mapped I / O control circuit for controlling a peripheral device having an O register, the base address register holding a base address in advance, and the second memory address range supplied from the central processing unit, the memory. An address comparison unit that compares the address range with a first memory address range based on the base address and outputs a select signal if the same, and a third memory address range input from the central processing unit I / O
Address mapping storing mapping information indicating whether an address of the mapped I / O area is allocated or an address of the memory mapped I / O area and a conversion address or address conversion method of the third memory address range. If the table and the third memory address range are defined in advance as I / O mapped I / O areas on the address mapping table, then according to the translation address or address translation method of the address mapping table, The memory address input from the central processing unit is converted into the I / O address of the I / O mapped I / O register of the peripheral device, and the third memory address range is stored in the memory mapped I / O on the address mapping table. Predefined as a region Then, according to the address conversion method of the address mapping table, the memory address input from the central processing unit is converted into the memory address of the memory-mapped I / O register of the peripheral device, and the third memory address range is If neither the memory mapped I / O area nor the I / O mapped I / O area is defined on the address mapping table, the memory address input from the central processing unit is directly converted without address conversion. It is characterized by comprising an address conversion unit for outputting.

[0009] The invention described in claim 4 is the first invention.
The memory-mapped I / O control circuit described in 2 or 3 is characterized in that the select signal is also sent to the central processing unit.

[0010] The invention according to claim 5 is based on claim 1,
2. The memory mapped I / O control circuit according to 2 or 3, wherein the base address register, the address comparison unit, the address mapping table and the address conversion unit are configured by hardware having a flip-flop circuit and an AND circuit. Is characterized by.

[0011]

BEST MODE FOR CARRYING OUT THE INVENTION Embodiments of the present invention will be described below with reference to the drawings. The description will be specifically made using the embodiments. FIG. 1 is a block diagram showing the electrical configuration of a memory mapped I / O control circuit according to an embodiment of the present invention. Memory-mapped I / O control circuit 1 of this example
Are memory-mapped I / O registers 21a, 21b, ...
And I / O mapped I / O registers 22a, 22b, ...
Is a circuit for controlling the controller 2 as a peripheral LSI chip including the base address register 11
, An address comparison unit 12, an address mapping table 13, and an address conversion unit 14. Each of these units 11 to 14 is composed of hardware such as a flip-flop circuit and an AND circuit.

The base address register 11 is a CP
The base address BA supplied from U3 is stored and held, and also supplied to the address comparison unit 12. The base address BA is set to an arbitrary value by the CPU 3, and by not specifying the lower bits, a predetermined memory address range can be set with the base address BA as the start address. Address comparison unit 1
2 indicates whether or not the memory map address (range) MA supplied from the CPU 3 when the CPU 3 accesses the memory mapped I / O is the same as the above-mentioned memory address range with the base address BA as the start address. If a positive result is obtained by comparison, the select signal SEL is set to CP.
Output to U3 and address mapping table 13.
Here, the memory map address MA is an address that specifies the access range of the memory mapped I / O, and the memory address range can be specified by not specifying the lower bits. CPU3
Monitors the select signal SEL in order to quickly know whether the address range is an access range to the various registers 21a, 22a, ... Of the controller 2.

The address mapping table 13 is a CP
Table selection address (range) TA input from U3
Includes I / O mapped I / O registers 22a, 22b,
Stores mapping information indicating whether the address of ... Is assigned or the addresses of the memory-mapped I / O registers 21a, 21b, ... And the address conversion method of the table selection address (range) TA.
Here, the table selection address TA is an address that selects an arbitrary location within the range of the memory mapped I / O. In addition, the address conversion method is a process in which, for example, the bits of each address are exchanged or inverted so that the addresses of the I / O mapped I / O register do not collide. The address conversion unit 14 passes the converted address CA to the corresponding I / O register of the controller 2 according to the address conversion method.

Next, the operation will be described. First, when the computer system is powered on, the CPU 3 sets an appropriate base address BA in the base address register 11 according to the operation procedure of the initialization program. The set base address BA is supplied from the base address register 11 to the address comparison unit 12. Thereafter, for example, when the CPU 3 accesses the memory-mapped I / O after the application program is activated, the memory map address (range) MA is sent from the CPU 3 to the address comparison unit 12 and the address mapping table 13 is sent to the table. The selection address TA, the input address IA to the address conversion unit 14, and the data DA to the controller 2 are simultaneously supplied.

The address comparison unit 12 compares whether or not the memory map address (range) MA supplied from the CPU 3 is the same as the above-mentioned memory address range with the base address BA as the start address, and a positive result is obtained. If so, the select signal SEL is output to the CPU 3 and the address mapping table 13.

When the address mapping table 13 is supplied with the select signal SEL from the address comparison section 12, the address mapping table 13 receives the data on the table in the address mapping table 13 indicated by the table selection address (range) TA input from the CPU 3. , Memory / I / O
The selection signal MIS is generated, and the input table selection address TA is stored in the memory mapped I / O registers 21a, 2
1b, ... Or the address assigned to the I / O mapped I / O registers 22a, 22b ,. Also, the address mapping table 13 passes the corresponding address conversion method CM searched from the table to the address conversion unit 14.

For example, the table selection address TA is I / O mapped I / O on the address mapping table 13.
If the area is pre-defined, the CP is converted according to the address conversion method of the address mapping table 13.
The input address IA from U3 is applied to the corresponding I / O of the controller 2, for example, I / O of the I / O mapped I / O register 22a.
If the table selection address TA is previously defined as a memory-mapped I / O area on the address mapping table 13, it is input from the CPU 3 according to the address conversion method of the address mapping table 13. The address IA is converted into a corresponding memory address of the memory mapped I / O register 21a of the controller 2, for example, and output.
If the table selection address TA is a memory mapped I / O area on the address mapping table 13,
If it is not defined as a mapped I / O area, the input address IA from the CPU 3 is directly passed to the corresponding memory mapped I / O register 21b of the controller 2 without address conversion.

As described above, according to the above configuration, the address conversion unit 14 capable of selecting a plurality of access methods of the memory-mapped I / O and the I / O-mapped I / O for the controller 2 according to the input memory address. Since it has, it is possible to perform not only the mutual conversion of memory addresses but also the address conversion from the memory address space to the I / O address space. Therefore, the versatile I / O mapped I / O register corresponding only to a specific machine architecture can be freely used by machines of different architectures. Moreover, since it is composed of hardware, it can be converted at high speed.

The embodiment of the present invention has been described in detail above with reference to the drawings. However, the specific structure is not limited to this embodiment, and there are design changes and the like within the scope not departing from the gist of the present invention. Also included in the present invention. For example, all I / O registers on the controller side are I / O mapped I / O
Consisting of registers, 1 memory-mapped I / O register
If there is neither, the address mapping table 13
Is the I / O mapped I / O register 2 for the table selection address (range) TA input from the CPU 3.
It is sufficient if the mapping information indicating whether or not the addresses 2a, 22b, ... Are allocated and the address conversion method of the table selection address (range) TA are stored. Further, instead of the address conversion method, the converted address may be simply stored.

[0020]

As described above, according to the memory-mapped I / O control circuit of the present invention, the memory-mapped I / O is supplied to the peripheral device by the input memory address.
Since there is an address conversion unit capable of selecting a plurality of access methods for I / O mapped I / O and I / O mapped I / O, not only mutual conversion of memory addresses (in the case of the configuration according to claim 3) but also I from the memory address space is performed. Address conversion to the / O address space is also possible. Therefore, the versatile I / O mapped I / O register corresponding only to a specific machine architecture can be freely used by machines of different architectures. Moreover, since it is composed of hardware, it can be converted at high speed.

[Brief description of drawings]

FIG. 1 is a memory-mapped I / E which is an embodiment of the present invention.
It is a block diagram which shows the electric constitution of an O control circuit.

[Explanation of symbols]

1 memory mapped I / O control circuit 11 base address register 12 address comparison unit 13 address mapping table 14 address conversion unit 2 controller (peripheral device) 21a, 21b, ... Memory mapped I / O register 22a, 22b, ... I / O mapped I / O O register 3 CPU (central processing unit) BA base address (first memory address range) MA memory map address (second memory address range) TA table selection address (third memory address range) IA input address

Claims (5)

[Claims] 1. A memory-mapped I / C from a central processing unit.
A memory-mapped I / O control circuit for controlling a peripheral device having a memory-mapped I / O register and an I / O-mapped I / O register in response to an O access, the base address register holding a base address in advance. When the second memory address range is supplied from the central processing unit, the memory address range and the first memory address range based on the base address are compared, and if they are the same, a select signal is output. Address comparing unit, mapping information indicating whether or not an address of an I / O mapped I / O area is assigned to the third memory address range input from the central processing unit, and the third memory. An address mapping table that stores the translation address or address translation method of the address range; If the memory address range of No. 3 is previously defined as an I / O mapped I / O area on the address mapping table, input from the central processing unit according to the conversion address or address conversion method of the address mapping table. A memory mapped I / O control circuit comprising: an address conversion unit that converts the generated memory address into an I / O address of an I / O mapped I / O register of the peripheral device. 2. A memory-mapped I / C from a central processing unit.
A memory-mapped I / O control circuit for controlling a peripheral device having a memory-mapped I / O register and an I / O-mapped I / O register in response to an O access, the base address register holding a base address in advance. When the second memory address range is supplied from the central processing unit, the memory address range and the first memory address range based on the base address are compared, and if they are the same, a select signal is output. Address comparing unit, mapping information indicating whether or not an address of an I / O mapped I / O area is assigned to the third memory address range input from the central processing unit, and the third memory. An address mapping table that stores the translation address or address translation method of the address range; If the memory address range of No. 3 is previously defined as an I / O mapped I / O area on the address mapping table, input from the central processing unit according to the conversion address or address conversion method of the address mapping table. The converted memory address is converted into an I / O address of the I / O mapped I / O register of the peripheral device, and the third memory address range is a memory mapped I / O area on the address mapping table.
If it is not defined as an I / O mapped I / O area, an address conversion unit for directly outputting a memory address input from the central processing unit without address conversion is provided. Memory mapped I / O control circuit. 3. A memory mapped I / from a central processing unit.
A memory-mapped I / O control circuit for controlling a peripheral device having a memory-mapped I / O register and an I / O-mapped I / O register in response to an O access, the base address register holding a base address in advance. When the second memory address range is supplied from the central processing unit, the memory address range and the first memory address range based on the base address are compared, and if they are the same, a select signal is output. Whether the address of the I / O mapped I / O area or the address of the memory mapped I / O area is allocated to the address comparison unit and the third memory address range input from the central processing unit. Information indicating the mapping address and the translation address or address translation method of the third memory address range And an address mapping table storing the third memory address range is previously defined as an I / O mapped I / O area on the address mapping table, the conversion address of the address mapping table. Alternatively, according to an address conversion method, the memory address input from the central processing unit is converted into an I / O address of an I / O mapped I / O register of the peripheral device, and the third memory address range is the address mapping. If the memory mapped I / O area is previously defined on the table, the memory address input from the central processing unit is stored in the memory mapped I / O register of the peripheral device according to the address conversion method of the address mapping table. Address conversion to memory address, If the third memory address range is a memory mapped I / O area on the address mapping table, I
If it is not defined as an I / O mapped I / O area, an address conversion unit for directly outputting a memory address input from the central processing unit without address conversion is provided. Memory mapped I / O control circuit. 4. The memory mapped I / O control circuit according to claim 1, wherein the select signal is also sent to the central processing unit. 5. The base address register, the address comparison unit, the address mapping table, and the address conversion unit are configured by hardware having a flip-flop circuit and an AND circuit. 3. The memory mapped I / O control circuit described in 3.