JP2019114303A - Control chip and game machine using the same - Google Patents

Abstract

To solve a conventional problem caused by separately providing an address space of a memory and an address space of an input/output part (I/O).SOLUTION: While an address space for an I/O is independently provided in a conventional manner, a U register as hardware for designating an address of upper 8 bits to access to an incorporated device connected to the I/O is provided, and an upper address of 8 bits is designated in advance therein. Thus, it is possible to integrate an I/O address space provided separately from an address space for a memory with the address space for the memory into one address space.SELECTED DRAWING: Figure 4

Description

  The present invention relates to a security chip for controlling a gaming machine and a gaming machine incorporating the security chip.

  Initially, when a microcomputer was adopted as a security chip for controlling a gaming machine, Intel's 80 series CPU (hereinafter referred to as "80 series CPU") and Motorola's 68 series CPU (hereinafter referred to as "68 series CPU") Although each game machine maker has selected one of them in consideration of its design concept and ease of use, at present, 80 series CPUs are used as security chips for controlling game machines. It is mainstream.

  In the gaming machine, the memory capacity that can be used is restricted by a law, and the capacity of a program that can be written by a gaming machine maker called a user program is also restricted. Therefore, in order to utilize the limited program capacity more effectively, many 80 series CPU upper compatible CPUs are adopted now that follow the 80 series CPU but add more efficient instructions. The addition of such efficient instructions has become feasible due to the improvement of CPU development technology.

  Usually, when specifying addresses that require 2 bytes, the upper 1-byte address value is stored in advance in a specific register (referred to as “upper address register”), and this is stored in advance when accessing memory. Conventionally, a security chip for a gaming machine has been known which can access a memory by specifying only one lower byte while using the upper address. For example, if F0h of 1 byte is stored in the upper address register and 00h to FFh of 1 byte is specified as the lower address, F000h to F0FFh can be specified by 2 bytes, and this range Although the user RAM area of the 2-byte address can be accessed with the address, the address is practically designated by the lower 1 byte.

  FIG. 9 is a circuit diagram of a portion related to a memory and an input / output unit (I / O) of a security chip for gaming machine control based on a conventionally known 80-system CPU. Conventionally, as shown in FIG. 9, the address space of the memory 104 and the address space for the I / O 105 are provided separately. Therefore, depending on whether to access the memory address space or the I / O address space, the request signal is output from the memory request (MREQ) pin and the I / O request (IORQ) pin of the security chip, This is transmitted to the read (RD) terminal and the write (WR) terminal of the memory 104 and the I / O 105 via the logic circuit elements (gates) 107, 108, 109, 110.

Address decoders (DEC) 106 ₁ and 106 ₂ are decoders that decode address signals from the address bus, and the decoded signals are input to the chip select terminal (CS) of the memory 104 or I / O 105. Thereby, when the chip select terminal (CS) is valid, the memory 104 and the I / O 105 output the data to the data bus if the read signal (RD) is valid, and the write signal (WR) is valid. For example, the data on the data bus is written to the memory 104 and the I / O 105. Although the memory 104 and I / O 105 shown in FIG. 9 select devices by only the chip select terminal (CS) in simulation, the lower several bits (not shown) of the address bus are connected to You may specify the address of / O.

  If the address space of the memory and the address space of the input / output unit (I / O) are separately provided as in the prior art, a logic operation for selecting which address space is to be accessed, or the address space Hardware-related circuits are required to be related to the separate existence of Furthermore, although the security chip package requires pins for performing the above logic operation, it is possible to freely use more pins when developing a user program for a gaming machine. If possible, more flexible hardware implementation and program development will be possible.

  The present invention has been made based on the above circumstances, and solves the conventional problem associated with the memory address space and the input / output unit (I / O) address space being provided separately. To aim.

  In order to solve the above problems, a security chip for a gaming machine according to the present invention includes an address space for memory and an address space for input / output units (I / O), and an instruction to access each space. A security chip for a gaming machine having upward compatibility with a CPU including the above, and the address space for the input / output unit is integrated into the address space for the memory.

  The upper bits of the address specifying the address space for the input / output unit are stored in advance in the data storage device, and when specifying the input / output address space, the data of the upper bits is read from the data storage device Can be used as the upper bits to specify.

  The instruction for accessing the address space for the memory and the instruction for accessing the address space for the input / output can make all of the address space for integrated memory accessible.

  The data storage device may be a dedicated register in the CPU.

  In order to solve the above problems, a security chip for a gaming machine according to the present invention includes a first register and a second register indicating higher ranks of addresses, and the first register corresponds to a first instruction. And the second register corresponds to a second instruction, and the CPU accesses all the memory space with the first instruction and the second instruction.

  The first register is provided with a corresponding back register.

FIG. 2 is a block diagram showing a configuration of a CPU and a memory unit which are main parts of a security chip for gaming machine control according to one embodiment. FIG. 2 is a block diagram showing an internal configuration of a CPU core shown in FIG. 1; FIG. 6 is a diagram showing an internal state transition of a CPU according to an embodiment. It is the figure which showed in detail various registers contained in the register unit concerning one embodiment. 6 is a memory map of an address space including an address space for I / O according to an embodiment. FIG. 1 is a plan view of a security chip for gaming machine control according to one embodiment. FIG. 7 is a table showing names of respective pins of the security chip shown in FIG. 6 and descriptions thereof. FIG. 2 is a circuit diagram of a portion related to a CPU, a memory and an input / output unit (I / O) of a security chip for controlling a gaming machine according to an embodiment. FIG. 10 is a circuit diagram of a portion related to a CPU, a memory, and an input / output unit (I / O) of a conventional security chip for controlling a gaming machine.

  Hereinafter, an embodiment of the present invention will be described. FIG. 1 is a block diagram showing the configuration of a CPU 1 and a memory unit 4 which are main parts of a security chip for gaming machine control. The CPU 1 includes a CPU core 2 and a bus controller 3. The CPU core 2 controls the bus controller 3 with a bus control signal (Bus Cont), and reads / writes (R / W) signals and inputs / outputs with the memory unit 4. Exchange output data (Data). An interrupt / wait (INT / WAIT) signal can be input to CPU core 2, and a reset (RESET) signal can be input to CPU core 2 and bus controller 3. . Here, the memory unit 4 indicates a ROM to which a program executed by the CPU 1 is stored, a RAM used when the CPU 1 is executed, and an object to be accessed by the CPU 1 including an input / output unit (I / O).

  FIG. 2 is a block diagram showing an internal configuration of CPU core 2 shown in FIG. In the figure, the external input unit 10 receives an external signal (for example, RESET, INT, WAIT, BUSREQ, etc.) and passes it to the state control unit 11. At this time, the RESET signal is passed as an initialization signal for each unit, including the central control unit 12.

  The state control unit 11 manages the internal state transition shown in FIG. 3 to determine the operation state of the CPU core 2 and issues an actual operation instruction to the central control unit 12. The internal state transition for each instruction starts from the instruction fetch state (1) shown in FIG. 3 and the next internal state transition is determined according to the result of instruction decoding performed by central control unit 12 (for example, arithmetic processing, memory Loading, memory storage, etc.) and therefore have different internal state transitions for each instruction. Information on the state transition of each instruction is stored in the state control unit 11.

  Referring back to FIG. 2 again, the central control unit 12 reads the input data DI input from the memory unit 4 via the bus controller 3 and passes it to the instruction decoder 13, and the instruction decoder 13 analyzes the instruction. When the instruction analysis is completed by the instruction decoder 13 and the central control unit 12 passes the result of instruction decoding to the state control unit 11, the data path is executed according to the next operation instruction by the internal state transition determined in the state control unit 11. The unit 14 executes instruction operations sequentially. The sequence information of what kind of operation each instruction performs according to the result of the instruction decoding and the state instructed from the state control unit 11 is stored in the central control unit 12.

  Data path unit 14 includes a register unit 15. In the case of this embodiment, the register unit 15 has an 8-bit interrupt vector register I, a refresh register R, a 16-bit program counter PC, and a bank selector DST in addition to the two register banks of register bank 0 and register bank 1. , Bank selector SRC is included. Switching between the two register banks 0 and 1 can be made known by referring to the instruction (1 bit) of the register bank designating register RB included in the flag register F shown in FIG. 4 described later. be able to. That is, bank selector DST specifies that register bank 0 or register bank 1 stores the operation result of arithmetic logic operation unit (ALU) 16 and bank selector SRC selects source register to be input to ALU 16 as bank register 0 Select bank register 1.

  FIG. 4 shows the various registers included in the register unit 15 in more detail. As described above, register unit 15 includes two register bank 0 and register bank 1 and each register bank is an address register Q for designating the upper 8 bits of the 16 bit address for accessing the memory. (Hereinafter referred to as "Q register"), upper 8-bit address of 16-bit address for accessing built-in devices (timer, random number circuit, external input / output circuit etc.) connected to I / O (input / output unit) Register U to be specified (hereinafter also referred to as "U register"), 8-bit operation register A, flag register F (whose specific contents are shown in FIG. 4), general purpose registers B, C, D, E, H , L, 16-bit index register IX, IY, stack pointer SP, and program counter PC. Among the 8-bit registers, general-purpose registers BC, DE and HL can also be treated as 16-bit registers as a pair register.

  Furthermore, for the registers A, F, B, C, D, E, H, L, IX, IY, and Q in each register bank, these are used as front side registers, and back registers of the same configuration are provided. In the back register corresponding to each table register, the symbol “'” is attached to the same alphabet as the table register. The front side register and the back side register can be used by instantaneously selecting and replacing either of the registers with each other by a replacement instruction or the like. On the other hand, the register U and the register SP have a single configuration (without the back register). The CPU operates only on the front register of the register bank indicated by the register bank designation register RB and does not operate on the back register.

  Conventionally, as shown in FIG. 9, 256 bytes (specified by 8 bits) for accessing a built-in device connected to I / O (input / output unit) separately from the address space (memory map) for memory ) I / O address space (I / O map) was provided independently. Also, the LD instruction is provided as an instruction to access the address space for memory, and the 16-bit memory space is accessed. Furthermore, the LDQ instruction is used to access the upper 8 bits of the 16-bit address of the memory space using the Q register, and the memory space can be accessed using the 8 bits of the operand of the LDQ instruction as the lower address.

  Furthermore, conventionally, IN and OUT instructions are provided as dedicated instructions for accessing the I / O address space, and when this instruction is executed, access to the I / O address space is performed by the IORQ signal.

  On the other hand, in the present embodiment, the signals of MREQ and IORQ are eliminated and access to the memory, I / O (input / output unit) is performed by RD and WR signals, and is connected to the I / O (input / output unit). A U register is provided as hardware for specifying the upper 8-bit address for accessing the built-in device, and the upper 8-bit address is specified in advance here. As a result, the I / O address space provided separately from the memory address space is integrated into the memory address space to form one address space, and the IN instruction and OUT instruction conventionally provided are executed. Then, the upper 8 bits of the I / O mounted in the memory space are specified by the U register, and the lower 8 bits can be accessed using the lower 8 bits specified by the IN instruction and the OUT instruction operand.

  As described above, in the present embodiment, the memory space (mainly data area, work area) is accessed using the Q register in the LDQ instruction, and the internal device (timer, random number using the U register in the IN instruction and the OUT instruction). Programs can be written to access I / O of circuits, external input / output circuits, etc.). As a result, in addition to the effect of making the program easy to view, accessing the memory and I / Os located in the memory space that were originally accessing with 16-bit addresses as instruction operands with lower 8-bit operands The program capacity can be compressed. Furthermore, by having Q register, Q 'register, U register and a plurality of high-order specification registers, the number of times of replacement due to the use of high-order registers becomes smaller than when only one high-order register is used, and program capacity is further compressed. be able to.

  In the above example, the I / O is accessed by the IN instruction and the OUT instruction, but the memory space may be accessed by the IN instruction and the OUT instruction. This means that, for example, when accessing three 256-byte areas on memory, the upper 8 bits of each are designated in the Q register, Q 'register, and U register, and each area is specified by the LDQ instruction and the IN instruction OUT instruction. You may access

  FIG. 5 is a memory map including an address space for I / O, showing the address space of this embodiment. In this one memory map, in addition to the address space for the memory, a control area 37 for accessing the built-in device connected to the I / O is provided. The upper 8 bits of the 16 bits specifying the control area 37 are data previously specified in the U register. Therefore, the address of the actual built-in device is substantially designated by the lower 8 bits.

Furthermore, in the memory area shown in the memory map of FIG. 5, the "use area" in which the program for the gaming machine is arranged and the program for the gaming machine are necessary for the testing of chips defined by law. It includes "out of use area" in which a program for processing and fraud prevention is arranged. In the used area, user program area 30 (Y ₁ byte) starting from 0000h, user data area 31 (Y ₂ byte), Y _4- byte first user RAM 32 whose address starts from XXXX ₇ and Y starting with address XXXX _{9 A 5-} byte second user RAM 33 is included. The user program area 30 and the user data area 31 are composed of a non-rewritable memory such as a ROM, and the first user RAM 32 and the second user RAM 33 are composed of a rewritable memory such as a RAM.

The user program area 30 stores a program for controlling a gaming machine developed by each gaming machine maker for each gaming machine. The user data area 31 stores a data table to be referred to when the program for controlling gaming machines stored in the user program area 30 is executed. The first user RAM 32 and the second user RAM 33 are used as work areas during execution of the game machine control program stored in the user program area 30. In the case of a pachinko program, only the first user RAM 32 is used, and in the case of a pachislot program, both the first user RAM 32 and the second user RAM 33 are used. Generally, a control program for a gaming machine and an interrupt program are executed as a program for controlling the gaming machine. The first user RAM 32 and the second user RAM 33 are also used as stack areas for temporarily storing return addresses of register saving, subroutines, and interrupt processing, in addition to work areas. The initial value of the Q register is the upper 8 bits of XXXX ₇ and indicates the upper byte of the first user RAM 32, and the initial value of the Q 'register is the upper 8 bits of XXXX ₉ and indicates the upper byte of the second user RAM 33. .

Outside the use area, an external program area 34 (Y ₉ bytes) whose address starts from XXXX ₅ and an external user RAM 35 (Y ₆ bytes) whose address starts from XXXX ₁₁ are included. The external program area 34 is configured by a ROM, and the external user RAM 35 is configured by a memory that can be updated outside the use area. In the external program area 34, programs other than the control of the gaming machine for processing required for chip testing and for the purpose of preventing fraud are arranged, and the external user RAM 35 works while the program in the external program area 34 is being executed. It is used as a stack area for temporarily storing the return address of register save and subroutine as an area.

The built-in device setting area 36 is an area in which a register for setting a built-in device (timer, random number circuit, external input / output circuit, etc.) of the gaming machine control chip is arranged. The built-in device control area 37 is an area for performing access control of a built-in device for gaming machine control. As described above, the upper 8 bits of the 16-bit address for accessing this area are, for example, the upper 8 bits of XXXX ₁₅ set in advance as initial values in the U register.

  FIG. 6 is a plan view of the security chip 50 for gaming machine control according to the present embodiment, and FIG. 7 is a table showing names of the respective pins of the security chip 50 shown in FIG. As shown in FIG. 6, the security chip 50 is provided with 35 pins on the left side and 36 pins on the right side of the package body, for a total of 71 pins. When the security chip 50 is mounted on a substrate, these pins are connected to various signal lines and power supply lines provided on the substrate. A security chip for controlling a gaming machine can not regularly adopt a surface mounting part or a multilayer substrate, and it must be a DIP-shaped package as shown in FIG. Therefore, considering the strength of the package and the manufacturing process, it is the maximum number of pins that can be provided by the current 71 pins.

  Each maker of game machines develops a program for their own game machines, but the more pins that can be freely used at that time, the higher the freedom of development. However, in an actual security chip, as shown in FIG. 6, a large number (71) of pins are provided at very narrow intervals. Among these, as described above, the pins other than the pins used for the inspection become pins that can be used by game machine makers for their own effects and the like. For this reason, there has been a demand for increasing the number of pins that can be used freely for directing game machines and the like.

  FIG. 8 is a hardware circuit diagram of a portion related to the memory and the input / output unit (I / O) of the security chip for gaming machine control according to the present embodiment. In the present embodiment, as shown in FIG. 5, the I / O address space and the memory address are integrated by integrating the address space for the built-in device connected to the I / O (input / output unit) with the memory address space. The two pins of the memory request (MREQ) and the I / O request (IORQ), which are required in the conventional security chips for gaming machines, which are separate from the space, are not necessary. Therefore, two pins to which a conventional memory request (MREQ) and an I / O request (IORQ) have been allocated can be released as pins which can be used freely by a game machine maker. This increases the degree of freedom in program development among gaming machine manufacturers, and is useful for developing more advanced gaming machine programs.

  Furthermore, as in the present embodiment, by integrating the I / O address space with the memory address space, the logic circuit elements (gates) 107, 108, 109, 110 as shown in FIG. Wear is simplified and costs are reduced.

  As mentioned above, although embodiment of this invention was described, these are one embodiment to the last, the technical scope of this invention is not limited to the above-mentioned embodiment, It judges based on a statement to a claim. It should be.

1: CPU
2: CPU core 3: Bus controller 4: Memory (unit)
5: Input / output unit (I / O)
6 ₁ , 6 ₂ : Address decoder (DEC)
10: external input unit 11: state control unit 12: central control unit 13: instruction decoder 14: data path unit 15: register unit 30: user program area 31: user data area 32: first user RAM
33: Second user RAM
34: External program area 35: External user RAM
36: built-in device setting area 37: built-in device control area 50: security chip 53: second user RAM
57: Control area 101: CPU
104: memory unit 105: output unit _{(I / O) 106 1,} 106 2: an address decoder (DEC)
107, 108, 109, 110: logic circuit elements

Claims (7)

A security chip for a gaming machine having a host address space for memory and an address space for input / output unit (I / O) and having upward compatibility with a CPU having an instruction to access each space,
A security chip for a gaming machine, wherein an address space for the input / output unit is integrated into an address space for the memory.   The upper bits of the address specifying the address space for the input / output unit are stored in advance in the data storage device, and when specifying the input / output address space, the data of the upper bits is read from the data storage device The security chip according to claim 1, wherein the security chip is used as an upper bit for designating.   The security chip according to claim 1 or 2, wherein all of the integrated memory address spaces can be accessed by an instruction to access the memory address space and an instruction to access the input / output address space.   The security chip according to claim 2, wherein the data storage device is a dedicated register in a CPU.   A first register indicating a high order of an address and a second register are provided, the first register corresponds to a first instruction, the second register corresponds to a second instruction, and the CPU generates the first instruction. A security chip for a gaming machine, which accesses all the memory space with the second command and the second command.   The security chip according to claim 5, wherein the first register is provided with a corresponding back register.   A gaming machine equipped with the security chip according to any one of claims 1 to 6.

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