JPH0540694A - Cache memory device - Google Patents

Abstract

PURPOSE:To variably set block size by varying the size of a data block that is a unit to store data in cache memory by a mode switching means settable from the outside. CONSTITUTION:When the value of a mode flag 70 which designates the kind of block size of the cache memory shows '0', no change operation by an address modifier 80 is performed on an inputted address i.e., the values of bits 24-26 of an address register 30. Meanwhile, when the value of the flag 70 shows '1', the address designation of tag memory is performed by the address modifier 80 by resetting the least significant bit of the inputted address i.e., the bit 26 of the address register 30 at '0' compulsorily. Thereby, the even-numbered set of tag memory is always designated when the value of the flag 70 shows '1'. When access to the cache memory is performed, the even-numbered set of tag memory is compared 40, 41 with a real address, and data of way in which coincidence can be obtained is selected and is sent to an arithmetic part.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a cache memory device used for high speed processing of a computer.

[0002]

2. Description of the Related Art FIG. 5 is a diagram for explaining a conventional cache memory. In FIG. 5, 10 is a tag memory for holding real address information of data stored in a block of the cache memory, and 20 is main memory data. A data memory composed of blocks for storing a copy, 30 is an address register for holding an address generated for accessing data, 40 and 41 are address information read from the tag memory 10 and a real address of data to be accessed, respectively. A comparator for comparing information, 50 is a multiplexer for selecting data read from the data memory 20 based on the comparison result of the comparator 40, and 60 is for registering (writing) a new data block in the data memory 20. A memory interface that controls data transfer from a main memory (not shown) to the data memory 20. It is the interface. 2 shows the internal structure of each entry in the tag memory 10 and the data memory 20. 100 is a tag memory entry,
Reference numeral 200 indicates a data memory entry. The tag memory entry consists of address information of the data stored in the corresponding entry of the data memory and the valid bit of the entry. When valid data is stored in the data memory entry, the valid state is indicated by the valid bit. The data memory entry consists of 4 8-byte data, 3
It consists of 2 bytes. Intra-block addresses 00 to 11 are assigned to the four 8-byte data.

Next, the operation will be described. When the data processing device accesses the data on the memory, the address (virtual address in the case of the virtual memory system) is set in the address register 30 to access the tag memory 10 and the data memory 20. In the case of this example, since the number of vertical entries (called the number of sets) of the tag memory and the data memory is set to 8, the set designation is performed from bit 24 of the 32 bit address set in the address register 30. 26 bits of 3 bits. The data memory further uses bits 27-28 of the address to specify the address within the block. Further, since the number of lateral entries (called the number of ways) in the tag memory and the data memory is 2, the information for two ways is read from the addressed set. Of these, the 2-way address information read from the tag memory 10 and the real address of the data converted from the virtual address to the real address by an address conversion unit (not shown) are compared by the comparators 40 and 41, and the comparison result is shown. Send to multiplexer 50. 2 read from 2 ways of data memory 20
Of the eight 8-byte data, one of the comparators 40 and 41 corresponding to the way in which a match is detected (called a cache hit) is selected by the multiplexer 50 and sent as 8-byte data to the arithmetic unit (not shown). On the other hand, if no match is detected in any of the comparators 40 and 41 (called a cache miss), it indicates that the data to be accessed is not registered in the cache.
The data is read from the main memory (not shown), and the data is registered in either one of the designated sets. The method of designating the way to be registered is outside the scope of the present invention, and a description thereof will be omitted. The data to be registered is a continuous 32-byte data area on the main memory including the data to be accessed. 8 between main memory and memory interface 60
Assuming a byte data transfer, in order to register this 32-byte area to the entry of the data memory, the memory interface 60 fetches continuous 32-byte data from the main memory by four 8-byte data transfers and sequentially. Register to data memory entry.

[0004]

An unspecified number of application programs are executed in the data processing device. Since application programs have different processing characteristics, memory access characteristics also differ. It is known that the relationship between the block size of the data memory of the cache and the hit rate of the cache differs depending on the program because the characteristics of the memory access are different. Since the conventional cache memory device is configured as described above and the block size of the data memory is uniquely determined, there is a problem that the block size becomes inappropriate depending on the program to be executed and the performance of the cache memory deteriorates. there were.

The present invention has been made to solve the above problems, and an object thereof is to obtain a cache memory in which a block size of a data memory can be variably set. It is an object of the present invention to provide a means capable of setting a block size in.

[0006]

The cache memory device according to the present invention is provided with a flag for designating the type of block size, and by designating this flag, the structure of the cache can be changed. Furthermore, another invention makes it possible to change the setting of this flag by a program.

[0007]

In the cache memory device according to the present invention, the block size can be changed by designating the flag designating the type of the block size. Therefore, the block size is changed according to the program executed by the data processing device. Also,
In another aspect of the invention, the control program determines the properties of the application program to dynamically change the optimum block size for each application program to be executed.

[0008]

DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention will be described below with reference to the drawings. In FIG. 1, 70 is a mode flag that designates the type of block size of the cache memory, and 80 is an address modifier that modifies the address according to the designation of the flag 70 when the tag memory 10 is addressed. In FIG. 2, reference numeral 100 indicates one entry extracted from the tag memory 10 to show its contents, and 200 indicates the data memory 2.
The contents are shown by extracting one entry out of 0. FIG. 3 shows the correspondence between the designation of the flag 70 and the cache memory and the data in the main memory. 101
Is a tag entry adjacent to the tag entry 100, 201
Is a data entry adjacent to the data entry 200, 9
01, 902, 903, and 904 are data blocks in the main memory.

Next, the operation will be described. In FIG. 1, when the value of the flag 70 is "0", the address modifier 80
Does not change the input address, that is, the value of bits 24 to 26 of the address register 30. Therefore, the reference to the tag memory and the data memory is exactly the same as the conventional example. Furthermore, the method of registering block data when a cache miss occurs is exactly the same as the conventional example. FIG. 3A shows the relationship between the tag memory, data memory, and main memory data in this case. Independent blocks 901 and 902 on the main memory are tag memories,
It is registered in each adjacent entry of the data memory. Conversely, it indicates that the blocks of the main memory can be independently registered in the entries of the tag memory and the data memory.

On the other hand, when the value of the flag is "1", the address modifier 80 forcibly sets the least significant bit of the input address, that is, the bit 26 of the address register 30.
The tag memory is addressed by resetting it to 0 ", so that when the value of the flag 70 is" 1 ", the tag memory is always designated to the even numbered set and the odd numbered set is not used. The addressing of the memory 20 is the same as the conventional example, that is, the address register 30.
The even-numbered or odd-numbered set of the data memory is designated by the value of the bit 26 of. As a result, adjacent even-numbered and odd-numbered entries are paired to form one block having double the capacity. FIG. 3B shows the relationship between the tag memory, the data memory, and the data in the main memory in this case. Adjacent block 9 in main memory
03 and 904 are adjacent entries 2 of the data memory
00 and 201 are registered. On the other hand, in the tag memory, the block address is registered in the even-numbered entry 100, and the adjacent entry 101 is not used. In the case of accessing the cache in FIG. 1, even-numbered sets of the tag memory are read and the comparators 40 and 41 compare with the real address. If a match is detected on one of the two sides (cache hit), the comparison result is sent to the multiplexer 50, and the data of the matching way is selected from the data read from the data memory and sent to the arithmetic unit. At this time, the data memory is bit 24 of the address register 30.
Since the set is specified by ~ 26, either even-numbered data or odd-numbered data is read.

When a new main memory block is to be registered in the data memory due to a cache miss, the memory interface 60 is designated by the flag 70, as described in the conventional example 4.
The 8-byte data transfer (burst transfer) is performed twice consecutively. In this case, two burst transfers are performed for pairs of even-numbered and odd-numbered blocks. If the transferred data of the main memory block is an even-numbered block data sequentially, the data is transferred to the even-numbered entry of the data memory 20.
If it is odd-numbered block data, it is registered in the odd-numbered entry of the data memory.

FIG. 4 is a diagram for explaining a method of setting the flag 70. In the figure, 910 indicates a high potential (or a logical value "1"), and 911 indicates a low potential (or a logical value "0"). Reference numeral 912 is a switch, 920 is a system control device for controlling the data processing device, 921 is a control bus, and 9 is a control bus.
22 is an interface circuit with the control bus, 930 is a central processing unit (CPU) that executes programs in the data processing device, 931 is a memory bus, and 932 is an address that monitors the memory bus 931 and controls the setting of the flag 70. Decoder, 933 is a signal line. In the figure, (1) is a method of setting the flag 70 from the outside to the data processing device. (A) shows a method of setting with an external switch, and (b) shows a method of setting with a system controller. In (b), the system control device 920 sends a command for setting the flag 70 via the control bus 921. The command implementation method is not particularly limited because it is not directly related to the present invention. When the command is sent, the bus interface circuit 922 interprets it and, if it is a command for setting the flag 70, sets a value in the flag 70 according to the designation. In the method (1), the mode of the cache memory designated by the flag 70 is fixed regardless of the program execution in the data processing device.

In the figure, (2) shows a method of setting the mode of the cache memory by a program executed by the data processing device. An instruction for operating the flag 70 is defined in advance (in this example, it is assumed that the flag 70 is defined as a memory-mapped I / O and the flag 70 is operated by an input / output instruction). The flag 70 is set by executing the instruction. When the instruction of the central processing unit 930 is executed, the address decoder 932 monitoring the memory bus 931 fetches and interprets the instruction of the instruction, and sets the flag 70 based on the designation. The set flag 70 is sent to the central processing unit 930 via the signal line 933 to specify the mode of the cache memory. If this method is used, for example, when the control program of the data processing device starts the execution of the user program or the application program,
It is possible to analyze the properties of those processes in advance and change the block configuration of the cache based on the result to obtain the optimal configuration. Examples of programs with different processing characteristics include online transaction processing and large-scale scientific and technological calculations.

In this embodiment, 8 sets × 2 ways,
Although the cache memory having a 32-byte block structure has been described, a cache memory having another structure may be used. Further, when the flag 70 is set by the program of the data processing device, the flag 70 is handled as the memory mapped I / O, but the present invention is not limited to this and another implementation method may be used. Furthermore, although an example in which two types of block sizes can be selected by designating the flag 70 has been shown, a larger number of types of block sizes may be designated.

[0015]

As described above, according to the present invention, the mode flag of the cache memory is provided so that the block size can be variably set. Therefore, the cache memory can be set in accordance with the characteristics of the program executed by the data processing device. Since the block size can be changed, the utilization efficiency of the cache memory can be improved.

[Brief description of drawings]

FIG. 1 is a block diagram showing a cache memory device according to an embodiment of the present invention.

FIG. 2 is a diagram showing the contents of an entry in a tag memory and the contents of an entry in a data memory of a cache memory device according to an embodiment of the present invention.

FIG. 3 is a diagram showing a relationship among a tag memory, a data memory, and main memory data in the cache memory device according to the embodiment of the present invention.

FIG. 4 is a diagram illustrating a mode flag setting method of a cache memory, which is a feature of the invention, in a cache memory device according to an embodiment of the present invention.

FIG. 5 is a block diagram showing a cache memory device according to a conventional example.

[Explanation of symbols]

 60 memory interface circuit 70 cache memory mode flag 80 address modifier

Claims (2)

[Claims] 1. In a data processing device having a cache memory, the size of a data block, which is a unit for storing data in the cache memory, can be changed according to a designated mode by a mode switching means that can be set from outside the data processing device. Characteristic cache memory device. 2. The cache memory device according to claim 1, further comprising a mode switching unit that can be set by a program executed by the data processing device.