JPS61239339A - System for controlling transfer of page data - Google Patents

Abstract

PURPOSE:To effectively transport page data, by installing a data buffer to a storage controller between an extended storage device and CPU/channel processor and transferring the page data to the data buffer of the extended storage device through the data buffer. CONSTITUTION:Since the data transfer between a main storage device (MSU) and extended storage device (ESE) 6 is masses of page units which are continuous in the forward direction of addresses, a data buffer 27 and ESE controlling section (ESE CTL) 28 are installed to a storage controller (MCU) 2, and in the case of 'page in', a page address and start signal S are sent from the ESE CTL28 to the ESE6. The ESE6 stores data in a data buffer 61 while adding '1' to an address register (AR) 62. The ESE CTL28 of the storage controlling device 2 confirms that the data buffer 27 is not filled up with data and send a data transfer request to the ESE6 to transfer data. In the case of 'page out', the data transfer is performed after confirming that data are loaded into the data buffer 27 from the main storage device.

Description

[Detailed Description of the Invention] [Table of Contents] Overview Industrial Application Fields Conventional Technology Problems to be Solved by the Invention Means for Solving the Problems Effects of the Invention [Summary] At least the central processing unit (CPU), channel processing unit (CHP), main storage (o+sU), expanded storage (ESE).

In a computer system consisting of a storage control unit (MCU) that performs storage control and interface control between a central processing unit (CPU)/channel processing unit (CI(P)), the expanded storage device (ESE) and the main memory Equipment (MS
Focusing on the fact that data transfer to and from KI) is in page units, the expansion storage device Z, (ESE) is provided with a sufficient number of banks and a data buffer (for example, 1 page/4KB), and storage control is performed. A data buffer of a certain size (for example, 64 bytes) is provided on the device (MCU) side, and after booting the extended storage device (ESE) from the storage control device (MCU), the storage control device (MCU) MC1l)
In the ESE control unit on the side, the storage control unit (MCI
I) The data buffer on the side is not full.

Alternatively, confirm that the data has been loaded from the main storage unit (MSU) and issue a data transfer request (SYNCDATA).
By transmitting the data anew, it is possible to transfer data in units of, for example, 8 bytes.

[Industrial application field]

The present invention provides a main memory device (
MSU), and an expanded storage device (MSU) consisting of elements that sacrifice high speed to some extent due to low cost requirements.
page units (for example, 4 KB) between
This invention relates to a control method for data transfer.

With the recent onlineization of computer systems,
The construction of so-called TSS systems, in which a large number of users share and use one computer system, has become popular, and depending on the response content, slow response times from the user's perspective have become a problem. It's here.

Generally, in a TSS system, the user's memory usage area is in the file memory (DASD), and even if the fastest file memory (DASD) is used at present, the memory usage area for the user is in the file memory (DASD). Therefore, the data transfer speed is limited to a maximum of 3 MB/S.

Therefore, although the speed is slower than the main storage unit (MSU), an economical and large-capacity storage device (extended storage unit (ESE))
and set the user area as file memory (DASD).
Both of the expanded storage devices (ESE) mentioned above should have it.

Normally, data is only initially loaded from the file memory (DASD) to the expanded storage device (ESE), and subsequent data transfer between the file memory (DASD) and expanded storage device (ESE) is avoided as much as possible. Do it like this.

Therefore, data from the main storage unit (MSU) is not stored in the file memory (DASD) but in the expansion storage (one unit (ESE)).
When data stored in a certain file memory (DASD) is needed, it is read from the extended storage device (ESE), thereby reducing the response time from the user's perspective by 1! It has become possible to improve fj by two orders of magnitude.

However, access control to the extended storage device (ESE) is performed in the same way as the main storage device (MSU) due to the difference in access time and cycle time.
There are many hardware-related difficulties, and effective data transfer methods are now required.

[Conventional technology]

FIG. 5 shows an example of the system configuration of a general data processing device.
0. 3. Or the main storage device (hereinafter referred to as MSU 110 to #3) from the channel processing unit (hereinafter referred to as CHP IQ, 11) 1. Or, an access request to the expanded storage device (hereinafter referred to as ESE) 6 is
In the storage control unit (hereinafter referred to as MCU) 2, the ports corresponding to each device are accepted and then prioritized and processed. Note that the service processor (SVP) 5 is a device in charge of maintenance and operation of this system.

FIG. 6 shows the host i! in the MCU 2 in the data processing device of FIG. 2 is a block diagram showing an access control unit.

First, CPU (110, #1)3. Mataha CIIP (+1
0. #1) 4 (7) MSU (il.

~113) The access request (REQ) for 1 is accepted by the corresponding ports 21 and 22, one of them is selected by the priority circuit (P) 23, and the MSU
(110 to #3) Activate access to 1.

Control information regarding the activated access (for example, operation code, lock flag, valid bit request source point, etc.), address, and if the access is a partial write, the write data is sequentially composed of N stages of shift registers. It is held in the pipeline 240 and used to control main memory access.

If the access that started MSU (00 to #3) 1 is for FUE/7CH operation, go to 〇DR250 to MStl (
After the address for #O~113)1 is sent, after a certain timing, MSU (110~#3)1 to F
Fetch data is read through ETCHDATA 252, passes through DATA gate ERGE 254, and is sent to HCC.
After undergoing ECC check and correction processing in the FCH 253, each CPU (#O, #1) 3. C) IP (#0.l+
1) Sent to 4.

When the access that started MSII (#0-#3) 1 is a store operation, the MSU is
(#O~#3) After the address for 1 is sent, E
An ECC code is added to the store data in CCST 253, and after a certain timing, 5TORE DATA
Through 251? Sent to lSU ($0~#3)1.

When the above store operation is a partial write, the partial write data stored in the pipeline 240 is
CI (through DATA 252 +l5tl (#O~
#3) Data read from 1 and DATA MER
After being merged in GE 254, an ECC code is added in ECCST 253, and 5TORE DATA 251
It is stored in the MSU (#O~113) l through.

When the above store operation for MSU (10-#3) 1 is performed, register BII? Buffer memory (BS) in each CPU (#0.+11) 3 through 261
The invalidation processing request for each CPIJ (#0.#1)
Sent on 3rd.

Also, when a 1-bit error, etc. is detected in the above ECCFC) I253, the address is stored in the register FSAR.
260, GPBR262, each CPU (#O,
l1l)3 and operates to enter machine check interrupt processing.

The above explanation was given as an access operation to MSU (#0 to #3) 1, but as is clear from FIGS. MSII (#0 to #3) 1
The only difference is the address, access time, and cycle time.

Therefore, for data transfer from hsu (wing θ~#3) 1 to ESE 6, for example, a page transfer command is issued from CPU (#0. MStl (110~#3) 1 and ESE 6
MS ADDR250, ESE ADD
Address information is sent via R250', and F
ETCHI) The data read from the ATA 252 is transferred to the DATA MERGE 254. ECCFCH253
It was being transferred through.

Similarly, from ESE 6 to MSIJ (#0 to #3)
Data transfer to FETCHDATA 252.1. D
ATA MERGE 254. ECC5T 253,5
This was done through TORE DATA 251.

[Problem that the invention seeks to solve]

Therefore, in the conventional system, the MCU 2 has two types of information i! Devices are connected at the same location, and their access times, cycle times, and therefore busy times are different, making data transfer control complicated.

■ MStl (110~#3)1. Unpredictable "waiting" occurs in access requests to the ESH 6 due to their respective busy states, making it difficult to perform efficient data transfer.

There was a problem.

SUMMARY OF THE INVENTION The present invention overcomes the above-mentioned drawbacks of the prior art, and aims to provide a method for efficiently transferring data without being concerned with the access time, busy time, etc. of the ESE6.

[Means for solving problems]

FIG. 1 is a principle block diagram of the ESE access unit of the present invention, in which MSLI (110 to 113) 1 and ESE
Focusing on the point that the data transfer between 61 and 6 is a block of consecutive pages in the forward direction of addresses, (11ESE6 has a sufficient number of panchromatic zeros and a data buffer 4KB/page) 61, +2>MC
U2 has a data buffer 27 of a certain size (for example, 64 hides) for data transfer with the ESE 6;
ESE control unit (ESE CTL) 28, (3)
First, based on instructions from the pipeline 240, the ES
E control unit (hereinafter referred to as ESE CTI) 28 to E
When the signal S that activates access to SE 6 is sent, a data transfer request (SYNC
MStl (#0~
#3) Configure so that data transfer can be performed focusing on only one example state.

Specifically, (a) In the case of page-in (ESE=6MSU) -1) M
EsE CTL 2B of CI2 sends an access activation signal S and a page address to ESE 6.

In ESE 6, after setting the page address in the address register (AR) 62, the address register (AR) 62 is incremented by 1 and data addressed to 8 bytes is stored in the data buffer 61.

2) ESE CTL 2B in MCI2 confirms that the data in the data buffer 27 is not full, and then
Send a data transfer request (SYNCDATA) to ESE 6, taking into account E6's maximum access time.

3) In ESE6, from the data buffer 61, 8 bytes are sent to MCU 2 for one “5YNCDATA”.
The data is transferred to the data buffer 27 of.

4) The data buffer 27 of the MCI2 transfers 8 bytes of data (then the corresponding CPU port 21
Send to.

At this time, if priority (P) cannot be obtained, the MCU
The data buffer in 2 becomes full, and the above “5YNC
The transmission of DATA is interrupted.

After that, one page (4KB) of data is transferred from the data buffer 61 of ESE 6 to the data buffer 2 of MC[I 2.
The same operation is repeated until the data is transferred to 7.

(b) In the case of page out (MSU mourning ESE): ■)
Based on instructions from pipeline 240, HCIJ 2
to ESE 6, store access activation signal S
At the same time, the start address of the storage page is sent to the address register (AR) 62, and a load request is issued to MSU1.

The data fetched from MSU 1 by the load request is stored in data buffer 27 in MCU 2.

2) Every time 8 bytes of data is stored from the MSUI to the data buffer 27, the ESE CTL 2B
Sends "5YNCDATA' to the data buffer 61 of the E6, and transfers 8 bytes of data to the data buffer 61 of the ESE 6.

3) On the ESE6 side, unless the data buffer 61 is "empty", the address register (AR) 62 is incremented by 1 in the order sent from CHI 2.
Activate each bank and store the relevant data.

Thereafter, the same operation is repeated until one page (4 KB) of data is transferred from the data buffer 21 of the MCII 2 to the data buffer 61 of the ESE 6.

Therefore, (a) In case of page-in, write data for MSU 1 is always written to MCU 2.
The data will exist in the data buffer 27 of .

(b) In the case of page-out, there is always "empty space" in the data buffer 27 of MC, U2, and the data fetched from MSU 1 can be hit twice.

There is a characteristic called.

[Effect]

That is, according to the present invention, at least the central processing unit (C
PU), channel processing unit (CHP), main memory (MStl), extended storage (ESE), and storage control and central processing unit (CPU)/channel processing unit (
A storage control device (CHP) that controls the interface between
Focusing on the fact that data transfer between the extended storage unit (ESE) and the main storage unit (MSU) is in page units in a computer system consisting of a A large number of banks and a data buffer (for example, 1 page/4 KB) are provided, and a data buffer of one stroke size (for example, 64 bytes) is provided on the storage control unit (MCU) side. After starting the extended storage value W (ESE) from the device (CO), the ESE control unit on the storage control unit (MCI) side determines that the data buffer on the storage control unit (MCU) side is not full; Or main storage unit (MSU)
), and sends a data transfer request (SYNCDATA) again, allowing data transfer in units of, for example, 8 bytes. This has the effect of enabling effective data transfer with simple control, ignoring bank access time and bank busy time.

〔Example〕

Embodiments of the present invention will be described in detail below with reference to the drawings with reference to FIG. FIG. 2 is a block diagram showing an embodiment of the present invention, FIG. 3 is a diagram showing a page data transfer procedure (sequence) according to the present invention, and FIG. 4 is a page-in example. This is a time chart showing the operation when the ESE CTL 2 in FIG.
8 and data buffer 27.61. and access signal S for ESE 6, data request signal '5YNCDA
TA' are functional blocks and control signals necessary to implement the present invention.

In the following explanation, the data bus width between each device is 8 bytes, and the capacity of data byte 61 in ESE 6 is 4KB.
, the capacity of the data buffer in MCU 2 is 64 bytes.

Page data transfer related to the present invention is data transfer in units of 4 KB, and includes the following two operations.

(1) Page-in: 4K in ESEe specified by page transfer command
Move the data of B to the location within the MSUI specified by the same instruction.

(2) Page out: 4K in MSU L specified by page transfer command
Moves the data in B to the location in ESES specified by the same instruction.

In order to implement the present invention in such page data transfer processing, l! It is necessary to prepare a sufficient number of panchromatic 0s and a data buffer 61 for SE 6. That is, a) By establishing the throughput relationship (ESE access throughput ≧ MSU access C page data transfer only), MCU 2 can perform control focusing only on conflicts in MSU 1, and b) In a page-in operation, ESIE 6 uses data buffer 6 regardless of the state of MStl 1.
1 can be read continuously wE.

Also, the data buffer 27 in MCU 2
For data transfer between gEsEs, this has the effect of eliminating any negative impact on MSU 17 access (due to page data transfer).

The page data transfer when the present invention is implemented will be described below, focusing on the page data transfer sequence shown in FIG. 3, with reference to the block diagrams shown in FIGS. 1 and 2, and the time chart shown in FIG. Explain the operation.

(1) For page-in (ESE-OMSU) operation: ■
CP fetch request from CPU 1 to ESE 6
When the U-boat 21 is connected, the CPU boat 21 = 6 priority circuit (P) 23) pipeline 240 = OE
SE CTL 2B, propagates the access, and in the process performs an address exception check for ESE 6;
If there is no address corresponding to ESE 6, then CP
II I and terminate the process.

(2) Next, when a store request from CPU 1 to MSU 1 is accepted, an address exception check for MSU 1 is performed in the same manner.

■ After confirming that there are no address exceptions in both ■ and ■,
The ESE CTL 28 activates a fetch access ([!SE RE port) S to the ESE 6 and sets a page address (ESS! ADDR) in the address register (AR) 62.

In ESE 6, upon receiving the fetch request S,
The process currently being executed, for example, the patrol process, etc. is interrupted, the state is set to ESE BANK GO, and data transfer from Panchrome 0 to the data buffer 61 is started. At this time, each time 8 bytes of data is transferred, the address register (AR) 62 is incremented by 1, and the separately provided bank counter (BANK CT) is also incremented by 1.
be done. (See Figure 4, ■)■ ESE CTL 2
8 starts the fetch access and sends a data transfer request '5YNCDATA' to ESE 6 after a certain period of time T (specifically, ESE access time x 2).
The corresponding 8-hide data will be displayed after 3 machine cycles.
Loaded into data buffer 27 of MCU 2.

This data transfer is continued until the data buffer 27 reaches 32 bytes, and is interrupted when it exceeds 32 bytes.

After the interruption, even if there is a data transfer request "5YNCDATA" that has already been sent to ESE 6, the capacity of the data buffer 27 is 64 because there is a lag of 3 machine cycles.
It never exceeds a part-time job.

Further, the above-mentioned interruption determination may be made, for example, when the datum, buffer 2
This can be done by calculating the values of the in pointer and out pointer provided in 7.

The data loaded into the data buffer 27 of the MCU 2 is sequentially set in the store data register (WD) (not shown) of the corresponding CPU boat 21, and a store access (MSU GO, MSU WD) to the old U1 is activated. .

Although this store access to MSU 1 is not shown, it is performed while changing the address of the CPU boat 21 by +8'.

If the above store access to MSU 1 is made to wait by another boat, data transfer between the MCU 2 and ESE 6 may be interrupted, but if the contents of the data buffer 27 of U2 become less than 32 hides. At that point, the interruption is lifted and data transfer occurs again.

When the data transfer request "5YNCDATA" is sent 512 times, the page-in process ends. (See Figure 4, ■) ■ When the operations from ■ to ■ above are completed, the CPU poll
21, and ESE CTL 2B are released from the busy state, and the result of the page-in process is reported to the CPIJ 1.

(2) In case of page out (MSU Naka ESE) operation:
■~■ are the same operations except that the store/fetch in (1) is reversed.

■ ? 'fetch access to lSU 1 from CP
[Start up sequentially while changing the address of I port 21 by '+8''.

The data read from MSU 1 is l'lcU 2
The data is loaded into the data buffer 27 of the ESE 6, and at the same time the data transfer request '5YNCDATA' is sent to the ESE 6, the data is sent to the data buffer 61 of the ESE 6.

On the ESE 6 side, as described above, unless the data buffer 61 is "empty", the address register (
AR) While adding 1 to 62, activate each bank and store the data.

When the number of fetch accesses to MSU 1 reaches 512, the page-out process ends.

■ Same as ■ in (1).

In this way, in the present invention, from MCU 2 to ESE
After a certain period of time T after sending the access activation request S to
Simply send a data transfer request '5YNCDATA' to the ESE 6 each time 8 bytes of data is loaded into the ESE 6.
The feature is that page data transfer is performed between MSU1 and ESH6.

〔Effect of the invention〕

As described above in detail, the page data transfer control method of the present invention is implemented by at least the central processing unit (CPU).
, channel processing unit (CHP), main memory (iSO
), an expanded storage device (ESE), and a storage control unit 01CU) that controls the interface between storage control and a central processing unit (CPU)/channel processing unit (CHP). Focusing on the fact that data transfer between the ESE) and the main memory (1'1sU) is in page units, it is necessary to provide a sufficient number of banks for the extended storage (ESE) and a data buffer (for example, 1 page/1sU). 4 KB), and a data buffer of a certain size (for example, 64 bytes) is provided on the storage control device (MC1l) side. II
After booting the extended storage device (ESE) from the I device (4GO), the ESE on the storage control unit ICU)
The control unit checks that the data storage on the storage control device (MCIJ) side is not full or that the main storage device (MCIJ) is not full.
By confirming that the data has been loaded from '1slI) and sending the data transfer request (SYNCDATA) again, it is possible to transfer data in units of, for example, 8 hides. This has the effect of enabling effective data transfer with simple control, ignoring the access time on the ESE side and the busy time of the bank.

[Brief explanation of drawings]

FIG. 1 is a principle block diagram of the ESE access section of the present invention. FIG. 2 is a block diagram showing an embodiment of the present invention. FIG. 3 is a diagram showing a page data transfer sequence according to the present invention. FIG. 4 is a time chart showing the operation when page-in is performed by implementing the present invention. FIG. 5 is a diagram showing the system configuration of a general delta processing device. FIG. 6 is a block diagram showing a main memory access control section according to the prior art. It is. In the drawings, 1 is a main storage device (MSUIIO~#3). 2 is a memory control unit (MC port). 3 is the central processing unit (CPU $1011). 4 is a channel processing device (CHP #O, #1). 21 and 22 are main memory access request ports. 23 is a priority circuit (P), and 240 is a pipeline. 27 is a data buffer, 28 is an ESE control unit (ESE
CTL). 6 is an expanded storage device (ESE), and 60 is a bank. 61 is a data buffer. 62 is an address register (AR). ■～■ are each processing step of page data transfer. 5E ESE Ata Women's Club Girl's Club Balloon 7 [J Stem/g

Claims (1)

[Claims] At least a central processing unit (CPU) (3), a channel processing unit (CHP) (4), a main storage unit (MSU) (1)
), an expanded storage device (ESE) (6), and a storage control unit (MCU) that performs storage control and interface control between a central processing unit (CPU)/channel processing unit (CHP) (
2), the main storage unit (MSU) (1) and the expanded storage unit (ES
E) (6) To perform page-by-page data transfer between the extended storage device (ESE) (6) and the storage control device (6),
MCU) (2), data buffers (61,
27) and sends access requests to the expanded storage device (ESE) (6) into two types: a startup request (S) to the expanded storage device (ESE) (6), and a data transfer request (SYNC DATA). A page featuring the following:
Data transfer control method.